KR20080114182A - Semiconductor dvice and method for manufacturing of the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided to obtain advantages in a self aligned contact by decreasing an aspect ratio between gates by reducing the height of the gate in a cell region and to prevent a gate pattern defect due to the residue of a gate conductive layer by omitting a patterning process of the gate conductive layer in the cell region. A semiconductor device includes a substrate(51), a recess pattern(53), a first gate, and a second gate. The substrate includes a cell region and a peripheral circuit region. The recess pattern is formed in the substrate of the cell region. The first gate is reclaimed in the recess pattern. The second gate is positioned on the substrate of the peripheral circuit region. The firs gate and the second gate include a gate conductive layer and a gate metal layer respectively.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DVICE AND METHOD FOR MANUFACTURING OF THE SAME}

1 is a cross-sectional view showing a gate of a semiconductor device manufactured according to the prior art.

2 is a cross-sectional view illustrating a gate formed in a dense region and a small region of a semiconductor device according to an exemplary embodiment of the present invention.

3A to 3L are cross-sectional views of a process for forming gates in the dense and dense regions of a semiconductor device.

Explanation of symbols on the main parts of the drawings

51 substrate 52 device isolation film

53 recess pattern 54, 60 gate insulating film

55, 61A, 61B: gate conductive film

56, 62: diffusion barrier film 57, 63: gate metal film

58, 64 gate hard mask layer

59, 65: Gate spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device having a recessed channel gate (hereinafter referred to as a recessed gate) and a method of manufacturing the same during a semiconductor device manufacturing process.

In the DRAM (Dynamic Radom Access Memory) device, which is a typical semiconductor device, a recess gate is formed in a cell area to solve a short channel effect. In the peripheral circuit area, gates are manufactured in a planar shape, and as the degree of integration increases, a method of manufacturing a dual gate has become common.

1 is a cross-sectional view showing a gate of a semiconductor device manufactured according to the prior art.

Referring to FIG. 1, a recess gate RG is formed in a dense region, eg, a cell region CELL, of a semiconductor device, and an NMOS gate NG and a PMOS gate PG are formed in a dense region, eg, a peripheral circuit region PERI. ) Is formed.

The gates RG, NG, and PG have the same height from the surface of the substrate 11, which includes the gate conductive film 13, the diffusion barrier 14, and the gate in the cell region CELL and the peripheral circuit region PERI. This is because the metal layers 15 and the gate hard mask layer 17 are sequentially formed and then patterned to form respective gates RG, NG, and PG.

Meanwhile, with the recent increase in the degree of integration of semiconductor devices, the laminated gate pattern of the gate metal film 15 / gate conductive film 13 may act as an RC delay due to the high sheet resistance due to the decrease in the line width of the gate pattern. Can be. In order to solve such a problem, the thickness of the gate metal film 15 should be increased.

However, when the thickness of the gate metal film 15 is increased, a bridge phenomenon between the landing plug and the gate conductive layers 13 to 15 may be caused by the high aspect ratio between the gate patterns 13 to 17.

Therefore, there is a need for a technique capable of effectively forming a landing plug while increasing the thickness of the gate metal film 15.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and a first object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which reduce the specific resistance by adjusting the formation height of the gate metal film.

It is also a second object of the present invention to provide a semiconductor device and a method of manufacturing the same, which provide an easy self-aligned contact process by reducing the aspect ratio between gates in a dense area.

According to an aspect of the present invention for achieving the above object, a substrate including a cell region and a peripheral circuit region, a recess pattern formed in the substrate of the cell region, a first gate embedded in the recess pattern and the peripheral circuit A semiconductor device comprising a second gate on the substrate in a region is provided.

Further, according to another aspect of the invention, providing a substrate comprising a cell region and a peripheral circuit region, forming a recess pattern by etching the substrate of the cell region, a first surface on the surface of the recess pattern Forming a gate insulating film, embedding a first gate conductive film in the recess pattern, forming a second gate insulating film on a substrate in the peripheral circuit region, and forming a second gate conductive film on the second gate insulating film. Forming a gate metal layer in the cell region and the peripheral circuit region; and etching the gate metal layer and the first and second gate conductive layers to form a plurality of first gate patterns in each of the cell region and the peripheral circuit region. And forming a second gate pattern.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a cross-sectional view illustrating a gate formed in a dense region and a small region of a semiconductor device according to an exemplary embodiment of the present invention. Here, the dense area is an area in which a plurality of gates are densely gathered. In the embodiment, the cell area is taken as an example. The dense area is an area in which a plurality of gates are densely gathered. In the embodiment, the peripheral circuit area is taken as an example.

Referring to FIG. 2, a recess gate RG having a recess channel is formed in the cell region CELL, and an NMOS gate NG and a PMOS gate PG having a flan channel are formed in the peripheral circuit region PERI. Is formed.

The recess gate RG is formed in a stacked structure of the gate insulating film 54, the gate conductive film 55, the gate metal film 57, and the gate hard mask layer 58. The recess gate RG is partially embedded in the recess pattern 53 of the substrate 51.

In detail, the gate insulating film 54 and the gate conductive film 55 are embedded in the recess pattern 53, and the remaining gate metal film 57 and the gate hard mask layer 58 protrude onto the surface of the substrate 51. . Alternatively, the gate metal layer 57 may be embedded in the recess pattern 53, or may be embedded in the gate hard mask layer 58.

The gate metal film 57 is formed to lower the gate resistance because the gate conductive film 55 alone has a high gate resistance. In addition, the gate hard mask layer 58 is positioned on the recess gate RG to prevent breakage of the recess gate RG in a subsequent etching process. In addition, a gate spacer 59 may be formed to protect sidewalls of the gate patterns 55 and 57 to 59, and a diffusion barrier 56 may be interposed between the gate conductive layer 55 and the gate metal layer 57. have.

A void may be formed in the gate conductive layer 55 of the recess gate RG, and the void may contact the gate insulating layer 54 to cause a shortening of the channel. To solve this problem, the gate conductive layer 55 is doped with a high concentration of impurities. Preferably, a high concentration of impurities are doped into the gate conductive film 55 adjacent to the gate insulating film 54.

The gate insulating layer 54 is formed of pure SiO ₂ having excellent GOI (Gate Oxide Integrity) characteristics. The GOI characteristic refers to the quality of the gate oxide film, and is expressed as a voltage (BV, breakdown voltage) when the leakage current becomes a breakdown current while increasing the voltage.

Subsequently, the NMOS gate NG and the PMOS gate PG of the peripheral circuit region PERI are formed on the substrate 51 by the gate insulating film 60, the gate conductive films 61A and 61B, the gate metal film 63, and the like. The stack structure of the gate hard mask layer 64 includes a gate spacer 65 for protecting these sidewalls. In addition, a diffusion barrier 62 may be interposed between the gate conductive film 61 and the gate metal film 63. N-type impurities are doped in the gate conductive film 61A of the NMOS gate NG, and P-type impurities are doped in the gate conductive film 61B of the PMOS gate PG.

The gate conductive films 55, 61A, and 61B of the respective gates RG, NG, and PG may be, for example, polysilicon films, and the gate metal films 57 and 63 may be, for example, any of transition metals and rare earth metals. It may be formed of one or a laminated film thereof.

Comparing the height of the recess gate RG having such a structure and the NMOS gate (NG, the description of the PMOS gate having the same height as the NMOS gate is omitted), the height H1 of the recess gate RG is NMOS. It can be seen that it is lower than the height H2 of the gate NG.

The formation height H1 of the recess gate RG is low, and the height of the gate conductive film 55 of the recess gate RG and the gate conductive film 61A of the NMOS gate NG is greater than the surface of the substrate 51. This is because the standard is different. That is, the gate conductive film 55 of the recess gate RG is buried in the recess pattern 53 so that the region exposed to the recess pattern 53 is at least the gate conductive film 61A of the NMOS gate NG. Because it is lower than the height of.

As such, when the height of formation of the recess gate RG in the cell region CELL is reduced, a landing plug contact hole formed in a subsequent process may be easily formed. This is because the aspect ratio between the plurality of recess gates RG is lowered. In addition, the thickness of the gate metal layers 57 and 63 may be efficiently increased due to the lower aspect ratio between the plurality of recess gates RG.

In summary, in the cell region having a high density, the aspect ratio between the recess gates RG is reduced, and the landing plug can be easily formed. In addition, the height of the gate metal film 57 can be increased by decreasing the projecting height of the gate conductive film 55, so that the gate resistance can be reduced. However, the increased thickness of the gate metal film 57 should take into account the aspect ratio between the recess gates RG.

In addition, although the embodiment has described the recess gate RG, the bulb-type recess gate or the polygon recess gate may have the same advantages as described above.

Subsequently, the gate according to the embodiment of the present invention shown in FIG. 2 is formed in the following manner.

3A to 3L are cross-sectional views illustrating a process of forming a gate in a dense region and a dense region of a semiconductor device. Here, the dense area is an area in which a plurality of gates are densely gathered. In the embodiment, the cell area is taken as an example. The dense area is an area in which a plurality of gates are densely gathered. In the embodiment, the peripheral circuit area is taken as an example.

As shown in FIG. 3A, after forming the device isolation layer 102 on the semiconductor substrate 101 in which the cell region CELL and the peripheral circuit region PELI are separated, the recess pattern 104 is formed.

The device isolation film 102 has a small area and is formed by a shallow trench isolation (STI) method having excellent insulation characteristics. The recess pattern 104 has a line shape and is formed as a pad layer pattern 103.

The pad layer pattern 103 may be an insulating film having a stacked structure of three layers. For example, an oxide film (SiO ₂ ) having a thickness of 5 to 100 GPa formed by an oxidation process as a first insulating film, a silicon nitride film (Si ₃ N ₄ ) having a thickness of 50 to 300 GPa as a second insulating film, and a thickness of 100 to 100 It can be formed of a silicon oxide film (SiO ₂ ) or a silicon oxynitride film (SiON) of 2000 kV.

Subsequently, the substrate 101 is etched using the pad layer pattern 103 as an etch barrier to form the recess pattern 104. The etching of the substrate 101 may be performed by at least one selected from the group consisting of a fluorine (F) -based gas such as CF ₄ , CHF ₃ , NF _3, or CCl ₄ gas. Alternatively, the wet etching process may be performed.

The depth of the recess pattern 104 formed in this way is 100 ~ 3000Å, the shape may be polygonal, for example, circular, U-shaped, square or bulb-shaped. In addition, the bottom surface of the recess pattern 104 may be further formed with a fin-like protrusion.

Subsequently, an oxidation process is performed to form a first gate insulating film 105 on the surface of the recess pattern 104. The first gate insulating film 105 is formed of a pure oxide film (SiO ₂ ) having a thickness of 30 to 200 Å.

Subsequently, the first gate conductive film 106 is formed to fill the recess pattern 104.

The first gate conductive film 106 may be a polysilicon film doped with an N-type impurity, such as phosphorus (P) or arsenic (As), or may be phosphorus or arsenic through ion implantation after forming an undoped polysilicon film. Can be doped.

In addition, since the aspect ratio of the recess pattern 104 is high, a seam may be formed in the first gate conductive film 106. In order to prevent the seam from moving, the first gate conductive film 106, preferably The dopant is doped with a high concentration of impurities in the first gate conductive film 106 adjacent to the first gate insulating film 105. To this end, the first gate conductive film 106 may be deposited several times, and the concentration of impurities may be 4E20 / cm ² to 5E20 / cm ² . And it is preferable that the thickness of a polysilicon film is 50-2000 kPa.

As shown in FIG. 3B, the planarization process is performed to fill the recess pattern 104 with the first gate conductive film 106A. At this time, a part of the pad layer pattern 103A is also recessed.

This planarization process can proceed in two steps.

First, first planarization is performed such that the first gate conductive film 106 formed on the pad layer pattern 103 is removed. The second planarization planarizes the second insulating film in the pad layer pattern 103 with the polishing stop film. Examples of planarization include chemical mechanical polishing and etch back.

As shown in FIG. 3C, the first cell gate protective layer 107 is formed on the cell region CELL of the resultant planarization.

The first cell gate protective layer 107 is a protective layer formed to protect the cell region CELL when the gate conductive layer is formed in the peripheral circuit region PERI, and uses an oxide layer or a nitride layer as a single layer or a stack. Here, the thickness of the oxide film is 10 to 200 kPa, the thickness of the nitride film is 10 to 500 kPa, and may be formed of a polysilicon film instead of the nitride film.

As shown in FIG. 3D, a second gate insulating film 108 is formed on the substrate 101 of the peripheral circuit region PERI.

A second gate insulating film 108 may be an oxide film (SiO ₂₎ or an oxide film (SiO ₂₎ formed by oxidizing the substrate 101, nitride (nitridation) to a silicon oxynitride film (SiON) is formed. When the silicon oxynitride film is used, P-type impurities doped in the gate conductive film may be prevented from penetrating into the substrate 101.

The second gate insulating film 108 may be formed in multiple layers, such as dual or triple, and may include hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), and radium instead of oxide (SiO ₂ ). Oxide (La ₂ O ₃ ), Hafnium Silicon Oxide (HfSiO), Zirconium Silicon Oxide (ZrSiO), Radium Oxide Nitride (LaON), Hafnium Silicon Oxide Nitride (HfSiON), Zirconium Silicon Oxide Nitride (ZrSiON) and Radium Silicon Oxide Nitride (La LaSiON) and at least one selected from the group consisting of. For example, it may be a laminated structure of a hafnium oxide film and a zirconium oxide film.

Subsequently, a second gate conductive film 109 is formed on the substrate 101 including the second gate insulating film 108.

The second gate conductive film 109 is formed of a polysilicon film, and may be a polysilicon film doped with phosphorus (P) or arsenic (As), and after the formation of the undoped polysilicon film, an ion implantation process may be performed. Phosphorus or arsenic can be doped. And it is preferable that the thickness of a polysilicon film is 100-2000 kPa.

As shown in FIG. 3E, the second gate conductive layer 109 is partially etched to remain only in the peripheral circuit region PERI. Thereafter, the first cell gate protective layer 107 is removed.

As shown in FIG. 3F, an ion implantation mask 110 exposing only the PMOS region PMOS of the peripheral circuit region PERI is formed, and the second gate conductive layer 109A of the PMOS region PMOS is formed using the ion implantation mask 110. P-type insolubles such as boron (B) are ion-implanted.

The ion implantation mask 110 uses a photoresist layer, and the dose of boron (B) is preferably 3E15 to 3E16 / cm ₂ . Alternatively, a boron compound containing fluorine or hydrogen in boron (B) may be used.

After the ion implantation process, the ion implantation mask 110 is removed.

Subsequently, an annealing process is performed to activate impurities.

The annealing process is preferably performed for a process temperature of 700 ~ 1100 ℃ and a processing time of 5 seconds ~ 60 minutes.

As shown in FIG. 3G, the diffusion barrier layer 111, the gate metal layer 112, and the gate hard mask layer 113 are sequentially formed on the resultant annealing process.

The pretreatment cleaning process may be performed before the diffusion barrier 111 is formed.

There pre-cleaning process can proceed to the wet or dry, for example, liquid was diluted (diluted) HF or diluted BOE (bufferd oxide etchant, HF and NH ₄ F 100: a solution mixed in a 1: 1 or 300 Solution may be used, and the dry process may be carried out by an in-situ plasma cleaning process.

The diffusion barrier 111 is a thin film including at least one selected from the group consisting of titanium (Ti), tungsten (W), silicon (Si), and nitrogen (N), and may be, for example, a tungsten film containing nitrogen. .

The gate metal film 112 is at least one selected from the group consisting of tungsten film W, molybdenum film Mo, cobalt film Co, copper film Cu, platinum film Pt, and ruthenium film Ru. It may be formed, for example, may be a laminated structure of a tungsten film / cobalt film.

The gate hard mask layer 113 may be at least one selected from the group consisting of a nitride layer (Si ₃ N ₄ ), an oxide layer (SiO ₂ ), a silicon oxynitride layer (SiON), SiCN, SiC, and SiOC. It may be a laminated structure of a nitride film and an oxide film. And, the thickness may be 200 ~ 3000Å.

As shown in FIG. 3H, a primary gate pattern is formed in the cell region CELL, the PMOS region PMOS, and the NMOS region NMOS by using a gate patterning mask.

Only the first gate pattern is etched up to the diffusion barrier layer 111A, and only a portion of the second gate conductive coating layer 112A and the pad layer pattern 103A below it is etched. In detail, the pad layer pattern 103B of the cell region CELL is etched by about 10 to about 100 microseconds, and the second gate conductive film 119 of the peripheral circuit region PERI is about 10 to about 200 microseconds.

As shown in FIG. 3I, a capping layer 114 is formed on the resultant formed with the primary gate pattern.

The capping layer 114 protects the cell region CELL in the separation process of the second gate conductive layer 119 connected to each other, and prevents the diffusion barrier 111A from being oxidized.

As the capping film 114, a nitride film can be used, and the thickness thereof is preferably 20 to 200 kPa.

Subsequently, the second cell gate protective layer 115 is formed on the cell region CELL of the resultant in which the capping layer 114 is formed.

The second cell gate protective film 115 may be formed of at least one selected from the group consisting of an oxide film (SiO ₂ ), a spin on glass (SOG) film, a boron phosphorus silicalicate glass (BPSG) film, or an amorphous carbon film. There may be, for example, a stacked structure of a BPSG film and an SOG film. And it is preferable that thickness is 100-5000 kPa.

As shown in FIG. 3J, the gate conductive layers 109A and 109B and the gate insulating layer 111 are etched by performing an etch back process.

Due to this etching process, the gate conductive films 109A and 109B of the NMOS gate NG and the PMOS gate PG are separated from each other. In addition, the capping layer 114 may have a spacer shape on sidewalls of the gate patterns NG and PG.

Subsequently, an oxidation process is performed to form the sidewall protection layer 116 on the sidewalls of the etched gate conductive layers 109C and 109D.

For example, the oxidation process may be performed by heat treatment at 700 to 1100 ° C. in an O ₂ or O ₂ + H ₂ or H ₂ O + H ₂ atmosphere to form the sidewall protective layer 116 on the sidewalls of the gate conductive layers 109C and 109D. Sidewalls on the sidewalls of the gate conductive films 109C and 109D through plasma treatment using a thermal oxidation method and O ₂ or O ₂ + H ₂ or H ₂ O + H ₂ gas at a temperature of 400 to 700 ° C. There is a plasma oxidation method for forming the protective film 116.

If the sidewall protection layer 116 is formed by plasma oxidation, the process of forming the capping layer 114 may be skipped.

Subsequently, N-type LDD doping is performed on the NMOS gate NG and P-type LDD doping is performed on the PMOS gate PG by self alignment.

LDD doping is a method used to improve the operating voltage of a semiconductor device using a region where impurity doping is low. N-type LDD doping may be performed after P-type LDD doping.

As shown in FIG. 3K, gate spacers 117 are formed on both sidewalls of the NMOS gate NG and the PMOS gate PG.

The gate spacer 117 is formed by forming an insulating film, for example, one of a nitride film and an oxide film or a stacked film thereof over the NMOS and PMOS gates NG and PG, and then performing an anisotropic etching process.

Next, an interlayer insulating film 118 is formed and planarized.

Next, as shown in FIG. 3x, the landing plug 119 is formed in the cell region CELL.

Unlike the prior art (see FIG. 1), the first gate conductive film 106A of the recess gate RG has a small range of protruding from the surface of the substrate 101, so that the overall height of the recess gate RG is low. In the case of the recess gate RG formed in the cell region CELL, since an embodiment of the present invention has a step difference lower than the height of the recess gate relative to the substrate, the landing plug 119 may be formed. Low aspect ratio Therefore, even if the landing plug 124 is formed by the self-aligned contact (SAC) method, it can be stably formed without the self-aligned contact failure.

According to the embodiment of the present invention, the gates of the cell region CELL and the peripheral circuit region PERI are independently formed to reduce the formation height of the cell region CELL. The benefits of this are

First, since the formation height of the recess gate RG formed in the cell region CELL is reduced, the aspect ratio between the recess gates RG is reduced. As a result, the landing plug 119 may be stably embedded.

Second, the gate resistance may be increased by the formation height of the gate metal layer by the formation height of the first gate conductive layer 106A reduced in the cell region CELL.

Third, the gate oxide layer of the recess gate RG may be formed of pure SiO ₂ having excellent gate oxide integrity (GOI) characteristics.

The GOI characteristic refers to the quality of the gate oxide film, and is expressed as a voltage (BV, breakdown voltage) when the leakage current becomes a breakdown current while increasing the voltage.

Fourth, the first gate conductive film 106A in which the first gate conductive film 106A is heavily doped with impurities is used to suppress the shim formed in the first gate conductive film 106A of the recess gate RG. It can be formed as. Since the first gate conductive film 106A is formed separately from the second gate conductive film of the peripheral circuit region PERI, impurities can be doped at a high concentration.

Fifth, since the second gate conductive film formed in the peripheral circuit region PERI can be formed independently of the cell region CELL, the dual gate forming process of the peripheral circuit region PERI is caused by a change in thickness of the second gate conductive film. This is easy.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention is advantageous in the self-aligned contact (SAC) process because the height of the gate of the cell region is reduced and the aspect ratio between the gates is reduced, and the gate conductive film patterning process of the cell region can be omitted. This solves the problem of bad gate pattern caused by gate conductive film residue.

In addition, since the gate conductive film in the cell region is embedded in the recess pattern, the formation height of the gate metal film can be increased, thereby reducing the gate resistance.

Therefore, the self-aligned contact process facilitates not only the integration degree of the semiconductor device but also the contact resistance, and thus, the semiconductor device capable of high-speed operation can be obtained.

Claims (13)

A substrate comprising a cell region and a peripheral circuit region; A recess pattern formed in the substrate of the cell region; A first gate embedded in the recess pattern; And A second gate on the substrate in the peripheral circuit region Semiconductor device comprising a. The method of claim 1, The first gate and the second gate each include a gate conductive film and a gate metal film. The method of claim 2, The gate conductive film of the first gate is lower than the height of the gate conductive film of the second gate. The method of claim 3, And the gate metal film of the first gate and the gate metal film of the second gate have the same height. Providing a substrate comprising a cell region and a peripheral circuit region: Etching a substrate in the cell region to form a recess pattern; Forming a first gate insulating film on a surface of the recess pattern; Embedding a first gate conductive film in the recess pattern; Forming a second gate insulating film on the substrate in the peripheral circuit region; Forming a second gate conductive film on the second gate insulating film; Forming a gate metal film on the cell region and a peripheral circuit region; And Etching the gate metal layer and the first and second gate conductive layers to form a plurality of first and second gate patterns in each of the cell region and a peripheral circuit region. Semiconductor device manufacturing method comprising a. The method of claim 5, And forming an insulating layer to fill the first gate pattern after forming the first and second gate patterns, and etching the insulating layer to form a landing plug between the first gate patterns. The method of claim 5, And a gate conductive film of the first gate is lower than a height of the gate conductive film of the second gate. The method of claim 5, The gate metal film of the first gate pattern and the gate metal film of the second gate pattern have the same height. The method of claim 5, The first and second gate conductive films are formed of a polysilicon film. The method of claim 9, The method of manufacturing a semiconductor device to the doped boron in a concentration of 4E20 / cm ² ~ 5E20 / cm ^{2 in} the polysilicon film of the first gate conductive film. The method of claim 5, The second gate pattern includes a PMOS and an NMOS gate. The method of claim 11, And a concentration of impurities doped in the first gate conductive film and the second gate conductive film is different from each other. The method of claim 5, The step of embedding the first gate conductive film in the recess pattern is a semiconductor device manufacturing method for forming a first gate pattern embedded in the recess pattern by performing a planarization process after forming the conductive film to fill the recess pattern.

Images