KR20080114031A - Stack package - Google Patents

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KR20080114031A
KR20080114031A KR1020070063183A KR20070063183A KR20080114031A KR 20080114031 A KR20080114031 A KR 20080114031A KR 1020070063183 A KR1020070063183 A KR 1020070063183A KR 20070063183 A KR20070063183 A KR 20070063183A KR 20080114031 A KR20080114031 A KR 20080114031A
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South Korea
Prior art keywords
substrate
semiconductor chip
stack package
bump
flip
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KR1020070063183A
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Korean (ko)
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김재면
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주식회사 하이닉스반도체
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Priority to KR1020070063183A priority Critical patent/KR20080114031A/en
Publication of KR20080114031A publication Critical patent/KR20080114031A/en

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    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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Abstract

The stacked package is provided to minimize the malfunction due to the signal delay or the noise by forming a stack package of the structure which adheres the substrates with the medium of bump. The stacked package comprises the first substrate(220), the first semiconductor chip(210), the second substrate(240), and the second semiconductor chip(230). The first semiconductor chip is flip-chip-bonded on the first substrate. The second substrate is arranged on the first semiconductor chip. The second substrate is electrically connected to the first substrate. The second semiconductor chip is flip-chip-bonded on the second substrate.

Description

스택 패키지{Stack package}Stack package

도 1은 종래의 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional stack package.

도 2는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도.2 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도 3a 내지 도 3f는 본 발명의 실시예에 따른 스택 패키지의 제조 방법을 설명하기 위한 공정별 단면도.3A to 3F are cross-sectional views of processes for describing a method of manufacturing a stack package according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

210 : 제1반도체 칩 212 : 제1본딩 패드210: first semiconductor chip 212: first bonding pad

214 : 제1범프 220 : 제1기판214: first bump 220: first substrate

222 : 코아 물질 224 : 제1회로 배선222 core material 224 first circuit wiring

226 : 제2회로 배선 228 : 제1절연막226: second circuit wiring 228: first insulating film

230 : 제2반도체 칩 232 : 제2본딩 패드230: second semiconductor chip 232: second bonding pad

234 : 제2범프 240 : 제2기판234: second bump 240: second substrate

242 : 코아층 244 : 금속 배선242: core layer 244: metal wiring

246 : 제2절연막 250 : 매립재246: second insulating film 250: buried material

260 : 제3범프 270 : 접착 부재260: third bump 270: adhesive member

280 : 봉지부 290 : 외부접속단자280: encapsulation 290: external connection terminal

본 발명은 스택 패키지에 관한 것으로, 보다 상세하게는, 전기적 특성이 우수하고 크기가 작은 스택 패키지에 관한 것이다.The present invention relates to a stack package, and more particularly, to a stack package having excellent electrical characteristics and a small size.

반도체 집적 회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 효율성을 만족시키기 위해 지속적으로 발전되어 왔다. 최근에 들어서는 전기/전자 제품의 소형화 및 고성능화가 요구됨에 따라 "스택"에 대한 다양한 기술들이 개발되고 있다. Packaging technologies for semiconductor integrated circuits have been continuously developed to meet the demand for miniaturization and mounting efficiency. Recently, as the miniaturization and high performance of electric / electronic products are required, various technologies for the "stack" have been developed.

반도체 산업에서 말하는 "스택"이란 적어도 2개 이상의 칩 또는 패키지를 수직으로 쌓아 올리는 기술을 일컫는 것으로서, 이러한 스택 기술에 의하면, 메모리 소자의 경우는 반도체 집적 공정에서 구현 가능한 메모리 용량 보다 2배 이상의 메모리 용량을 갖는 제품을 구현할 수 있고, 또한, 실장 면적 사용의 효율성을 높일 수 있다. The term "stack" in the semiconductor industry refers to a technology for stacking at least two chips or packages vertically. According to this stack technology, a memory device has twice as much memory capacity as a memory capacity that can be realized in a semiconductor integrated process. It is possible to implement a product having a, and also to increase the efficiency of the use of the mounting area.

도 1은 종래의 스택 패키지를 도시한 단면도이다. 1 is a cross-sectional view showing a conventional stack package.

도시된 바와 같이, 중앙부에 캐버티(134)가 형성되고, 상면 양측 가장자리 및 하면 양측 중앙부에 접속 패드(132)를 구비한 기판(120) 상에 중앙부에 제1본딩 패드(112)를 구비한 제1반도체 칩(110)이 플립 칩 본딩된다. 상기 제1반도체 칩(110) 상에는 접착제(114)를 매개로 상면에 제2본딩 패드(122)가 구비된 제2반도체 칩(120)이 부착되어 있다. 상기 제1반도체 칩(110)의 제1본딩 패드(112) 및 상기 제2반도체 칩(120)의 제2본딩 패드(122)는 각각 기판(130) 하면 및 상면에 구비 된 접속 패드(132)와 제1 및 제2금속 와이어(140a, 140b)로 연결되어 있다. 상기 제2금속 와이어(140b)는 상기 제2반도체 칩(120) 상에 형성된 지지층(150)에 의해 고정되어 있다. 상기 기판(130)의 캐버티(134) 하부 및 상기 기판(130)의 상부에는 봉지부(160)가 형성되어 있으며, 상기 기판(130)의 하부에는 솔더볼로 이루어진 외부접속단자(170)가 부착된다. As shown, the cavity 134 is formed at the center portion, and the first bonding pad 112 is disposed at the center portion on the substrate 120 having the connection pads 132 at both edges of the upper surface and the center at both sides of the lower surface. The first semiconductor chip 110 is flip chip bonded. On the first semiconductor chip 110, a second semiconductor chip 120 having a second bonding pad 122 is attached to an upper surface of the first semiconductor chip 110. The first bonding pad 112 of the first semiconductor chip 110 and the second bonding pad 122 of the second semiconductor chip 120 are connected to the bottom surface and the top surface of the substrate 130, respectively. And the first and second metal wires 140a and 140b. The second metal wire 140b is fixed by the support layer 150 formed on the second semiconductor chip 120. An encapsulation portion 160 is formed below the cavity 134 of the substrate 130 and an upper portion of the substrate 130, and an external connection terminal 170 made of solder balls is attached to the lower portion of the substrate 130. do.

상기 종래의 스택 패키지는 각 반도체 칩과 기판 간의 신호 연결이 금속 와이어에 의해 이루어지므로 속도가 느려지고, 전기적 연결을 위해 많은 수의 금속 와이어가 사용되어 각 칩의 전기적 특성 열화가 발생한다. In the conventional stack package, since the signal connection between each semiconductor chip and the substrate is made by metal wires, the speed is slowed, and a large number of metal wires are used for the electrical connection, thereby deteriorating the electrical characteristics of each chip.

그리고, 상기 상부 및 하부 반도체 칩과 상기 기판을 연결하는 금속 와이어의 길이 차이로 인해 스택 패키지의 전기적인 특성을 좌우하는 RLC 값이 서로 상이하게 되어 신호 전달의 지연(Delay) 및 노이즈 현상이 발생하고, 이로 인해, 서로 상이한 전기적인 연결에 의해 고속으로 동작시 오동작이 발생하게 되어 고속동작이 요구되는 제품에 적용이 불가능하다.In addition, due to the difference in the length of the metal wires connecting the upper and lower semiconductor chips and the substrate, the RLC values that influence the electrical characteristics of the stack package are different from each other, resulting in delay and noise of signal transmission. Therefore, malfunction occurs when operating at high speed due to different electrical connections, and thus it is not applicable to a product requiring high speed operation.

또한, 금속 와이어를 형성하기 위해 기판에 추가 면적이 요구되고, 각 반도체 칩과 기판 간의 형성된 금속 와이어를 위한 갭(gap)이 요구되므로 패키지의 크기가 커진다. In addition, an additional area is required for the substrate to form the metal wire, and a gap for the metal wire formed between each semiconductor chip and the substrate is required, thereby increasing the size of the package.

본 발명은 전기적 특성이 우수하고 크기가 작은 스택 패키지를 제공한다. The present invention provides a stack package having excellent electrical characteristics and a small size.

본 발명에 따른 스택 패키지는, 제1기판; 상기 제1기판 상에 플립 칩 본딩된 제1반도체 칩; 상기 제1반도체 칩 상에 배치되고, 상기 제1기판과 전기적으로 연결된 제2기판; 및 상기 제2기판 상에 플립 칩 본딩된 제2반도체 칩을 포함하는 것을 특징으로 한다. Stack package according to the present invention, the first substrate; A first semiconductor chip flip-bonded on the first substrate; A second substrate disposed on the first semiconductor chip and electrically connected to the first substrate; And a second semiconductor chip flip-bonded on the second substrate.

상기 제1기판과 제2기판은 범프에 의해 연결된 것을 특징으로 한다.The first substrate and the second substrate is characterized in that connected by the bump.

상기 범프는 상기 플립 칩 본딩된 상기 제1반도체 칩의 높이보다 큰 두께를 갖는 것을 특징으로 한다.The bump has a thickness greater than a height of the flip chip bonded first semiconductor chip.

상기 제2기판은 배선을 형성하기 위하여 코아 물질 상에 금속층을 형성하고 식각 공정을 진행하여 범프와 전기적 연결을 위한 부분만을 남긴 인쇄회로 기판인 것을 특징으로 한다.The second substrate may be a printed circuit board that forms a metal layer on a core material and forms an etch process so as to form wiring, leaving only a portion for electrical connection with the bump.

상기 제2기판은 내부에 금속 배선이 형성되고, 전기적 연결을 위해 상기 금속 배선의 일부분이 외부로 노출된 패턴 테이프인 것을 특징으로 한다.The second substrate may be formed of a metal wiring therein, and a portion of the metal wiring may be a pattern tape exposed to the outside for electrical connection.

상기 제1기판과 상기 제1반도체 칩 사이에 개재된 매립재를 더 포함하는 것을 특징으로 한다.And a buried material interposed between the first substrate and the first semiconductor chip.

상기 제2기판과 상기 제2반도체 칩 사이에 개재된 매립재를 더 포함하는 것을 특징으로 한다.And a buried material interposed between the second substrate and the second semiconductor chip.

상기 제1기판 상에 상기 제1반도체 칩, 제2기판 및 제2반도체 칩을 덮도록 형성된 봉지부를 더 포함하는 것을 특징으로 한다.And an encapsulation part formed on the first substrate to cover the first semiconductor chip, the second substrate, and the second semiconductor chip.

상기 제1기판에 부착된 외부접속단자를 더 포함하는 것을 특징으로 한다.It further comprises an external connection terminal attached to the first substrate.

상기 제1반도체 칩의 하면과 상기 제2기판의 하면 사이에 개재된 접착 부재를 더 포함하는 것을 특징으로 한다.And an adhesive member interposed between the lower surface of the first semiconductor chip and the lower surface of the second substrate.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 반도체 칩들을 범프를 이용한 플립 칩 본딩 방식으로 각 대응하는 기판 상에 부착한 후, 상기 기판들을 범프를 매개로 부착하는 구조로 스택 패키지를 형성한다. According to the present invention, a stack package is formed by attaching semiconductor chips onto each corresponding substrate by a flip chip bonding method using bumps, and then attaching the substrates via bumps.

따라서, 스택 패키지의 상하부 반도체 칩 간의 전기적인 연결을 동일하게 함을 물론 신호의 연결 경로를 짧게 할 수 있어, 신호 지연이나 노이즈로 인한 오동작을 최소화할 수 있다. Therefore, the electrical connection between the upper and lower semiconductor chips of the stack package may be the same, and the signal connection path may be shortened, thereby minimizing malfunction due to signal delay or noise.

이에 따라, 고속 동작이 요구되는 제품 적합한 스택 패키지를 형성할 수 있다. Accordingly, a stack package suitable for a product requiring high speed operation can be formed.

이하에서는, 본 발명의 실시예에 따른 스택 패키지 및 그의 제조 방법을 상세하게 설명하도록 한다.Hereinafter, a stack package and a manufacturing method thereof according to an embodiment of the present invention will be described in detail.

도 2는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도이다. 2 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도시된 바와 같이, 본 발명에 따른 스택 패키지는 제1기판(220) 상에 제1반도체 칩(210)이 플립 칩 본딩 되고, 상기 제1반도체 칩(210) 상에 상기 제1기판(220)과 전기적으로 연결된 제2기판(240)이 배치되며, 상기 제2기판(240) 상에는 제2반도체 칩(230)이 플립 칩 본딩되어 구성된다. As shown, in the stack package according to the present invention, the first semiconductor chip 210 is flip chip bonded onto the first substrate 220, and the first substrate 220 is formed on the first semiconductor chip 210. A second substrate 240 electrically connected to the second substrate 240 is disposed, and the second semiconductor chip 230 is flip chip bonded on the second substrate 240.

상기 제1기판(220)은 내부에 코아 물질(222)이 구비되고, 상기 코아 물질(222)의 상부 및 하부에는 제1 및 제2회로 패턴(224, 226)이 배치되며, 상기 제1 및 제2회로 패턴(224, 226)은 접속 패드 및 볼랜드로 이용된다. 상기 제1기판(220)의 코아 물질(222) 및 제1 및 제2회로 패턴(224, 226) 상에는 절연을 위하여 솔더 레지스트로 이루어진 제1절연막(228)이 형성된다. The first substrate 220 is provided with a core material 222 therein, and first and second circuit patterns 224 and 226 are disposed above and below the core material 222, respectively. The second circuit patterns 224 and 226 are used as connection pads and borland. On the core material 222 and the first and second circuit patterns 224 and 226 of the first substrate 220, a first insulating layer 228 made of a solder resist is formed for insulation.

상기 제1반도체 칩(210)은 상면에 상기 제1기판(220) 중앙부의 제1회로 패턴(224)과 대응하는 위치에 제1본딩 패드(212)가 구비된다. 상기 제1반도체 칩(210)의 제1본딩 패드(212) 상에는 제1범프(214)가 형성되며, 상기 제1반도체 칩(210)은 상기 제1범프(214)가 상기 제1기판(220)의 제1회로 패턴(224)에 부착되도록 상기 제1기판(220) 상에 플립 칩 본딩된다. 상기 제1반도체 칩(210)과 상기 제1기판(220) 사이에는 상기 제1범프(214)를 보호하기 위하여 매립재가 형성될 수 있다. The first semiconductor chip 210 is provided with a first bonding pad 212 at a position corresponding to the first circuit pattern 224 of the central portion of the first substrate 220 on the top surface. A first bump 214 is formed on the first bonding pad 212 of the first semiconductor chip 210, and the first bump 214 is formed on the first substrate 220. Flip chip bonding on the first substrate 220 to be attached to the first circuit pattern 224. A buried material may be formed between the first semiconductor chip 210 and the first substrate 220 to protect the first bump 214.

상기 제2기판(240)은 배선을 형성하기 위하여 코아 물질 상에 금속층을 형성하고 식각 공정을 진행하여 범프와 전기적 연결을 위한 부분만을 남긴 인쇄회로 기판이다. 상기 제2기판(240)은 코아층(242)과 금속 배선(224) 및 상기 금속 배선(224)의 절연 및 산화 방지를 위하여 금속 배선(224)을 덮는 제2절연막(246)으로 이루어지며, 상기 제1기판(220)의 제1회로 패턴(224)과 대응하는 부분의 상기 코아층(242) 및 제2절연막(246)은 패터닝되어 일부 금속 배선(224)의 상하부가 노출된다. The second substrate 240 is a printed circuit board that forms a metal layer on a core material and forms an etch process so as to form a wiring, leaving only a portion for the electrical connection with the bumps. The second substrate 240 includes a core layer 242, a metal wiring 224, and a second insulating film 246 covering the metal wiring 224 to prevent insulation and oxidation of the metal wiring 224. The core layer 242 and the second insulating layer 246 of the portion corresponding to the first circuit pattern 224 of the first substrate 220 are patterned to expose upper and lower portions of some metal lines 224.

즉, 상기 제1기판(220)의 제1회로 패턴(224) 중 상기 제1기판(220)에 부착된 제1반도체 칩(210)의 외측으로 구비된 제1회로 패턴(224)과 대응하는 위치의 금속 배선(224)의 상하부는 외부로 노출된다. 상기 제2기판(240)은 내부에 금속 배선이 형성되고, 전기적 연결을 위해 상기 금속 배선의 일부분이 외부로 노출되도로 패터닝된 테이프로 이루어진 패턴 테이프가 사용될 수 있다. That is, the first circuit pattern 224 of the first circuit pattern 224 of the first substrate 220 corresponds to the first circuit pattern 224 provided to the outside of the first semiconductor chip 210 attached to the first substrate 220. The upper and lower portions of the metal wiring 224 at the position are exposed to the outside. The second substrate 240 may have a metal wiring formed therein, and a pattern tape made of a tape patterned to expose a portion of the metal wiring to the outside for electrical connection.

상기 제2반도체 칩(230)은 상면에 상기 제2기판(240)의 금속 배선(224)과 대응하는 위치에 제2본딩 패드(232)가 구비된다. 상기 제2반도체 칩(230)의 제2본딩 패드(230) 상에는 제2범프(234)가 형성되며, 상기 제2반도체 칩(210)은 상기 제2범프(234)가 상기 제2기판(240)의 금속 배선(224) 상면에 부착되도록 상기 제2기판(240) 상에 플립 칩 본딩된다. The second semiconductor chip 230 is provided with a second bonding pad 232 on a top surface of the second semiconductor chip 230 at a position corresponding to the metal wire 224 of the second substrate 240. A second bump 234 is formed on the second bonding pad 230 of the second semiconductor chip 230, and the second bump 234 is the second substrate 240 on the second semiconductor chip 210. Flip chip bonding on the second substrate 240 to be attached to an upper surface of the metal wire 224.

상기 제2기판(240)과 상기 제2반도체 칩(230) 사이에는 상기 제2범프(234)를 보호하기 위하여 매립재(250)가 구비되며, 상기 제2기판(240)의 금속막(244) 하면에는 상기 제1반도체 칩(210)와 제1범프(214)의 높이합 보다 높은 두께를 갖는 제3범프(260)가 형성된다. A buried material 250 is provided between the second substrate 240 and the second semiconductor chip 230 to protect the second bump 234 and the metal film 244 of the second substrate 240. The third bump 260 having a thickness higher than the sum of the heights of the first semiconductor chip 210 and the first bump 214 is formed on the bottom surface.

상기 제2반도체 칩(230)이 부착된 제2기판(240)은 상기 제1반도체 칩(210) 상에 배치되도록 상기 제1기판(220) 상에 상기 제3범프(260)를 매개로 실장된다. 상기 제3범프(260)는 상기 제1기판(220) 상에 부착된 제1반도체 칩(210)의 외측에 배치된 제1회로 배선(224)에 부착된다. 상기 제1반도체 칩(210)과 제2기판(240) 사이에는 접착력 강화를 위하여 접착 부재(270)가 개재된다. 상기 제1기판(220)과 상기 제2기판(240) 사이에는 상기 제1 및 제3범프(214, 260)을 보호하기 위하여 매립재가 형성될 수 있다.The second substrate 240 to which the second semiconductor chip 230 is attached is mounted on the first substrate 220 via the third bump 260 so as to be disposed on the first semiconductor chip 210. do. The third bump 260 is attached to the first circuit wiring 224 disposed outside the first semiconductor chip 210 attached to the first substrate 220. An adhesive member 270 is interposed between the first semiconductor chip 210 and the second substrate 240 to enhance adhesion. A buried material may be formed between the first substrate 220 and the second substrate 240 to protect the first and third bumps 214 and 260.

상기 제1기판(220)의 상면에는 상기 제1반도체 칩(210), 제2기판(240) 및 제2반도체 칩(230)을 덮도록 봉지부(280)가 형성되며, 상기 제1기판(220)의 제2회로 배선(226)에는 솔더볼로 이루어진 외부접속단자(290)가 부착된다. An encapsulation part 280 is formed on an upper surface of the first substrate 220 to cover the first semiconductor chip 210, the second substrate 240, and the second semiconductor chip 230. An external connection terminal 290 made of solder balls is attached to the second circuit wiring 226 of 220.

이와 같이, 본 발명에 따른 스택 패키지는 반도체 칩들을 범프를 이용한 플립 칩 본딩 방법으로 각 대응하는 기판 상에 부착한 후, 상기 기판들을 범프를 매개로 부착하는 구조로 형성되어 스택 패키지의 상하부 반도체 칩 간의 전기적인 연결을 동일하게 함을 물론 짧게 할 수 있어,신호 지연이나 노이즈로 인한 오동작을 최소화할 수 있다. As described above, the stack package according to the present invention is formed in a structure in which semiconductor chips are attached to each corresponding substrate by a flip chip bonding method using bumps, and then the substrates are attached via bumps to form upper and lower semiconductor chips of the stack package. The electrical connection between the two parts can be made the same, of course, and can be shortened, thereby minimizing malfunction due to signal delay or noise.

도 3a 내지 도 3f는 본 발명의 실시예에 따른 스택 패키지의 제조 방법을 설명하기 위하여 도시한 공정별 단면도이다.3A to 3F are cross-sectional views illustrating processes for manufacturing a stack package according to an exemplary embodiment of the present invention.

도 3a를 참조하면, 내부에 코아 물질(222)이 배치되고, 상기 코아 물질(222)의 상하면에 다수의 제1 및 제2회로 패턴(224, 226)이 구비되며, 상기 코아 물질(222) 및 제1 및 제2회로 패턴(224, 226) 상에 제1절연막(228)이 형성된 제1기판(220) 상에 상면에 다수의 제1본딩 패드(212)를 구비하고, 상기 제1본딩 패드(212) 상에 제1범프(214)가 형성된 제1반도체 칩(210)을 플립 칩 본딩한다. Referring to FIG. 3A, a core material 222 is disposed therein, a plurality of first and second circuit patterns 224 and 226 are disposed on upper and lower surfaces of the core material 222, and the core material 222 is provided. And a plurality of first bonding pads 212 on an upper surface of the first substrate 220 on which the first insulating layer 228 is formed on the first and second circuit patterns 224 and 226. The first semiconductor chip 210 having the first bump 214 formed on the pad 212 is flip chip bonded.

상기 제1반도체 칩(210)은 제1본딩 패드(212) 상에 형성된 제1범프(214)를 상기 제1기판(220)의 중앙부 제1회로 패턴(224)에 대응하도록 부착함으로써 제1기판(220)과 전기적으로 연결된다. The first semiconductor chip 210 attaches the first bump 214 formed on the first bonding pad 212 to correspond to the first circuit pattern 224 in the center of the first substrate 220. Is electrically connected to 220.

도 3b를 참조하면, 코아층(242) 상에 금속막을 형성한 후, 상기 제1기판(220)에 부착된 제1반도체 칩(210)의 외측으로 형성되어 있는 제1회로 패턴과 대응하는 위치에 상기 금속막이 잔류하도록 패터닝하여 금속 배선(244)을 형성한다. 그런 다음, 상기 금속 배선(244)을 덮도록 상기 코아층(242) 및 금속 배선(244)의 일부분 상에 제2절연막(246)을 형성한 후, 상기 금속 배선(244)의 상하면를 노출되도록 상기 제2절연막(246) 및 코아층(242)을 식각하여 제2기판(240)을 완성한다.Referring to FIG. 3B, after the metal layer is formed on the core layer 242, a position corresponding to the first circuit pattern formed on the outside of the first semiconductor chip 210 attached to the first substrate 220 is formed. The metal line 244 is formed by patterning the metal film to remain therein. Thereafter, a second insulating film 246 is formed on the core layer 242 and a portion of the metal wire 244 to cover the metal wire 244, and then the upper and lower surfaces of the metal wire 244 are exposed. The second insulating layer 246 and the core layer 242 are etched to complete the second substrate 240.

도 3c를 참조하면, 상기 제2기판(240) 상에 상면에 다수의 제2본딩 패드(232)가 구비되고, 상기 제2본딩 패드(232) 상에 제2범프(234)가 형성된 제2반도체 칩(230)을 상기 제2범프(234)가 상기 제2기판(240)의 금속 배선(244) 상면에 부착되도록 플립 칩 본딩한다. Referring to FIG. 3C, a plurality of second bonding pads 232 are provided on the second substrate 240 and a second bump 234 is formed on the second bonding pads 232. The semiconductor chip 230 is flip chip bonded so that the second bump 234 is attached to the upper surface of the metal wire 244 of the second substrate 240.

도 3d를 참조하면, 상기 제2기판(240)과 제2반도체 칩(230) 사이에 상기 제2범프(234)를 보호하기 위하여 매립재(250)를 형성한다. 그런 다음, 상기 제2기판(240)의 금속 배선(244) 하면으로 상술한 제1반도체 칩 및 그에 부착된 제1범프의 높이합 보다 높은 높이로 제3범프(260)를 형성한다.Referring to FIG. 3D, a buried material 250 is formed between the second substrate 240 and the second semiconductor chip 230 to protect the second bump 234. Then, the third bump 260 is formed on the lower surface of the metal wire 244 of the second substrate 240 to a height higher than the sum of the heights of the first semiconductor chip and the first bump attached thereto.

도 3e를 참조하면, 상기 제1반도체 칩(210)이 부착된 제1기판(220) 상에 상기 제2반도체 칩(230)이 부착된 제2기판(240)을 상기 제3범프(260)가 상기 제1기판(220)의 제1회로 패턴(224)에 부착되도록 실장한다. 이때, 상기 제1반도체 칩(210)의 하면과 상기 제2기판(240)의 하면 사이에는 접착성 테이프 또는 접착재로 이루어진 접착 부재(270)를 개재하여 제1반도체 칩(210)과 상기 제2기판(240)을 안정적으로 부착한다. Referring to FIG. 3E, the second bump 240 having the second semiconductor chip 230 attached to the third bump 260 is mounted on the first substrate 220 on which the first semiconductor chip 210 is attached. Is attached to the first circuit pattern 224 of the first substrate 220. In this case, between the lower surface of the first semiconductor chip 210 and the lower surface of the second substrate 240 through the adhesive member 270 made of an adhesive tape or adhesive material, the first semiconductor chip 210 and the second The substrate 240 is stably attached.

도 3f를 참조하면, 상기 제1기판(220) 상에 제1반도체 칩(210), 제2반도체 칩(230) 및 제2기판(240)을 덮도록 봉지부(280)를 형성한다. 그런 다음, 상기 제1기판(220) 하부의 제2회로 패턴(226)에 바람직하게 솔더볼로 이루어진 외부접속단자(290)를 형성하여 스택 패키지의 제조를 완료한다.Referring to FIG. 3F, an encapsulation part 280 is formed on the first substrate 220 to cover the first semiconductor chip 210, the second semiconductor chip 230, and the second substrate 240. Then, an external connection terminal 290 preferably formed of solder balls is formed on the second circuit pattern 226 under the first substrate 220 to complete the manufacture of the stack package.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 반도체 칩들을 범프를 이용한 플립 칩 본딩 방법으로 각 대응하는 기판 상에 부착한 후, 상기 기판들을 범프를 매개로 부착하는 구조로 스택 패키지를 형성함으로써, 스택 패키지의 상하부 반도체 칩 간의 전기적인 연결을 동일하게 함을 물론 신호의 연결 경로를 짧게 할 수 있어, 신호 지연이나 노이즈로 인한 오동작을 최소화할 수 있다. As described above, according to the present invention, the semiconductor chips are attached onto each corresponding substrate by a flip chip bonding method using bumps, and then the stack packages are formed by attaching the substrates via bumps, thereby forming a stack package. The electrical connection between the semiconductor chips can be the same, and the signal connection path can be shortened, thereby minimizing malfunction due to signal delay or noise.

이에 따라, 고속 동작이 요구되는 제품 적합한 스택 패키지를 형성할 수 있다. Accordingly, a stack package suitable for a product requiring high speed operation can be formed.

Claims (10)

제1기판;A first substrate; 상기 제1기판 상에 플립 칩 본딩된 제1반도체 칩;A first semiconductor chip flip-bonded on the first substrate; 상기 제1반도체 칩 상에 배치되고, 상기 제1기판과 전기적으로 연결된 제2기판; 및 A second substrate disposed on the first semiconductor chip and electrically connected to the first substrate; And 상기 제2기판 상에 플립 칩 본딩된 제2반도체 칩;A second semiconductor chip flip-bonded on the second substrate; 을 포함하는 것을 특징으로 하는 스택 패키지. Stack package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제1기판과 제2기판은 범프에 의해 연결된 것을 특징으로 하는 스택 패키지. The first substrate and the second substrate is a stack package, characterized in that connected by a bump. 제 2 항에 있어서,The method of claim 2, 상기 범프는 상기 플립 칩 본딩된 상기 제1반도체 칩의 높이보다 큰 두께를 갖는 것을 특징으로 하는 스택 패키지.And wherein the bump has a thickness greater than a height of the flip chip bonded first semiconductor chip. 제 1 항에 있어서,The method of claim 1, 상기 제2기판은 배선을 형성하기 위하여 코아 물질 상에 금속층을 형성하고 식각 공정을 진행하여 범프와 전기적 연결을 위한 부분만을 남긴 인쇄회로 기판인 것을 특징으로 하는 스택 패키지.The second substrate is a stack package, characterized in that the printed circuit board leaving only a portion for the electrical connection with the bump by forming a metal layer on the core material to form the wiring and the etching process. 제 1 항에 있어서,The method of claim 1, 상기 제2기판은 내부에 금속 배선이 형성되고, 전기적 연결을 위해 상기 금속 배선의 일부분이 외부로 노출된 패턴 테이프인 것을 특징으로 하는 스택 패키지.The second substrate is a stack package, characterized in that the metal wiring is formed therein, and a portion of the metal wiring is a pattern tape exposed to the outside for electrical connection. 제 1 항에 있어서,The method of claim 1, 상기 제1기판과 상기 제1반도체 칩 사이에 개재된 매립재를 더 포함하는 것을 특징으로 하는 스택 패키지.The stack package further comprises a buried material interposed between the first substrate and the first semiconductor chip. 제 1 항에 있어서,The method of claim 1, 상기 제2기판과 상기 제2반도체 칩 사이에 개재된 매립재를 더 포함하는 것을 특징으로 하는 스택 패키지.And a buried material interposed between the second substrate and the second semiconductor chip. 제 1 항에 있어서,The method of claim 1, 상기 제1기판 상에 상기 제1반도체 칩, 제2기판 및 제2반도체 칩을 덮도록 형성된 봉지부를 더 포함하는 것을 특징으로 하는 스택 패키지.And a sealing part formed on the first substrate to cover the first semiconductor chip, the second substrate, and the second semiconductor chip. 제 1 항에 있어서,The method of claim 1, 상기 제1기판에 부착된 외부접속단자를 더 포함하는 것을 특징으로 하는 스택 패키지.The stack package further comprises an external connection terminal attached to the first substrate. 제 1 항에 있어서,The method of claim 1, 상기 제1반도체 칩의 하면과 상기 제2기판의 하면 사이에 개재된 접착 부재를 더 포함하는 것을 특징으로 하는 스택 패키지.And a bonding member interposed between the lower surface of the first semiconductor chip and the lower surface of the second substrate.
KR1020070063183A 2007-06-26 2007-06-26 Stack package KR20080114031A (en)

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