KR20080111874A - Apparatus for testing semiconductor and method thereof - Google Patents

Abstract

A semiconductor test device and a test method are provided to reduce test time of a semiconductor device effectively by carrying out singular semiconductor device test in fault. A semiconductor test device comprises a control signal input part(110), control signal interface unit(120), data Input part(130), test data interface unit(140), test output data interface unit(150), standards data storage module(160) and test comparison unit(170). The control signal input part generates a control signal for test. The control signal interface unit authorizes the control signal in semiconductor devices comprising a semiconductor element(180,190) group for a test. The data Input part generates a test data. The test data interface unit authorizes test data to semiconductor devices comprising a semiconductor element group for a test. The test output data interface unit integrates and receives test output data outputted, at the same time, from the semiconductor devices comprising a semiconductor element group for a test. The standards data storage module stores reference data which are output data when the output of all semiconductor devices comprising a semiconductor element group for a test is excellent. The test comparison unit compares test output data of the test output data interface unit with reference date and determines the fault of the semiconductor element group for a test.

Description

Semiconductor test apparatus and test method {APPARATUS FOR TESTING SEMICONDUCTOR AND METHOD THEREOF}

1 is an exemplary block diagram of a semiconductor test apparatus according to the prior art.

2 is a block diagram showing an exemplary configuration of a semiconductor test apparatus according to the present invention.

3 is a waveform diagram for explaining a test performed in the semiconductor test apparatus according to the present invention.

4 is a block diagram showing another exemplary configuration of a semiconductor test apparatus according to the present invention.

5 is an exemplary flow chart of a semiconductor test method in accordance with the present invention.

6 is another exemplary flow chart of a semiconductor test method in accordance with the present invention.

<Description of the symbols for the main parts of the drawings>

110: control signal input unit 120: control signal interface unit

130: data input unit 140: test data interface unit

150: test output data interface unit

160: reference data storage unit 170: test comparison unit

180, 190: semiconductor device

210: test data applying unit 220: test output data receiving unit

230: reference data storage unit 240: test comparison unit

250: semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly to branching signal lines to two or more semiconductor devices to apply test data and control signals in parallel, and to receive test output data from each semiconductor device and to receive the reference data. In comparison with the test, two or more semiconductor devices can be tested at the same time, and in the case of failure, a single semiconductor device test can be executed to effectively reduce the test time of the semiconductor devices. A semiconductor test apparatus that can be tested at the same time.

With the development of semiconductor device manufacturing technology, the capacity of semiconductor devices produced per unit silicon area has been greatly increased, and the share of semiconductor devices in the total manufacturing cost is relatively increasing.

In addition, due to the development of sub-micron process technology, the integration of semiconductor device chips is further increased, and error phenomena due to the combination of various cells inside the semiconductor device chip are very diverse, which makes it difficult to test. As a result, the production efficiency of the semiconductor device may be reduced. For this reason, more effective and rapid test techniques for semiconductor devices are required.

1 is an exemplary block diagram showing a configuration of a semiconductor test apparatus according to the prior art. Referring to FIG. 1, a semiconductor test apparatus 2 according to a conventional embodiment includes a test means 4 and an interface device 16.

The test means 4 is a device for determining whether the semiconductor device is defective in the semiconductor device tester or the chip set of the main board by using a read mode, and the semiconductor device such as the semiconductor device tester or the chip set of the main board is defective. The configuration for determining whether this is referred to as test means 4 in the specification of the present invention.

The test means 4 are connected with the semiconductor element 26 via the interface device 16 as shown. In general, the interface device 16 includes a high-fix (HiFix) board for connecting the test means 4 and the semiconductor device handler, and a DUT board for mounting the semiconductor device to the handler. That is, the interface device 16 refers to a device which is located between the test means 4 and the semiconductor element 26 to be tested to electrically and mechanically connect various signal lines according to the test purpose.

Referring to FIG. 1, the test means 4 includes a control signal input unit 6 therein for transmitting control signals such as clocks, RAS, CAS, and CS which are various semiconductor device control signals. (6) and the semiconductor element 26 under test are interconnected by a single signal line via the control signal interface 18.

In addition, inside the test means 4, a bungee signal input section 8 for sending out a bungee signal to designate a particular cell of the semiconductor device is provided, and the semiconductor device 26 for testing with the bungee signal input section 8 is provided. ) Are interconnected by a single signal line via the bungee signal interface 20.

In addition, a data input unit 10 for inputting test data is provided inside the test means 4, and the data input unit 10 is mutually connected with the semiconductor element 26 for testing through the data signal interface 22. Connected, and output data output from the semiconductor element 26 due to the corresponding data input is mutually applied to the comparison section 12 provided inside the test means 4 via the data signal interface 22. It is connected.

The comparator 12 included in the test means 4 is also interconnected with a reference data storage 14 for storing reference data read out for comparison with the output data applied from the semiconductor element 26.

Therefore, the test means 4 of the semiconductor test apparatus 2 can determine the defective state of the semiconductor element 26 by repeating the process of writing the test vector to the semiconductor element and reading it from the semiconductor element at the input terminal.

As a result, in the test mode (when the test mode input signal is 1), the reference signal read out from the reference data storage unit 14 should be 1, but if the output signal generated from the semiconductor element 26 is 0, It can be seen that the semiconductor element 26 is in a bad state.

According to the conventional semiconductor test apparatus 2, since the test data is input for each semiconductor element and the output data should be determined accordingly, for example, a DUT board for accommodating and testing n semiconductor elements 26 at the same time is used. In this case, the input unit 10 and the comparison unit 16 of the test means 4 equal to the number of semiconductor elements 26 mounted in the DUT should be provided. The input unit 10 and the comparison unit 16 are usually implemented as expensive test IO cards. According to the conventional semiconductor test apparatus, an excessive number of respective semiconductor devices tested for determining whether the input of test data and the test output data are normal or not is determined. Since the test IO card is required, the cost required for the production of the semiconductor test apparatus 2 has been increased. Since the number of semiconductor devices tested at one time is limited to the number of test IO cards, the time required for testing is increased. It acted as a limiting factor in improving the productivity of the device.

An object of the present invention is to branch a signal line to two or more semiconductor devices, apply test data and control signals in parallel, receive test output data from each semiconductor device, and compare them with reference data to the two or more semiconductor devices. The present invention provides a semiconductor test apparatus that can simultaneously perform a test for a semiconductor device, and can perform a single-stage semiconductor device test in case of failure, thereby effectively reducing a semiconductor device test time and increasing the number of semiconductor devices that can be tested at one time.

Another object of the present invention is to provide a semiconductor test apparatus which improves the disadvantage of reducing the number of semiconductor devices that can be simultaneously tested in a unit test apparatus when a plurality of input / output terminals are provided.

In order to achieve the above technical problem, the semiconductor test device according to an embodiment of the present invention, in the semiconductor test device for testing a test target semiconductor device group consisting of N (N is an integer of 2 or more), A control signal input unit for generating a control signal for the control unit; A control signal interface configured to apply the control signal to the N semiconductor devices constituting the test target semiconductor device group; A data input unit for generating test data; A test data interface configured to apply the test data to the N semiconductor devices constituting the test target semiconductor device group; A test output data interface unit configured to integrate and receive test output data simultaneously output from the N semiconductor devices constituting the test target semiconductor device group; A reference data storage unit for storing reference data which is output data when all of the N semiconductor devices constituting the test target semiconductor device group are good; And a test comparison unit comparing the test output data with the reference data to determine whether the test target semiconductor device group is defective.

According to an embodiment of the present invention, the control signal interface unit may be identical based on signal wires branched in parallel from the control signal input unit to respective control signal input terminals of the N semiconductor elements in the semiconductor device group under test. The control signal may be applied simultaneously to the N semiconductor devices in the test target semiconductor device group.

According to another embodiment of the present invention, the test data interface unit may be configured to perform the same test based on a signal line branched in parallel from the data input unit to respective data input terminals of the N semiconductor elements in the test target semiconductor device group. And simultaneously applying data to the N semiconductor devices in the test target semiconductor device group.

According to another embodiment of the present invention, the test data output interface unit may be configured to perform the test based on signal wires integrated into a single test comparator at each data output terminal of the N semiconductor devices in the test target semiconductor device group. And integrating and receiving the test output data simultaneously output from the N semiconductor devices in the target semiconductor device group.

According to another exemplary embodiment of the present disclosure, the test output data interface unit may further include a passive element or an active element to integrate and receive the test output data simultaneously output from the N semiconductor elements in the test target semiconductor element group. Characterized in that.

According to another embodiment of the present invention, the control signal is characterized in that it comprises a clock signal as a signal for controlling the operation of the N semiconductor elements.

According to another embodiment of the present invention, the control signal is characterized in that it comprises an address signal of the semiconductor element.

According to another embodiment of the present invention, the semiconductor test apparatus may include a high-fix configuration for interfacing the semiconductor test apparatus with the N semiconductor elements in the test target group; And a DUT board having a socket for mounting the N semiconductor elements. The control signal interface unit, the test data interface unit, and the test output data interface unit may include the high-fix configuration or the DUT. Characterized in that arranged on the board.

According to another exemplary embodiment of the present invention, the test comparator includes two or more threshold comparators having different comparison threshold voltages, thereby outputting a partial failure of the N semiconductor devices in the semiconductor device group under test. The voltage and the output voltage in case of all failures are distinguished from each other.

According to another exemplary embodiment of the present disclosure, the test data interface unit and the test output data interface unit may be integrated with each other.

According to another exemplary embodiment of the present disclosure, the test output data interface unit may further include an output buffer, and the output buffer may be respectively output from the N semiconductor devices in the test target semiconductor device group. If is different from each other characterized in that for adjusting the voltage level of the test output data.

In a semiconductor test apparatus according to another embodiment of the present invention, a semiconductor test apparatus for testing a semiconductor device having a plurality of input / output terminals, the test data applying unit applying test data to the plurality of input / output terminals of the semiconductor device. ; Two or more input / output terminals of the plurality of input / output terminals of the semiconductor device are grouped into an input / output terminal group to integrate test output data by the test data output from respective input / output terminals belonging to the input / output terminal group, thereby integrating test output. An output data receiver for receiving as data; A reference data storage unit for storing reference data which is output data when all of the input / output terminals belonging to the input / output terminal group of the semiconductor element are good; And a test comparison unit comparing the reference data with the integrated test output data to determine whether the semiconductor device is defective.

According to another embodiment of the present invention, the test data applying unit may include: test data input wires configured to receive the test data from the test data applying unit; And a plurality of test data application wirings for branching from the test data input wiring to simultaneously input the test data to the input / output terminals belonging to the input / output terminal group.

According to another embodiment of the present invention, the test data input wiring is less than the total number of the plurality of input and output terminals of the semiconductor device, the semiconductor test apparatus, characterized in that

According to another embodiment of the invention, the test output data receiving unit, the test data receiving wiring for integrating the test output data from each of the input and output terminals belonging to the input and output terminal group to a single output data receiving unit It characterized by including.

According to another embodiment of the present invention, the test output data receiving unit may include a passive element or an active element.

According to another embodiment of the present invention, the test output data receiver further includes an output buffer, wherein the output buffer is different from each other when the test output data respectively output from the plurality of input / output terminals of the semiconductor device is different. The voltage level of the test output data is adjusted.

According to another embodiment of the present invention, the test data applying unit and the test output data receiving unit may be integrated with each other.

According to another aspect of the present invention, a semiconductor test apparatus includes a semiconductor test apparatus configured to apply the same control signal and the same test data to two or more semiconductor devices, and to integrate and receive test output data from the two or more semiconductor devices. A control signal interface unit for applying the control signal in parallel to the at least two semiconductor devices; And a test data interface configured to apply the test data to the at least two semiconductor devices in parallel and to integrally receive the test output data from the at least two semiconductor devices.

According to another embodiment of the present invention, the control signal interface unit may include: a control signal input line for transmitting the single control signal; And a plurality of control signals electrically branched from the control signal input wires and electrically connected in parallel to all or part of the two or more semiconductor elements to transfer the control signal to all or part of the two or more semiconductor elements. It characterized in that it comprises a wiring.

According to another embodiment of the present invention, the control signal input wiring is characterized in that the number is less than the number of the two or more semiconductor elements.

According to another embodiment of the present invention, the test data interface unit includes: a test data input line for transferring the single test data; And a plurality of test data application wirings electrically connected in parallel to all or a portion of the at least two semiconductor elements so as to branch from the test data input line to transfer the test data to all or a portion of the at least two semiconductor elements. It characterized by including.

According to another embodiment of the present invention, the test data input wiring is characterized in that the number is smaller than the number of the two or more semiconductor devices.

According to another exemplary embodiment of the present disclosure, the test data interface unit may include a test data receiving line configured to receive the test output data from the at least two semiconductor devices.

A test method according to another embodiment of the present invention is a semiconductor test method for testing a test target semiconductor device group consisting of a plurality of semiconductor devices, comprising: (a) controlling the plurality of semiconductor devices in the test target semiconductor device group Applying signals in parallel; (b) applying test data to the plurality of semiconductor devices in parallel; (c) integrating and receiving test output data that is a result of performing the corresponding test data from the plurality of semiconductor devices; And (d) determining whether the entire test target semiconductor device group is defective based on the test output data.

According to another embodiment of the present invention, the test target semiconductor device group includes a first semiconductor device and a second semiconductor device, and the step (a) or the step (b) may be performed on the first semiconductor device. The control signal or the signal wire for applying the test data may be branched to apply the control signal or the test data to the second semiconductor device.

According to another exemplary embodiment of the present disclosure, the semiconductor test method may further include (e) storing reference data which is the test output data with respect to the test data when the entire test target semiconductor device group is satisfactory. The step (d) may include (d-1) comparing the reference data with the test output data.

According to another exemplary embodiment of the present invention, a test method includes testing a semiconductor device including a plurality of input / output terminals, the method including: (a) applying a control signal to the semiconductor device; (b) applying test data in parallel to the plurality of input / output terminals of the semiconductor device; (c) integrating and receiving test output data which is a result performed in response to the test data from the plurality of input / output terminals of the semiconductor device; And (d) determining whether the semiconductor device is defective based on the test output data.

According to another embodiment of the present invention, the plurality of input and output terminals, the first input and output terminal and the second input and output terminal, the step (b), for the application of the test data to the first input and output terminal The test data may be applied to the second input / output terminal by branching a signal wire.

According to another embodiment of the present invention, the semiconductor test method comprises the steps of: (e) storing reference data which is the test output data for the test data when all of the plurality of input / output terminals of the semiconductor element are good; Further comprising, wherein step (d), (d-1) comparing the reference data and the test output data; characterized in that it comprises a.

A semiconductor test method according to another embodiment of the present invention is a semiconductor test apparatus for testing a test target semiconductor device group consisting of a plurality of semiconductor devices, the same test of each of the semiconductor devices constituting the test target semiconductor device group A parallel connection node for integrating test output data by data; When the output potential level of the integrated output data of the parallel connection node is located between the 'high' voltage reference level and the 'low' voltage reference level when all the semiconductor devices belonging to the test target semiconductor device group are good products At least one of the target semiconductor device group is characterized in that it comprises a; a test comparison unit to determine that the defective.

According to another embodiment of the present invention, the test comparison unit, when determining that the output potential level of the integrated output data of the parallel connection node is a logic level opposite to the test data, a plurality of constituting the test target semiconductor device group All of the above semiconductor elements are determined to be defective.

According to another exemplary embodiment of the present disclosure, the semiconductor test apparatus may further include at least one semiconductor device constituting the test target semiconductor device group when the test comparison unit determines that at least one of the test target semiconductor device groups is defective. And a secondary test unit which performs a secondary test for selecting the semiconductor device as a defective product by inputting test data individually.

According to another exemplary embodiment of the present disclosure, the semiconductor test apparatus may further include a control signal input unit configured to branch and input the same control signal to a plurality of the semiconductor devices forming the test target semiconductor device group. .

Lastly, according to another exemplary embodiment of the present disclosure, the semiconductor test apparatus may further include a data input unit configured to branch and input the same test data into a plurality of the semiconductor devices forming the test target semiconductor device group. It is done.

Hereinafter, the semiconductor test apparatus of the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram illustrating an exemplary configuration of a semiconductor test apparatus according to the present invention.

As shown in the drawing, the semiconductor test apparatus includes a control signal input unit 110, a control signal interface unit 120, a data input unit 130, a test data interface unit 140, and a test output data interface unit. 150, a reference data storage 160, and a test comparator 170 may be included.

The semiconductor test apparatus according to the present invention is a semiconductor test apparatus capable of simultaneously testing a group of test target semiconductor elements including a plurality of semiconductor elements.

In FIG. 2, two semiconductor devices 180 and 190 are illustrated. For example, the two semiconductor devices may form a test target semiconductor device group. However, the number of semiconductor devices in the semiconductor device group under test is not limited thereto, and may be set to, for example, four or eight.

The control signal input unit 110 inputs a control signal for testing a semiconductor device to the test target semiconductor device group. The control signal may include, for example, a clock signal or an address signal of a semiconductor device, and may include, for example, a control signal such as RAS, CAS, CS, or the like of a memory device. The control signal is generated for the test of the semiconductor device and is received through the control signal input unit 110.

Such a control signal may be generated in the semiconductor test apparatus according to the present invention and applied to the control signal input unit 110, for example.

The control signal interface unit 120 applies a control signal input from the control signal input unit 110 to the plurality of semiconductor elements 180 and 190 in the semiconductor device group under test in parallel. In this case, the control signal interface unit 120 may branch the signal wire for the control signal and apply it to the plurality of semiconductor devices 180 and 190 in the semiconductor device group under test.

The data input unit 130 receives test data for transmission to the test target semiconductor device group. That is, data to be written to the plurality of semiconductor devices 180 and 190 in the semiconductor device group under test is received.

Such test data may be generated in the semiconductor test apparatus according to the present invention and applied to the data input unit 130, for example.

The test data interface unit 140 applies the test data input from the data input unit 130 to the test target semiconductor device group in parallel.

In this case, the test data interface unit 140 may branch the signal lines for the test data and apply them in parallel to the plurality of semiconductor devices 180 and 190 in the test device semiconductor device group.

The test output data interface unit 150 collectively receives test output data output from the plurality of semiconductor devices 180 and 190 in the test device semiconductor device group.

Meanwhile, the test output data interface unit 150 may integrate and receive test output data respectively output from the plurality of semiconductor devices 180 and 190 in the semiconductor device group under test based on the signal wiring. That is, the signal wires for the test output data output from each of the plurality of semiconductor devices 180 and 190 may be electrically connected to a single signal wire and integrated. In this case, not only the signal wiring but also passive elements such as resistors or active elements such as transistors can be used for integrated reception of test output data.

In addition, the test output data interface unit 150 may further include an output buffer (not shown).

The output buffer is a voltage level of the test output data when the test output data respectively output from the plurality of semiconductor devices 180 and 190 are different, that is, when one or more of the plurality of semiconductor devices 180 and 190 are defective. By adjusting the configuration, the test comparator 170 may be configured to easily check whether there is a defect.

Meanwhile, the test data interface unit 140 and the test output data interface unit 150 may be integrally implemented.

For example, the semiconductor devices 180 and 190 use the same terminal for input of test data and output of test output data.

However, when the semiconductor devices 180 and 190 use separate terminals for input of test data and output of test output data, the semiconductor devices 180 and 190 may not be integrated and implemented separately. For example, in the case of a memory device or a logic IC device having a data input terminal and an output terminal separately, the test data interface unit 140 and the test output data interface unit 150 may be separately implemented.

The reference data storage unit 160 stores reference data which is output data when all of the plurality of semiconductor devices 180 and 190 in the test target semiconductor device group are good.

The test comparison unit 170 compares the test output data integrated through the test output data interface unit 150 with the reference data stored in the reference data storage unit 160 to determine whether the test target semiconductor device group is defective. .

The test comparator 170 may include two or more threshold comparators having different comparison threshold voltages.

When the two or more threshold comparators are used, the output voltage when the plurality of semiconductor devices 180 and 190 in the test target semiconductor device group is defective may be sensed. That is, it is possible to check the range of the output voltage with respect to the test output data determined to be defective.

Meanwhile, the control signal interface unit 120, the test data interface unit 140, and the test output data interface unit 150 may control the control signals and the test data of the semiconductor test apparatus to include a plurality of semiconductor devices ( It is configured to be applied to or received from the plurality of semiconductor devices 180 and 190 in the semiconductor device group under test.

Such an interface is performed based on a high-fix configuration for interface between a conventional semiconductor test device and a semiconductor device under test, and a DUT board having a socket for mounting a plurality of semiconductor devices.

Therefore, the semiconductor test apparatus according to the present invention has a high-fix configuration for the interface between the semiconductor test apparatus and the plurality of semiconductor elements 180 and 190 in the test target group, and a socket for mounting the plurality of semiconductor elements 180 and 190. It may further include a DUT board having a. In this case, the control signal interface unit 120, the test data interface unit 140, and the test output data interface unit 150 may be arranged in such a high resolution configuration or a DUT board.

Hereinafter, the operation of the test comparison unit 170 will be described in more detail with reference to FIG. 3.

3 is a waveform diagram illustrating test performance in the semiconductor test apparatus according to the present invention.

The waveform diagram shown in FIG. 3 includes a clock signal as a control signal, good quality data, that is, test output data output from each semiconductor element 170 and 180, that is, a memory in a normal case, in the semiconductor test apparatus shown in FIG. 2. When the data is defective, that is, the test output data output from each of the semiconductor devices 170 and 180, that is, the memory, and the one semiconductor device 170 and 180, that is, the memory are defective, the test output data interface unit 150. ) Test output data received and integrated in the test output data, the test output data received and integrated in the test output data interface unit 150 when the two semiconductor devices 170 and 180, that is, the memory is defective, and the two semiconductor devices 170 and 180, that is, waveforms of the test output data received by the test output data interface unit 150 when all of the memories are normal are illustrated.

In this case, when both of the semiconductor devices 170 and 180 are normal, the test output data received by the test output data interface unit 150 has the same waveform as the reference data previously stored in the reference data storage unit 160.

In the test, test data is input through the data input unit 110 and applied to the semiconductor devices 180 and 190 to be tested. For example, when the semiconductor devices 180 and 190 are memory devices or memory modules, a predetermined pattern of data (for example, 010101..., Ie, test data) is written in the semiconductor devices 180 and 190 in the write mode.

In this case, the semiconductor test apparatus according to the present invention integrally receives test output data from the semiconductor devices 180 and 190 through the test output data interface unit 150. Thereafter, the test output unit 150 compares the test output data integrated through the test output data interface unit 150 with the reference data of the reference data storage unit 160.

In this case, the reference data is the same waveform as the test output data received by the test output data interface unit 150 when both the good data or the two semiconductor devices 170 and 180 are normal.

For example, when the continuous data pattern of 01010101 input as shown in FIG. 3 is referred to as reference data, if the test output data integrally received through the test output data interface unit 150 is similar to 01010101, the semiconductor devices 180 and 190 may be used. It can be judged that they are all favorable semiconductor elements.

If the semiconductor device 180 or 190 outputs a pattern, such as 01000101, and the test output data integrally received through the test output data interface unit 150 is not 01010101, the test output is performed for a section in which the reference data is one. The data may be zero. Therefore, in this case, at least one of the semiconductor devices 180 and 190 may be determined to be defective.

In particular, when only one of the semiconductor devices 180 and 190 outputs bad data, that is, when one outputs a 'High' and one 'Low' voltage differently from each other, an input terminal node of the test comparator 170 (FIG. 2). (Shown as Node A) represents a distorted waveform of the intermediate level voltage, so that the test comparator 170 can simply confirm that the reference data does not match.

If the test output data output from the semiconductor devices 180 and 190 are all defective, the logic level is obvious from the input node Node A of the test comparator 170 such as 01000101. Therefore, the test comparison unit 170 may compare and determine whether or not the defect is bad compared to the reference data 01010101.

Therefore, the test 'Pass' process is performed only when both semiconductor devices 180 and 190 are good products, and in the other cases (both are bad or only one of them is bad), the semiconductor device 180, 190 may be classified separately and each test may be performed to determine whether it is a good product.

In particular, when the test comparator 170 uses two or more threshold comparators having different comparison threshold voltages, the output voltages may be compared and checked in detail when the semiconductor devices are all defective or some are defective. This is possible.

Simultaneous testing of a plurality of semiconductor devices, such as memory devices, in this manner allows the classification of most good memory devices in a short time, and the existing single memory for only a small number of memory devices that are not judged good in simultaneous tests. The testing process effectively reduces the overall memory test time.

Referring to the embodiment shown in Figure 2 in another aspect of the present invention. The semiconductor test apparatus for testing a test target semiconductor device group including a plurality of semiconductor devices 180 and 190 includes a parallel connection node A and a test comparison unit 170.

The parallel connection node Node A performs a function of integrating test output data by the same test data of each of the semiconductor devices 180 and 190 constituting the semiconductor device group under test.

The test comparator 170 has an output potential level of the integrated output data of the parallel connection node positioned between a 'high' voltage reference level and a 'low' voltage reference level of the integrated output data of the test target semiconductor device group in a normal case. In this case, at least one of the semiconductor device groups under test performs a function of determining that the defective product is defective.

If all of the semiconductor devices 180 and 190 are good or defective at the same time, the output potential level of the integrated test output data satisfying the 'high' voltage reference level or above or the 'low' voltage reference level is located, but otherwise If the output potential level is located between the levels, it can be determined that only some of the semiconductor devices are defective.

According to this embodiment, it is assumed that the semiconductor device group under test is composed of N semiconductor devices (N is an integer of 2 or more) and M (M is an integer of 2 or more) is tested simultaneously ( While the total number of semiconductor devices tested at the same time is M ㅧ N), the conventional semiconductor test apparatus requires M 테스트 N test IO cards, which are the total number of semiconductor devices tested at the same time, whereas according to the present invention only M test IO cards Because of this requirement, a small number of test IO cards can be used to simultaneously test a semiconductor device N times the number of test IO cards.

On the other hand, there is a problem that it is not possible to know exactly which semiconductor device of the semiconductor device group to be tested with this configuration alone. In order to solve this problem, when the test comparison unit 170 determines that at least one of the test target semiconductor device groups is a defective product, the test data may be inputted separately for at least one semiconductor device constituting the test device semiconductor device group. More preferably, the method further includes a secondary test unit (not shown) for performing a secondary test for selecting a defective semiconductor device.

In the second test, for example, assuming that the semiconductor device group includes the first semiconductor device 180 and the second semiconductor device 190, the CS (Chip Select), which is a control signal selectively for the first semiconductor device 180, is selectively selected. This can be done by applying a signal.

According to this embodiment, the test run time is lengthened due to the second test execution, but in the semiconductor process having a high yield (for example, 99%), the second test is less likely to occur, and thus the test run time delay problem can be ignored. In addition, it provides an effect of knowing exactly which semiconductor device of the semiconductor group under test has a defect.

In this case, when it is determined that the output potential level of the integrated output data of the parallel connection node A is at a logic level that is opposite to the test data, the test comparison unit 170 configures the plurality of semiconductor devices constituting the test target semiconductor device group. It is desirable to further minimize the probability of occurrence of the secondary test by determining that all of the defective items are defective products by treating the entire test target semiconductor device group without proceeding the above-described secondary test.

4 is a block diagram showing another exemplary configuration of a semiconductor test apparatus according to the present invention.

As illustrated, the semiconductor test apparatus according to another embodiment of the present invention includes a test data applying unit 210, a test output data receiving unit 220, a reference data storage unit 230, and a test comparison unit 240. do.

The semiconductor test apparatus according to another exemplary embodiment of the present invention illustrated in FIG. 4 is a case where the semiconductor test apparatus is applied to a test of a single semiconductor device, and particularly when applied to a semiconductor device having a plurality of input / output terminals. Similarly to the embodiment of FIG. 2, grouping two or more input / output terminals into an input / output terminal group to integrate test output data.

In the case of a semiconductor device having a plurality of input / output terminals, the number of input / output signal lines provided in the test apparatus is limited, so that the number of semiconductor devices that can be tested at the same time is greatly reduced.

However, the semiconductor test apparatus according to another embodiment of the present invention with reference to FIG. 4 is configured to apply test data to each of these input and output terminals in parallel, and to integrate and receive test output data from each input and output terminal. Take

This will be described in more detail as follows.

The test data applying unit 210 applies test data in parallel to a plurality of input / output terminals of the semiconductor device 250.

In this case, the test data applying unit 210 branches the test data input wiring (not shown) for test data input and the test data received through the test data input wiring to supply the same test data to the semiconductor device 250. The test data application wirings may be electrically connected to all or a part of the plurality of input / output terminals.

In this manner, the number of test data input wires may be smaller than the total sum of the plurality of input / output terminals of the semiconductor device 250, thereby simplifying the wiring structure of the semiconductor test apparatus.

The test output data receiver 220 integrates and receives test output data, which is a result of performing corresponding to test data, from a plurality of input / output terminals of the semiconductor device 250.

The test output data receiver 220 may include, in particular, test data receiving wires (not shown) for receiving test output data from a plurality of input / output terminals of the semiconductor device 250.

That is, the signal wires for the test output data output from each of the plurality of input / output terminals of the semiconductor device 250 may be connected to and integrated into a single signal wire. Or, in this case, not only signal wiring but also passive components such as resistors or active components such as transistors can be used for integrated reception of test output data.

Also, the test output data receiver 220 may further include an output buffer (not shown).

When the output buffers are different from each other in the test output data output from the plurality of input and output terminals of the semiconductor device 250, that is, when one or more outputs of the input and output terminals is bad, the test buffer is adjusted by adjusting the voltage level of the test output data The unit 240 may be configured to easily determine whether or not the defect.

Meanwhile, in the case of a memory device or a logic IC device having an input terminal and an output terminal separately, the test data applying unit 210 and the test output data receiving unit 220 are implemented separately, but both input and output are performed at the same terminal. In this case, the test data applying unit 210 and the test output data receiving unit 220 may be integrated.

The reference data storage unit 230 stores reference data which is output data when all of the outputs of the semiconductor device 250 are good.

The test comparator 240 compares the reference data of the reference data storage 230 with the test output data integrated by the test data receiver 220 to determine whether the semiconductor device 250 is defective.

The operation of the test comparator 240 is similar to that of the test comparator 170 described with reference to FIGS. 2 to 3 except that the operation of the test comparator 240 is a comparison of a plurality of input / output terminals of one semiconductor device, and thus a detailed description thereof is omitted. do.

In the case of applying the semiconductor test apparatus according to another embodiment of the present invention with reference to FIG. 4, for example, in a memory device having 16 IO input / output terminals, two input / output terminals are grouped into one input / output terminal group. It can be tested like a memory device with 10 IOs. This reduces the number of tester IO cards required per memory in half in the same general memory test device, which in turn doubles the number of products that can be tested simultaneously on one tester.

Meanwhile, although not shown, another embodiment according to the present invention is as follows.

In this embodiment, the same control signal and test data are applied to two or more semiconductor devices, and test output data is received from two or more semiconductor devices.

Therefore, the semiconductor test apparatus according to another embodiment of the present invention includes a control signal interface unit for applying control signals to two or more semiconductor devices in parallel, and test data to two or more semiconductor devices in parallel. And a test data interface configured to apply and integrally receive test output data from two or more semiconductor devices.

In this case, the control signal interface unit branches the control signal input line for inputting the control signal and the control signal received through the control signal input line to electrically parallel the same control signal to all or part of two or more semiconductor elements. The control signal application wiring to be connected may be included.

In addition, the number of such control signal input lines is preferably smaller than the total sum of input terminals for control signal input in each of two or more semiconductor devices.

In this case, the test data interface unit branches the test data input wiring for inputting the test data and the test data received through the test data input wiring to electrically parallel the same test data to all or part of two or more semiconductor devices. The test data application wiring to be connected may be included.

Likewise, the number of test data input wires is preferably smaller than the total sum of input terminals for test data input to two or more semiconductor devices.

In addition, the test data interface unit may include test data receiving wires for receiving test output data from two or more semiconductor devices.

5 is an exemplary flowchart of a semiconductor test method according to the present invention.

The semiconductor test method according to the present invention illustrated in FIG. 5 relates to a method of testing a test target semiconductor device group including a plurality of semiconductor devices.

First, a semiconductor element to be tested, such as a memory, is attached to a test apparatus. In this case, for example, two or more memories are grouped into a group of semiconductor devices under test. The test is subsequently performed simultaneously on the group of semiconductor devices to be tested.

That is, the control signals are applied in parallel to the plurality of semiconductor devices in the semiconductor device group under test (S110). Control signals include, for example, instructions for operating the memory, clocks, address signals, and the like.

Thereafter, test data is applied to the plurality of semiconductor devices in parallel (S120). The test data may be data written in a cell for testing a specific cell of a semiconductor device, for example, a memory. Alternatively, other non-memory devices may be data for its operation.

The parallel application in step S110 or S120 may be performed for the application of control signals or test data to the first semiconductor device, for example, if the group of semiconductor devices to be tested is composed of two devices, the first semiconductor device and the second semiconductor device. The signal wiring can be branched to apply a control signal or test data to the second semiconductor element.

Thereafter, the test output data, which is a result performed in response to the test data applied in step S120, is received from the plurality of semiconductor devices by integration. Such integrated reception is integrated, for example, via signal wirings, to test the overall failure, not each of the semiconductor devices.

Although not shown, reference data, which is test output data when the entire test target semiconductor device group is good with respect to the test data, may be stored in advance.

Such reference data is then used as a criterion for determining whether the entire semiconductor device group under test is defective.

Subsequently, it is determined whether or not the entire test target semiconductor device group is defective based on the test output data integrally received in step S130 (S140).

That is, when the reference data and the test output data are the same, the entire test target semiconductor device group may be determined to be good, and when not, the at least one semiconductor device may be determined to be defective.

In this case, the semiconductor devices may be individually tested for the semiconductor devices in the defective test target device group.

6 is another exemplary flow chart of a semiconductor test method according to the present invention.

The semiconductor test method according to the present invention illustrated in FIG. 6 relates to a method for testing a semiconductor device having a plurality of input / output terminals.

First, a semiconductor element to be tested, such as a memory, is attached to a test apparatus. In this case, the signal wires are connected to the plurality of input / output terminals of the semiconductor device and configured to perform a test on the plurality of input / output terminals at the same time.

First, a control signal is applied to the semiconductor device (S210).

Thereafter, test data is applied in parallel to the plurality of input / output terminals of the semiconductor device (S220).

In the parallel application in step S220, for example, assuming that a plurality of input / output terminals comprise a first input / output terminal and a second input / output terminal, the signal wiring for applying test data to the first input / output terminal is branched. The test data can be configured to apply test data to the second input / output terminal.

Thereafter, the test output data, which is a result of performing the corresponding test data, is received from a plurality of input / output terminals of the semiconductor device in combination (S230).

Although not shown, reference data, which is test output data when all of the plurality of input / output terminals of the semiconductor element are good, may be stored in advance.

The reference data is then a reference for determining whether or not the semiconductor device is defective.

Thereafter, it is determined whether the semiconductor device is defective based on the test output data (S240).

That is, when the reference data and the test output data are the same, the semiconductor device may be determined to be good, and when not the same, the semiconductor device may be determined to be defective.

In this case, the defective semiconductor device may be tested again or discarded through repair or the like.

Although the configuration of the present invention has been described in detail, these are merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. This will be possible.

Therefore, the embodiments disclosed herein are not intended to limit the present invention but to describe the present invention, and the spirit and scope of the present invention are not limited by these embodiments. It is intended that the scope of the invention be interpreted by the following claims, and that all descriptions within the scope equivalent thereto will be construed as being included in the scope of the present invention.

As described above, according to the present invention, two or more semiconductor devices branch signal lines to apply test data and control signals in parallel, receive test output data from each semiconductor device, and compare the test data with reference data. The above-described semiconductor device test may be simultaneously performed, and in the case of failure, a single semiconductor device test may be executed to effectively reduce the semiconductor device test time and increase the number of testable semiconductor devices at one time.

In addition, when a plurality of conventional input / output terminals are provided, the disadvantage of reducing the number of semiconductor devices that can be simultaneously tested in a unit test apparatus can also be improved.

Claims (35)

In the semiconductor test apparatus for testing a test target semiconductor device group consisting of N (N is an integer of 2 or more), A control signal input unit generating a control signal for a test; A control signal interface configured to apply the control signal to the N semiconductor devices constituting the test target semiconductor device group; A data input unit for generating test data; A test data interface configured to apply the test data to the N semiconductor devices constituting the test target semiconductor device group; A test output data interface unit configured to integrate and receive test output data simultaneously output from the N semiconductor devices constituting the test target semiconductor device group; A reference data storage unit for storing reference data which is output data when all of the N semiconductor devices constituting the test target semiconductor device group are good; And And a test comparison unit comparing the test output data with the reference data to determine whether the test target semiconductor device group is defective. The method of claim 1, wherein the control signal interface unit, The N semiconductors in the test target semiconductor device group may receive the same control signal based on a signal line branched in parallel from the control signal input unit to each control signal input terminal of the N semiconductor devices in the test semiconductor device group. A semiconductor test device, characterized in that applied to the device at the same time. The method of claim 1, wherein the test data interface unit, The same test data is transferred to the N semiconductor devices in the test target semiconductor device group based on signal wires branched in parallel from the data input unit to respective data input terminals of the N semiconductor devices in the test semiconductor device group. And applying at the same time. The method of claim 1, wherein the test data output interface unit, Simultaneously outputting from each of the N semiconductor devices in the group of semiconductor devices under test based on signal wires integrated into a single test comparator at each data output terminal of the N semiconductor devices in the group of semiconductor devices under test And a test output data integrated therein. The method of claim 1, wherein the test output data interface unit, And a passive device or an active device, integrating and receiving the test output data simultaneously outputted from the N semiconductor devices in the test target semiconductor device group. The method of claim 1, wherein the control signal, And a clock signal as a signal for controlling the operations of the N semiconductor devices. The method of claim 1, wherein the control signal, And a semiconductor device comprising an address signal of the semiconductor device. The semiconductor test apparatus of claim 1, A high resolution configuration for interfacing the semiconductor test device with the N semiconductor devices in the test target group; And And a DUT board having a socket for mounting the N semiconductor elements. And the control signal interface unit, the test data interface unit, and the test output data interface unit are arranged in the high-fix configuration or the DUT board. The method of claim 1, wherein the test comparison unit, By including two or more threshold comparators having different comparison threshold voltages, the output voltage in case of partial failure and the output voltage in case of all failures of the N semiconductor devices in the test target semiconductor device group are distinguished from each other. A semiconductor test apparatus, characterized in that. The method of claim 1, And the test data interface unit and the test output data interface unit are integrated with each other. The method of claim 1, The test output data interface unit is configured to further include an output buffer, And the output buffer adjusts a voltage level of the test output data when the test output data respectively output from the N semiconductor devices in the test target semiconductor device group is different. In a semiconductor test device for testing a semiconductor device having a plurality of input and output terminals, A test data applying unit configured to apply test data to the plurality of input / output terminals of the semiconductor device; Two or more input / output terminals of the plurality of input / output terminals of the semiconductor device are grouped into an input / output terminal group to integrate test output data by the test data output from respective input / output terminals belonging to the input / output terminal group, thereby integrating test output. An output data receiver for receiving as data; A reference data storage unit for storing reference data which is output data when all of the input / output terminals belonging to the input / output terminal group of the semiconductor element are good; And And a test comparison unit comparing the reference data with the integrated test output data to determine whether the semiconductor device is defective. The method of claim 12, wherein the test data applying unit, A test data input line configured to receive the test data from the test data applying unit; And And a plurality of test data applying wires for branching from the test data input wires to simultaneously input the test data to the input / output terminals belonging to the input / output terminal group. The method of claim 13, wherein the test data input wiring, Wherein the number is less than the total of the plurality of input / output terminals of the semiconductor device. The method of claim 12, wherein the test output data receiving unit, And a test data receiving line for integrating test output data from each of the input / output terminals belonging to the input / output terminal group and transmitting the test output data to the single output data receiving unit. The method of claim 12, wherein the test output data receiving unit, Semiconductor test device comprising a passive device or an active device The method of claim 12, The test output data receiver further includes an output buffer, The output buffer may adjust the voltage level of the test output data when the test output data respectively output from the plurality of input / output terminals of the semiconductor element are different. The method of claim 12, wherein the test data applying unit and the test output data receiving unit, Semiconductor test device, characterized in that integrated with each other A semiconductor test apparatus for applying the same control signal and the same test data to two or more semiconductor devices, and receiving and receiving test output data from the two or more semiconductor devices. A control signal interface unit for applying the control signals to the at least two semiconductor devices in parallel; And a test data interface configured to apply the test data to the at least two semiconductor devices in parallel and to integrally receive the test output data from the at least two semiconductor devices. The method of claim 19, wherein the control signal interface unit, Control signal input wiring for transmitting the single control signal; And A plurality of control signal application wirings branched from the control signal input wirings and electrically connected in parallel to all or a portion of the two or more semiconductor elements to transfer the control signal to all or a portion of the two or more semiconductor elements; Semiconductor test apparatus comprising a The control signal input wiring of claim 20, Semiconductor test apparatus, characterized in that less than the number of the two or more semiconductor devices The method of claim 19, wherein the test data interface unit, Test data input wiring for conveying the single test data; And A plurality of test data application wirings electrically connected to all or a portion of the two or more semiconductor elements in parallel to each other so as to branch from the test data input wiring to transfer the test data to all or a portion of the two or more semiconductor elements; Semiconductor test apparatus comprising a The method of claim 22, wherein the test data input wiring, And the number is smaller than the number of the two or more semiconductor elements. The method of claim 19, wherein the test data interface unit, And a test data receiving line configured to receive the test output data from the two or more semiconductor devices. In the semiconductor test method for testing a test target semiconductor device group consisting of a plurality of semiconductor devices, (a) applying a control signal in parallel to the plurality of semiconductor devices in the test target semiconductor device group; (b) applying test data to the plurality of semiconductor devices in parallel; (c) integrating and receiving test output data that is a result of performing the corresponding test data from the plurality of semiconductor devices; And and determining whether the entire test target semiconductor device group is defective based on the test output data. The method of claim 25, The test target semiconductor device group includes a first semiconductor device and a second semiconductor device, In the step (a) or the step (b), the control signal or the test data for the second semiconductor device may be branched by branching the signal wire for the application of the control signal or the test data to the first semiconductor device. Semiconductor test method, characterized in that for applying. The method of claim 25, The semiconductor test method may further include (e) storing reference data which is the test output data with respect to the test data when the entire test target semiconductor device group is satisfactory. The step (d) comprises (d-1) comparing the reference data and the test output data. A semiconductor test method for testing a semiconductor device having a plurality of input and output terminals, (a) applying a control signal to the semiconductor device; (b) applying test data in parallel to the plurality of input / output terminals of the semiconductor device; (c) integrating and receiving test output data which is a result performed in response to the test data from the plurality of input / output terminals of the semiconductor device; And (d) determining whether the semiconductor device is defective based on the test output data. The method of claim 28, The plurality of input / output terminals are composed of a first input / output terminal and a second input / output terminal, In the step (b), the test data is applied to the second input / output terminal by branching signal wires for applying the test data to the first input / output terminal. The method of claim 28, The semiconductor test method further includes: (e) storing reference data which is the test output data with respect to the test data when all of the plurality of input / output terminals of the semiconductor device are good; Wherein step (d), (d-1) comparing the reference data and the test output data; semiconductor test method comprising a. In the semiconductor test device for testing a test target semiconductor device group consisting of a plurality of semiconductor devices, A parallel connection node integrating test output data by the same test data of each of the semiconductor devices constituting the test target semiconductor device group; When the output potential level of the integrated output data of the parallel connection node is located between the 'high' voltage reference level and the 'low' voltage reference level when all the semiconductor devices belonging to the test target semiconductor device group are good products And at least one of the target semiconductor device groups is a test comparator that determines that the defective product is a defective product. The method of claim 31, wherein the test comparison unit, When it is determined that the output potential level of the integrated output data of the parallel connection node is a logic level opposite to the test data, it is determined that all of the semiconductor devices constituting the test target semiconductor device group are defective. Semiconductor test device. The apparatus of claim 31, wherein the semiconductor test device comprises: When the test comparison unit determines that at least one of the test target semiconductor device groups is a defective product, the semiconductor device that is a defective product is a method of inputting test data individually to at least one semiconductor device constituting the test target semiconductor device group. And a secondary test unit configured to perform a secondary test for selecting a second test device. The apparatus of claim 31, wherein the semiconductor test device comprises: And a control signal input unit configured to branch and input the same control signal to a plurality of the semiconductor devices forming the test target semiconductor device group. The apparatus of claim 31, wherein the semiconductor test device comprises: And a data input unit configured to branch and input the same test data to a plurality of the semiconductor devices forming the test target semiconductor device group.

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