KR20080109368A - Fuse circuit of semiconductor apparatus - Google Patents

Fuse circuit of semiconductor apparatus Download PDF

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Publication number
KR20080109368A
KR20080109368A KR1020070057583A KR20070057583A KR20080109368A KR 20080109368 A KR20080109368 A KR 20080109368A KR 1020070057583 A KR1020070057583 A KR 1020070057583A KR 20070057583 A KR20070057583 A KR 20070057583A KR 20080109368 A KR20080109368 A KR 20080109368A
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KR
South Korea
Prior art keywords
signal
fuse
identification information
output
output unit
Prior art date
Application number
KR1020070057583A
Other languages
Korean (ko)
Inventor
김경남
조호엽
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070057583A priority Critical patent/KR20080109368A/en
Publication of KR20080109368A publication Critical patent/KR20080109368A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses

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  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention provides a fuse signal output unit for outputting a fuse signal according to whether the fuse is cut or a test signal; An option selection signal output unit configured to output the fuse signal as an option selection signal according to whether an identification information output signal is activated; And an identification information output unit configured to output the fuse signal as identification information according to whether the identification information output signal is activated.

Description

Fuse circuit of semiconductor device {FUSE CIRCUIT OF SEMICONDUCTOR APPARATUS}

1 is a circuit diagram of a fuse circuit for design analysis of a semiconductor device according to the prior art;

2 is a circuit diagram of a fuse circuit for identification information of a semiconductor device according to the prior art;

3 is a circuit diagram of a fuse circuit of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100: fuse signal output unit 200: option selection signal output unit

300: identification information output unit 400: output control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and, more particularly, to a fuse circuit that can be used for other purposes than the original use.

The semiconductor device according to the prior art has a plurality of design analysis fuse circuits and a plurality of identification information fuse circuits.

The design analysis fuse circuit is a circuit for selectively activating one of a base circuit and an option circuit for replacing the base circuit during design analysis.

As shown in FIG. 1, a fuse circuit for design analysis of a semiconductor device according to the related art includes a plurality of transistors M1 to M3, a fuse, a plurality of inverters IV1 and IV2, and a NOR gate NR1. It is provided. An option selection signal output from the inverter IV2 is used as a signal for selecting one of the basic circuit and the option circuit to operate.

When the test signal TM is activated (for example, high level) by going to the test mode, the base selection signal (Base Selection) is deactivated to the low level and the option selection signal (Option Selection) is activated to the high level. When the option selection signal is activated, the operation of the basic circuit is stopped while the option circuit is operated.

When the test mode ends, the test signal TM is inactivated. As the test signal TM is deactivated, the option selection signal is deactivated and a basic circuit is operated instead of the option circuit.

If you want the option circuit to operate during normal operation after the test is completed, you can revise using the metal option.

Thereafter, in the mass production stage, the above-described design analysis fuse circuit is not required.

The fuse circuit for identification information stores identification information, that is, die ID (DID) for tracking wafer test information, wafer map, and experimental results even after packaging. It is a circuit for doing this. The die ID is composed of a plurality of bits, and includes a lot number, a wafer number, a coordinate (Net Die), and other information.

As shown in FIG. 2, a fuse circuit for identification information according to the related art includes a plurality of transistors M11 to M15, a fuse, a plurality of inverters IV11 to IV15, and a NOR gate NR11. .

When the identification information output signal TDID is activated (for example, at a high level), the fuse circuit for identifying information may identify the identification information DID according to whether the fuse is cut. Output to the outside of the semiconductor device through.

When the identification information output signal TDID is activated while the fuse is cut, the identification information DID is output through the data line GIO at a low level. When the identification information output signal TDID is activated while the fuse is not cut, the identification information DID is output through the data line GIO at a high level.

The conventional semiconductor device described above has a problem in that it is impossible to add a fuse circuit for adding identification information when design and analysis are completed and entered a mass production process. Of course, a sufficient number of identification fuse circuits can be added at the time of design, but there is a problem of greatly increasing the layout area, which is very inefficient when no mass production is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fuse circuit of a semiconductor device capable of adding identification information without a large increase in layout area even after mass production.

A fuse circuit of a semiconductor device according to the present invention includes a fuse signal output unit for outputting a fuse signal according to whether a fuse is cut or a test signal; An option selection signal output unit configured to output the fuse signal as an option selection signal according to whether an identification information output signal is activated; And an identification information output unit configured to output the fuse signal as identification information according to whether the identification information output signal is activated.

A fuse circuit of a semiconductor device according to the present invention may include a plurality of first fuse circuit units configured to output prestored identification information in response to activation of an identification information output signal; And a plurality of second fuse circuits configured to selectively output identification information set according to whether an option selection signal or a fuse is cut for selectively operating one of the basic circuit and the option circuit according to whether the identification information output signal is activated. It is another feature.

Hereinafter, a preferred embodiment of a fuse circuit of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

A plurality of fuse circuits of the semiconductor device according to the present invention are provided, and each fuse circuit has a fuse signal output unit 100, an option selection signal output unit 200, and an identification information output unit as shown in FIG. 3. 300 and an output control unit 400.

The fuse signal output unit 100 includes first to third transistors M21 to M23, a fuse, first and second inverters IV21 and IV22, and a NOR gate NR21. In the first transistor M21, a ground voltage VSS is applied to a gate, an external voltage VDD is applied to a source, and a drain thereof is connected to one end of a fuse. A reset signal Reset is input to a gate of the second transistor M22 and a drain thereof is connected to the other end of the fuse. An input terminal of the first inverter IV21 is connected to the other end of the fuse. The third transistor M23 receives the output of the first inverter IV21 at a gate thereof, and a source and a drain are respectively connected to the source and the drain of the second transistor M22. The NOR gate NR21 receives the output of the first inverter IV21 and the test signal TM. The second inverter IV22 receives the output of the NOR gate NR21 and outputs a fuse signal (Option Selection / DID).

The option selection signal output unit 200 passes the output of the third inverter IV23 according to the third inverter IV23 receiving the fuse signal Option Selection / DID and the identification information output signal TDID. A fourth inverter IV24 receives the first transmission gate TG1 and the output of the first transmission gate TG1 and outputs the delayed option selection signal Option Selection_D.

The identification information output unit 300 includes a fifth inverter IV25, a second transmission gate TG2, and a driver 310. The fifth inverter IV25 receives a fuse signal (Option Selection / DID) output from the fuse signal output unit 100. The second transmission gate TG2 outputs the output of the fifth inverter IV25 as the identification information DID according to the identification information output signal TDID. The driver 310 drives the identification information DID to a data line GIO level and outputs the same. The driver 310 is connected between the sixth and seventh inverters IV26 and IV27 and the power supply terminal and the ground terminal to receive the identification information DID, respectively, and the sixth inverter IV26 and the seventh inverter IV27 respectively. And fourth and fifth transistors M24 and M25 for receiving an output signal of the signal.

The output control unit 400 receives the identification information output signal TDID and receives a first transmission gate TG1 of the option selection signal output unit 200 and a second transmission gate TG2 of the identification information output unit 300. Eighth inverter IV28 to be supplied is provided.

The operation of the fuse circuit of the semiconductor device according to the present invention configured as described above is as follows.

The identification information output signal TDID maintains a deactivation level (eg, a low level) when there is no identification information output command from the outside, and activates a level (eg, a high level when an identification information output command is input externally. Transitions to).

During the design analysis test, the test signal TM is activated to a high level. Since the test signal TM is at a high level, the fuse signal Option Selection / DID is output at a high level.

The identification information output signal TDID is deactivated to a low level during the design analysis test. Since the identification information output signal TDID is at a low level, the first transmission gate TG1 of the selection signal output unit 200 is turned on, and the second transmission gate TG2 of the identification information output unit 300 is turned off. .

The fuse signal Option Selection / DID is output as a delayed option selection signal Option Selection_D through the third inverter IV23, the first transmission gate TG1, and the fourth inverter IV24.

An option circuit is selected according to the delayed option selection signal Option Selection_D. The option circuit is operated in the manner described above to perform a design analysis test. When the design analysis test is completed, the test signal TM becomes a low level.

On the other hand, when the identification information (DID) is set through the separate identification information setting fuse circuit may occur when it is necessary to add the identification information (DID).

When the design analysis test is completed, the fuse signal output unit 100 is no longer used for the purpose of generating the delayed option selection signal Option Selection_D. Therefore, the fuse signal output unit 100 is used for the purpose of setting extra identification information (DID) after the design analysis test is completed.

When the additional setting of the identification information DID is required, the fuse of the fuse signal output unit 100 may match the logic value of the identification information bit to be added for the plurality of fuse circuits as shown in FIG. 3. Selectively cut the fuse.

When the identification information output command is input in the state where the above-described additional setting of the identification information DID is completed, the identification information output signal TDID is activated to a high level.

Since the identification information output signal TDID is at a high level, the first transmission gate TG1 of the selection signal output unit 200 is turned off, and the second transmission gate TG2 of the identification information output unit 300 is turned on. .

By having the first transmission gate (TG1) and turned on when the identification information (DID) output, it is outputted as a delayed option selection signal (Option Selection_D) that is different from the design analysis test according to the optional fuse cutting prevent. In other words, the logic level of the delayed option selection signal Option Selection_D is changed to prevent the basic circuit or the option circuit from malfunctioning.

The fuse signal output unit 100 outputs a fuse signal (Option Selection / DID) at a high level when the fuse is cut, and low level at the fuse signal (Option Selection / DID) when the fuse is not cut. Will output

The fuse signal Option Selection / DID is output as identification information DID through the turned-on second transmission gate TG2.

The identification information DID is driven to the logic level of the data line GIO through the driver 310 and output to the data line GIO.

The identification information DID is read from the outside of the semiconductor device through the data line GIO to perform failure analysis.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Since the fuse circuit of the semiconductor device according to the present invention can be used for design analysis and identification information setting, it is possible to simply add identification information even after the design and analysis is completed, and it is very efficient because no additional layout is required.

Claims (15)

A fuse signal output unit configured to output a fuse signal according to whether a fuse is cut or a test signal; An option selection signal output unit configured to output the fuse signal as an option selection signal according to whether an identification information output signal is activated; And And an identification information output unit configured to output the fuse signal as identification information according to whether the identification information output signal is activated. The method of claim 1, The fuse signal output unit And a signal according to whether the fuse is cut and the test signal are combined to output the fuse signal as the fuse signal. The method of claim 1, The option selection signal output unit And output the fuse signal as an option selection signal when the identification information output signal is deactivated. The method of claim 3, wherein The option selection signal output unit And a switching element configured to receive the fuse signal at an input terminal and to receive the identification information output signal at a control terminal. The method of claim 1, The identification information output unit And output the fuse signal as identification information when the identification information output signal is activated. The method of claim 5, wherein The identification information output unit And a switching element configured to receive the fuse signal at an input terminal and to receive the identification information output signal at a control terminal. The method of claim 6, The identification information output unit And a driver for driving the output of the switching element to a signal level transmitted through a data line. A plurality of first fuse circuits configured to output previously stored identification information in response to activation of the identification information output signal; And A semiconductor having a plurality of second fuse circuits for selectively outputting identification information set according to whether an option selection signal or a fuse is cut for selectively operating one of a basic circuit and an option circuit according to whether the identification information output signal is activated. Fuse circuit of the device. The method of claim 8, The second fuse circuit portion A fuse signal output unit configured to output a fuse signal according to whether a fuse is cut or a test signal; An option selection signal output unit configured to output the fuse signal to the option circuit according to whether an identification information output signal is activated; And And an identification information output unit configured to output the fuse signal as identification information according to whether the identification information output signal is activated. The method of claim 8, The fuse signal output unit And a signal according to whether the fuse is cut and the test signal are combined to output the fuse signal as the fuse signal. The method of claim 8, The option selection signal output unit And output the fuse signal as an option selection signal when the identification information output signal is deactivated. The method of claim 11, The option selection signal output unit And a switching element configured to receive the fuse signal at an input terminal and to receive the identification information output signal at a control terminal. The method of claim 9, The identification information output unit And output the fuse signal as identification information when the identification information output signal is activated. The method of claim 13, The identification information output unit And a switching element configured to receive the fuse signal at an input terminal and to receive the identification information output signal at a control terminal. The method of claim 14, The identification information output unit And a driver for driving the output of the switching element to a signal level transmitted through a data line.
KR1020070057583A 2007-06-13 2007-06-13 Fuse circuit of semiconductor apparatus KR20080109368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070057583A KR20080109368A (en) 2007-06-13 2007-06-13 Fuse circuit of semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070057583A KR20080109368A (en) 2007-06-13 2007-06-13 Fuse circuit of semiconductor apparatus

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KR20080109368A true KR20080109368A (en) 2008-12-17

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