KR20080107215A - The method and apparatus for writing in non-volatile memory, and the memory thereof - Google Patents

Abstract

A nonvolatile memory writing method is provided to correct threshold voltage change due to the coupling and reduce an unnecessary recording operation without recording data in a dummy memory cell which is not used in the recording operation. A nonvolatile memory writing method is comprised of steps: programming an n-th memory cell by a first target voltage lower than a target threshold voltage of the n burn memory cell when recording data in the n-th and the(n-1)th memory cell successively; programming the(n-1)-th memory cell by target threshold voltage of the(n-1)th memory cell; programming the n-th burn memory cell by the target threshold voltage of the n-th memory cell when the n-th memory cell is the final memory cell of the memory cells.

Description

The method and apparatus for writing in non-volatile memory, and the memory

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram showing a configuration of a memory device.

2 is a diagram illustrating a structure of a memory cell array.

3 is a diagram illustrating a detailed structure of a memory cell array.

4A to 4C are diagrams illustrating changes in threshold voltages of memory cells according to the present invention.

5 is a diagram illustrating a procedure of writing data into a memory cell array according to the present invention.

6 is a flowchart of a nonvolatile memory writing method according to the present invention.

7 is a diagram illustrating an input method of an instruction set.

The present invention relates to a non-volatile memory write method, device and memory device, and particularly to eliminate the operation of writing to a dummy cell when only a part of the memory cells in the block of the memory cell array are used. A write method, a device and a memory device having an instruction set of.

Non-volatile memory devices that can be electrically erased and programmed have a feature of preserving data even when power is not supplied. A typical flash memory is flash memory.

The memory cells constituting the flash memory are composed of cell transistors having a control gate, a floating gate, a source and a drain. The cell transistors of the flash memory are programmed / erased by the F-N tunneling mechanism.

The erase operation of the cell transistor is performed by applying a ground voltage to the control gate of the cell transistor, and applying a high voltage higher than the power supply voltage to the semiconductor substrate (or Ek). According to this erase bias condition, a strong electric field is formed between them by the large voltage difference between the floating gate and the bulk, and as a result, electrons present in the floating gate are released in bulk by the F-N tunneling effect. At this time, the threshold voltage of the erased cell transistor is moved in the negative direction.

The program operation of the cell transistor is achieved by applying a high voltage higher than the power supply voltage to the control gate and applying ground voltages to the drain and bulk. Under this bias condition, electrons are injected into the floating gate of the cell transistor by the F-N tunneling effect. At this time, the threshold voltage of the programmed cell transistor is moved in the positive direction.

When electrons are injected into the floating gate, capacitive coupling occurs due to capacitive components between adjacent cell transistors of the same bit line. This coupling shifts the threshold voltage distribution of adjacent cell transistors toward higher threshold voltages. As a result, the amount of change in the threshold voltage of the adjacent cell transistors is proportional to the amount of change in the threshold voltage due to power storage components and programs between the floating gates of the adjacent cell transistors. Due to the change in the threshold voltage, the threshold voltage distribution of adjacent cell transistors is changed, so that the threshold voltage is different from the predicted threshold voltage, thereby reducing the reliability of the memory device and reducing the noise margin.

The technical problem to be achieved by the present invention is to consider the change of the threshold voltage due to the coupling by the power storage component without the operation to program the dummy cell other than the memory cell to be written when using only some of the memory cells in the block There is provided a nonvolatile memory recording method, apparatus and memory device that are programmed to a computer.

According to the nonvolatile memory writing method according to the present invention for achieving the technical problem, when writing to the adjacent n-1 and n times memory cells are sequentially written, the target of the n times memory cell in the n memory cells A first step of programming to a first target voltage lower than a threshold voltage; a second step of programming the n-1 memory cell with a second threshold voltage which is a target threshold voltage of the n-1 memory cell; And writing the data into only a part of the memory cells in the block of the memory cell array, wherein the third memory cell is the target threshold voltage of the nth memory cell in the nth memory cell when the nth memory cell is the last memory cell of the some memory cells. And a third step of programming to a threshold voltage. When data is written only to some memory cells in the block of the memory cell array and the nth memory cell is the last memory cell of the some memory cells, the nth number of times is not programmed into an unused dummy cell adjacent to the nth memory cell. The word line is programmed with a third threshold voltage.

The target threshold voltage of the nth memory cell is a minimum threshold voltage of a threshold voltage distribution corresponding to a state of data to be written to the nth memory cell, and the target threshold voltage of the nth memory cell is n-1. It may be a minimum threshold voltage of a threshold voltage distribution corresponding to a state of data to be written to a memory cell.

The first step repeats the step of programming and verifying the memory cell until the threshold voltage of the nth memory cell reaches the first target voltage, and the second step is the n-1 memory Repeating the step of programming and verifying the memory cell until the threshold voltage of the cell reaches the second threshold voltage, and in the third step, the threshold voltage of the nth memory cell reaches the third threshold voltage. Program and verify the memory cell until the memory cell is repeated.

In the first to third program operations, a predetermined voltage is applied to a word line and a bit line connected to the memory cell to inject charge into a floating gate of the memory cell. The voltages applied to the word lines are different voltages, and the voltages applied to the word lines in the second and third steps are the target threshold voltage of the nth memory cell and the target threshold of the nth-1 memory cell. If the voltages are the same, the voltages applied to the word line are the same, and if the target threshold voltage of the nth memory cell and the target threshold voltage of the n-1 memory cell are different from each other, the voltages applied to the wordline may be different. have.

The second step may further include reading data written to the n-th memory cell, and the third step may further include reading data written to the n-th memory cell. have.

In the nonvolatile memory writing method according to the present invention, when writing to adjacent memory cells n-1 and n, which are sequentially written, data is written to all memory cells in a block of the memory cell array, or When data is written only to some memory cells in the block, and the memory cell n is not the last memory cell among the some memory cells, the program is performed to the memory cell n at a level lower than the target threshold voltage of the memory cell n. And performing a first instruction set for programming the n-1 memory cell to a target threshold voltage of the n-1 memory cell. And when data is written to only some of the memory cells in the block of the memory cell array and the word line n is the last memory cell of the some memory cells, the memory cell n has a lower level than the target threshold voltage of the memory cell n. A second instruction to program and program the target threshold voltage of the n-1 memory cell to the n-1 memory cell and then program the target threshold voltage of the n th memory cell to the n th memory cell Performing the set.

A first step of programming the n th memory cell with a first target voltage lower than a target threshold voltage of the n th memory cell; And programming a second threshold voltage to the n-1 memory cell as a target threshold voltage of the n-1 memory cell, and wherein the second instruction set is configured to the nth memory cell. The first step of programming to one target voltage; The second step of programming the second threshold voltage to the n-1 memory cell; And programming a third threshold voltage to the n th memory cell as a target threshold voltage of the n th memory cell.

The first step repeats the step of programming and verifying the memory cell until the threshold voltage of the nth memory cell reaches the first target voltage, and the second step is the n-1 memory Repeating the step of programming and verifying the memory cell until the threshold voltage of the cell reaches the second threshold voltage, and in the third step, the threshold voltage of the nth memory cell reaches the third threshold voltage. Program and verify the memory cell until the memory cell is repeated.

In the first to third program operations, a predetermined voltage is applied to a word line and a bit line connected to the memory cell to inject charge into a floating gate of the memory cell. The voltages applied to the word lines are different voltages, and the voltages applied to the word lines in the second and third steps are a target threshold voltage of the nth memory cell and a target threshold of the n-1 memory cell. If the voltages are the same, the voltages applied to the word line are the same, and if the target threshold voltage of the nth memory cell and the target threshold voltage of the n-1 memory cell are different from each other, the voltages applied to the wordline may be different. have.

The second step may further include reading data written to the n-th memory cell, and the third step may further include reading data written to the n-th memory cell. have.

A nonvolatile memory recording apparatus according to the present invention includes an instruction storage unit for storing a first instruction set and a second instruction set for programming an operation of writing to a memory cell array; And when writing to adjacent memory cells n-1 and n, which are sequentially written, when data is written to all memory cells in a block of the memory cell array, or only in some memory cells in the block of the memory cell array. If the nth memory cell is not the last memory cell among the some memory cells, the first instruction set is loaded from the instruction storage unit and executed. The data is stored only in the some memory cells in the block of the memory cell array. And a controller configured to load and execute the second instruction set from the instruction storage unit when the n-th word line is the last memory cell of the partial memory cells, and the first instruction set is stored in the n-th memory cell. The program is executed at a level lower than the target threshold voltage of the nth memory cell. program the target threshold voltage of the n-1 memory cell to the n-1 memory cell, the second instruction set is programmed to a level lower than the target threshold voltage of the n-th memory cell After programming the n-1 memory cell with the target threshold voltage of the n-1 memory cell, the n-th memory cell is programmed with the target threshold voltage of the nth memory cell.

A nonvolatile memory device according to the present invention includes a memory cell array that stores data at different threshold voltages in a nonvolatile manner; An instruction storage unit for storing at least one instruction set for programming an operation of writing the memory cell array; And a control unit which loads the instruction set from the instruction storage unit, and outputs an address signal and write data to the memory cell array according to the instruction set. When writing to memory cell n, data is written to all memory cells in a block of a memory cell array, or data is written only to some memory cells in the block of the memory cell array, and the memory cell n is stored in the partial memory. If the memory cell is not the last memory cell, the program is performed at a lower level than the target threshold voltage of memory cell n in memory cell n and the target threshold voltage of memory cell n-1 in memory cell n-1. Load the first instruction set from the instruction storage unit and execute the first instruction set; When data is written to only some of the memory cells in the previous block and the memory cell n is the last memory cell of the some memory cells, the program is programmed to the memory cell n at a level lower than the target threshold voltage of the memory cell n. And a second instruction set configured to program the target threshold voltage of the n-1 memory cell to the n-1 memory cell and then program the target threshold voltage of the n th memory cell to the n th memory cell. Load and execute from the command store.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a diagram illustrating a configuration of a nonvolatile memory device.

The nonvolatile memory includes a controller 110, a memory cell array 130, an instruction storage unit 150, and an I / O buffer and a latch 170. The instruction storage unit 150 stores at least one instruction set for controlling write and read operations of the memory device. As a nonvolatile storage medium, a register, a read only memory (ROM), or the like may be used. The controller 110 loads an instruction set corresponding to each operation from the instruction storage unit 150, and adds an address ADD, write activation WE to the memory cell array 130 according to the instructions stored in the instruction set. A read enable RE is output, and a control signal is output to the I / O buffer and the latch 170. The memory cell array 130 stores data non-volatilely. When the write operation is performed on the memory cell array 130, data is applied to the bit line, and the memory cell corresponding to the address signal ADD is selected as a word line and then written. At this time, the data to be written is applied to the bit line of the memory cell array through the I / O buffer and the latch 170 according to the control signal output from the controller 110, and the data read from the memory cell array 130 is read from the I / O buffer. It is output to the O buffer and the latch 170.

2 is a diagram illustrating a structure of a memory cell array.

The memory cell array 130 includes a plurality of memory cells connected to a bit line in a source / drain direction and a word line is connected to a control gate of each memory cell connected along the bit line. The word line is commonly connected to memory cells in the same row connected to different bit lines.

3 is a diagram illustrating a detailed structure of a memory cell array.

Each memory cell MC0, MC1, ..., MC31 corresponds to at least one cell transistor, and each cell transistor has a control gate, a floating gate, a source, and a drain. The source and the drain of each cell transistor are connected to the source or the drain of an adjacent cell transistor, and each control gate is connected to the word lines WL0, WL1, ..., WL31 according to the row position of the cell transistor. Is connected to. The word lines WL0, WL1,..., WL31 are commonly connected to control gates of cell transistors of the same row position connected to other bit lines (not shown). The memory cell array constitutes a block composed of a predetermined number of cell transistors, and the cell transistors connected to the first word line and the last word line of each block are connected to the ground potential (0V) and the bit line BL through the switching elements, respectively. Connected. It is switched by SSL and GSL signals. The writing and reading of data is performed in units of word lines WL0, WL1, ..., WL31, and the selection of the word lines WL0, WL1, ..., WL31 is performed by the controller 110 from the memory cell array 130. Is determined by the address signal ADD output to the signal.

4A to 4C are diagrams illustrating changes in threshold voltages of memory cells according to the present invention.

The nonvolatile memory injects electrons into the floating gate to perform a program operation, and removes electrons to perform an erase operation, thereby changing the threshold voltage and writing data. At this time, capacitive coupling occurs between the floating gates of adjacent cells connected to the source and the drain by capacitive components, and the coupling causes a change in the threshold voltage of the adjacent cells. Since the non-volatile memory determines the level of the recorded data by using the magnitude of the current flowing through the source and the drain when a constant voltage level is applied to the control gate, the change of the threshold voltage reduces the noise margin, thereby reducing the reliability of the memory. Greatly decreases. Hereinafter, the state in which the threshold voltage is changed by the power storage component and the method of correcting the same by using the power storage components are illustrated using FIGS. 4A to 4C showing threshold voltage distributions of two memory cells MCn and MCn-1 disposed in WLn and WLn-1. Explain. The A state is an erased state in which no charge is injected into the floating gate, and the B state is a program state in which a threshold voltage is increased due to charge injected into the floating gate. When a predetermined voltage between the maximum threshold voltage of the A state and the minimum threshold voltage of the B state is applied to the word line, the memory cell in the A state flows in the current, and the memory cell in the B state does not flow. The size may be measured to read data stored in the memory cell.

The MCn-1 of FIG. 4A is programmed to the B state (410), and the MCn is an unprogrammed erase state (420). 4B shows a state 425 programmed in the B state to the MCn memory cell of the nth word line in the state of FIG. 4A. The electrons are injected into the floating gate to program the MCn into the B state, and coupling between the capacitors and the MCn-1 that are adjacently connected through the source or the drain occurs. This causes the MCn-1 to shift to the threshold voltage direction with a higher threshold voltage distribution 410-1. In order to compensate for such a change in the threshold voltage distribution, a method of programming the first threshold voltage level lower than the target threshold voltage, programming the memory cell of the next word line, and then programming the target threshold voltage level again may be used. Can be.

4C shows that the memory cell MCn of the nth word line WLn is programmed and then reprogrammed into the memory cell MCn-1 of the n−1th word line WLn-1. Since the MCn-1 is coupled by the MCn and the threshold voltage is changed, the MCn-1 is reprogrammed to a higher threshold voltage Vth2 (hereinafter, referred to as a second threshold voltage). Therefore, the minimum threshold voltage of the memory cells having the B state among the memory cells in the n−1 th word line WLn−1 is changed from the first target voltage Vth1 to the second threshold voltage Vth2. As a result, the memory cells of the WLn-1 word line have a higher threshold voltage distribution than the threshold voltage distribution 410-1 shifted due to the coupling due to the capacitance generated by the memory cells in the WLn word line. The minimum threshold voltage of the memory cells having the B state in the WLn word line is programmed to the first target voltage Vth1.

Preferably, the second threshold voltage Vth2 may be a voltage higher than the first target voltage Vth1. Since the coupling by the power storage component shifts the threshold voltage distribution in the positive direction, when the second threshold voltage Vth2 is set to a voltage higher than the first target voltage Vth1, the coupling by the power storage component can be corrected. Can be.

The present invention can be applied to MLC (Multi Level Cell) memory as well as SLC (Single Level Cell) memory. For example, in the case of MLC memory in which two bits are stored in one memory cell, four states are generated, and thus the target threshold voltages for each state are four. Therefore, the first target voltage and the second threshold voltage of each memory cell are determined according to the target threshold voltage corresponding to the data to be written in each memory cell. In the example of FIGS. 4A to 4C, when data is recorded in another C state instead of the B state in the MCn, the minimum value of the threshold voltage distribution of the MCn becomes a third threshold voltage lower than the target threshold voltage of the C state.

5 is a diagram illustrating a procedure of writing data in the memory cell array 130 according to the present invention.

As described above with reference to FIGS. 4A through 4C, to program twice to the first target voltage Vth1 and the second threshold voltage Vth2 at each memory cell, the program process must be performed twice for each memory cell. In programming the memory cells sequentially in word line order, the programming of the first target voltage Vth1 in the nth memory cell and the second threshold voltage Vth2 in the n-1 memory cell are repeated. In the case of programming by using the above, in order to program to the second threshold voltage Vth2 which is the target threshold voltage in the memory cell of the last word line, it is necessary to program the dummy cell located in the next word line adjacent to the last word line. The present invention changes the programming process to the last memory cell in order to eliminate the operation of programming the dummy cell. That is, in the write operation for the memory cell other than the last memory cell, the memory cell is programmed with the first target voltage Vth1 in the nth memory cell and the second threshold voltage Vth2 with the n-1 memory cell, but the last memory In the write operation for the cell, when the memory cell n is the last word line, the memory cell is programmed with the first target voltage Vth1 in the n memory cell and the second threshold voltage Vth2 with the n-1 memory cell. The second threshold voltage Vth2 is programmed into the nth memory cell. Therefore, the program for the word line n can be completed without programming the first target voltage Vth1 in the n + 1 memory cell and the second threshold voltage Vth2 in the nth memory cell. have.

Meanwhile, the process of writing data to the memory cell array 130 is controlled by the instruction set. When the instruction set is loaded, the controller 110 performs a recording operation according to a process programmed in the instruction set. When the address signal ADD is applied, the controller 110 loads and executes a corresponding instruction set. In this case, if WLn and WLn-1 are programmed for each instruction set, n is incremented and sequentially programmed, the WLn and WLn-1 may be written to the memory cell array 130 as one instruction set. However, as shown in FIG. 5, when writing only to some memory cells MC0, MC1, ..., MC29, that is, some word lines WL0, WL1, ..., WL29 in the block, one instruction When writing using only a set, since a write operation must be performed to the dummy cell MC30 to program the second threshold voltage Vth2 to the last memory cell MC29, an additional write operation is required. In order to solve this problem, the present invention does not perform an operation for writing to the dummy cell MC30 by using a different instruction set for the last memory cell MC29 when using only some memory cells in a block. Can be reduced.

When using the first instruction set in FIG. 5 (Pre-PGM WL2 and Final-PGM WL1), the first target voltage Vth1 is a threshold voltage lower than the second threshold voltage Vth2 in the n-th memory cell MC2. And the second threshold voltage Vth2 to the n-1 th memory cell MC1. Preferably, if n is 0 (MC0), the step of programming to the n-1 memory cell may be skipped. If n is 32, the step of programming to the nth memory cell may be skipped.

When using the second instruction set (Pre-PGM WL29, Final-PGM WL28, and Final-PGM WL29), the n-th memory cell is programmed with the first target voltage Vth1 in the n-th memory cell MC29. After programming the second threshold voltage Vth2 to the MC28, the second threshold voltage Vth2 is programmed to the n-th memory cell MC29. Therefore, there is no need to program the dummy memory cell MC30 as in the case of using only one instruction set.

7 is a diagram illustrating an input method of an instruction set.

The instruction set consists of a start command 80h, an address & data ADD & DATA, and an operation command 10h or 20h. The first instruction set and the second instruction set vary according to the operation command. The first instruction set consists of 80h, ADD & DATA, and 10h, and the second instruction set consists of 80h, ADD & DATA, and 20h. The controller 110 determines and executes which of the two operation commands 10h or 20h is loaded and executed based on the address. After the instruction set is entered, the write operation is as follows. When the start command 80h is input, the write operation is started, and the address & data ADD & DATA are input. The first operation command 10h or the second operation command 20h is subsequently input by the address & data DATA. The controller 110 performs a write operation according to a process programmed in the first operation command 10h or the second operation command 20h.

If data is written to only some of the memory cells in the block, the first instruction set is repeatedly executed until the last memory cell (80h, ADD & DATA, and 10h), and when the last memory cell is reached, the second instruction set is executed. After 80h, ADD & DATA, and 20h, the recording operation ends at 20h.

The present invention can also be used in MLC type memory. When the MLC method is used, the third threshold voltage which is the minimum value in the threshold voltage distribution corresponding to the data to be written in the memory cell 29 instead of the second threshold voltage Vth2 when programming to the memory cell MC29 29. Program with.

6 is a flowchart of a nonvolatile memory writing method according to the present invention.

The control unit 110 loads a corresponding instruction set from the instruction storage unit 150 according to the address signal, and writes an address signal (S) to write data to the memory cell array 130 according to a process of the loaded instruction set. ADD), a read signal RE, and a write signal WE are output, and a control signal is output to the I / O buffer and the latch 170. The I / O buffer and the latch 170 output data to the memory cell array 130 according to the control signal. The instruction set according to the present invention has a first instruction set and a second instruction set. The second instruction set is loaded when data is written only to some memory cells in the block, when writing data to the last memory cell of some memory cells (MC29 in FIG. 5), and the first instruction set is loaded by the second instruction set. When the data is written to all the memory cells in the block of the memory cell array, or when the data is written to only some memory cells in the block of the memory cell array, It is loaded when it is not the last memory cell MC29. Hereinafter, the flowchart of FIG. 6 will be described in detail.

When the recording operation is started, the controller 110 loads the first instruction set or the second instruction set from the instruction storage unit 150 according to the address signal ADD (S610). The controller 110 outputs the address signal ADD n and the activated write signal WE to the memory cell array 130 (S612), and outputs a control signal to the I / O buffer and the latch 170. The I / O buffer and the latch 170 output data to be written to the memory cell array 130 according to the control signal (S614). When the instruction set is loaded in the controller 110, the recording operation is performed differently when the first instruction set is loaded and when the second instruction set is loaded.

When the first instruction set is loaded, the n-th memory cell MCn is programmed with the first target voltage Vth1 (S620), and it is checked whether the first target voltage Vth1 has been reached (S622). If the first target voltage Vth1 is not reached, the program is again programmed to the nth memory cell MCn with the first target voltage Vth1 (S620), and the first target voltage Vth1 is checked. The process (S622) is repeated (S624). When the memory cell of the nth word line WLn reaches the first target voltage Vth1 (S624), the data written to the n-1th memory cell is read (S626). The n-th cell remains in the state of being written by the write operation on the n-1 address signal before the write operation is performed on the n-th address signal. The n-1th cell is programmed with the first target voltage if it has data in the B state (the state shifted from the first target voltage if it is programmed with B in the nth memory cell), and floats with the level of the A state The gate has a threshold voltage distribution in which electrons are erased. The read data may be stored in a storage medium such as a latch. The data written in the n-1 th memory cell is read, and the data of the corresponding level is written again in the n-1 th word line WLn-1 (S628). In this case, when the n−1 th memory cell has the level of the B state, it is programmed to the second threshold voltage Vth2 (S628), and the controller 110 checks whether the second threshold voltage Vth2 has been reached (S630). ). If the second threshold voltage Vth2 has not been reached, the process rewrites the memory cell with the second threshold voltage Vth2 (S628) and checks whether the second threshold voltage Vth2 has been reached (S630). When the second threshold voltage Vth2 is reached, the write operation of the nth memory cell is terminated (S632).

Preferably, when programming to the first target voltage (Vth1) and when programming to the second threshold voltage (Vth2), different voltages may be applied to the word line. When the threshold voltages are different from each other, the voltage applied to the word line also varies because the amount of electrons injected into the floating gate is different.

When the second instruction set is loaded, data is written to the memory cell of the nth word line WLn at the first target voltage Vth1 (S650), and the first target voltage Vth1 is checked. (S652). When the n th memory cell does not reach the first target voltage Vth1, the n th memory cell writes the first target voltage Vth1 again to the n th memory cell (S650) and checks whether the first target voltage Vth1 has been reached. The operation S652 is repeated (S654). When the n th memory cell reaches the first target voltage, data written to the n−1 th memory cell is read (S656). If the read data level has the B state level, the read data is written as the second threshold voltage Vth2 in the memory cell of the n−1th word line WLn-1 (S658) and the second threshold voltage Vth2. Check whether or not to reach (S660). If the n−1 th memory cell does not reach the second threshold voltage Vth2, the data is rewritten with the second threshold voltage Vth2 (S658) and the second threshold voltage Vth2 is checked. The process (S660) is repeated (S662). When the second threshold voltage Vth2 is reached, data is read in order to rewrite the second threshold voltage Vth2 to the nth memory cell written at the first target voltage Vth1 (S662 and S664). When the n-th memory cell is in the B state, the n-th word line WLn is written with the second threshold voltage Vth2 (S666), and it is checked whether the second threshold voltage Vth2 has been reached (S668). When the second threshold voltage Vth2 is not reached (S670), the memory cell of the nth word line WLn is written as the second threshold voltage Vth2 (S666) and whether the second threshold voltage Vth2 has been reached. The operation for checking whether or not (S668) is repeated. When the n th memory cell reaches the second threshold voltage (S670), the write operation for the nth address is terminated.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the non-volatile memory writing method, apparatus, and Mary apparatus according to the present invention have a threshold voltage due to coupling by a power storage component without writing to a dummy memory cell which is not used in a write operation using only some memory cells in a block. It is possible to correct the changing phenomenon, thereby reducing the unnecessary recording operation.

Claims (15)

A nonvolatile memory writing method for recording data by adjusting a threshold voltage of a memory cell, wherein when writing to adjacent n-1 and nth memory cells that are sequentially written, A first step of programming the n th memory cell with a first target voltage lower than a target threshold voltage of the n th memory cell; A second step of programming the n-1 memory cell with a second threshold voltage which is a target threshold voltage of the n-1 memory cell; And When data is written only to some memory cells in a block of a memory cell array, and the n th memory cell is the last memory cell among the some memory cells, the third threshold which is a target threshold voltage of the n th memory cell in the n th memory cell A nonvolatile memory writing method comprising a third step of programming with a voltage. The method of claim 1, wherein the nonvolatile memory writing method comprises: When data is written only to some memory cells in the block of the memory cell array and the nth memory cell is the last memory cell of the some memory cells, the nth number of times is not programmed into an unused dummy cell adjacent to the nth memory cell. A nonvolatile memory writing method comprising: programming a word line to a third threshold voltage. The method of claim 1, The target threshold voltage of the nth memory cell is a minimum threshold voltage of a threshold voltage distribution corresponding to a state of data to be written to the nth memory cell, The target threshold voltage of the n-1 memory cell is a minimum threshold voltage of a threshold voltage distribution corresponding to a state of data to be written to the n-1 memory cell. The method of claim 1, The first step may include repeating programming and verifying the memory cell until the threshold voltage of the nth memory cell reaches the first target voltage. The second step may include repeating programming and verifying the memory cell until the threshold voltage of the n-1 memory cell reaches the second threshold voltage. And the third step of repeating programming and verifying the memory cell until the threshold voltage of the nth memory cell reaches the third threshold voltage. The method of claim 1, In the first to third program operations, a predetermined voltage is applied to a word line and a bit line connected to the memory cell to inject charge into a floating gate of the memory cell. Voltages applied to the word lines in the first and third steps are different voltages, In the second and third steps, the voltage applied to the word line is equal to the voltage applied to the word line when the target threshold voltage of the nth memory cell and the target threshold voltage of the n−1 memory cell are the same. And when the target threshold voltage of the n-th memory cell and the target threshold voltage of the n-th memory cell are different from each other, voltages applied to the word line are different from each other. The method of claim 1, The second step may further include reading data written to the n-1 memory cell. And the third step further comprises reading data written to the nth memory cell. A nonvolatile memory writing method for recording data by adjusting a threshold voltage of a memory cell, wherein when writing to adjacent n-1 and nth memory cells that are sequentially written, When data is written to all the memory cells in a block of a memory cell array or when data is written to only some memory cells in the block of the memory cell array and the nth memory cell is not the last of the some memory cells, Perform a first instruction set to program the memory cell n to a level lower than the target threshold voltage of memory cell n and to program the memory cell n-1 to a target threshold voltage of memory cell n-1. Doing; And When data is written only to some memory cells in a block of a memory cell array and the word line n is the last memory cell of the some memory cells, the memory cell is programmed to a level lower than the target threshold voltage of the memory cell n. And a second instruction set for programming the target threshold voltage of the n-1 memory cell to the n-1 memory cell and then programming the target threshold voltage of the n th memory cell to the n th memory cell. Non-volatile memory recording method comprising the step of performing. The method of claim 7, wherein The first instruction set is A first step of programming the n th memory cell with a first target voltage lower than a target threshold voltage of the n th memory cell; And And programming a second threshold voltage into the n-1 memory cell as a target threshold voltage of the n-1 memory cell. The second instruction set is The first step of programming the first target voltage to the nth memory cell; The second step of programming the second threshold voltage into the n-1 memory cell; And And programming a third threshold voltage into the n th memory cell as a target threshold voltage of the n th memory cell. The method of claim 8, The first step may include repeating programming and verifying the memory cell until the threshold voltage of the nth memory cell reaches the first target voltage. The second step may include repeating programming and verifying the memory cell until the threshold voltage of the n-1 memory cell reaches the second threshold voltage. And the third step of repeating programming and verifying the memory cell until the threshold voltage of the nth memory cell reaches the third threshold voltage. The method of claim 8, In the first to third program operations, a predetermined voltage is applied to a word line and a bit line connected to the memory cell to inject charge into a floating gate of the memory cell. Voltages applied to the word lines in the first and third steps are different voltages, In the second and third steps, the voltage applied to the word line is equal to the voltage applied to the word line when the target threshold voltage of the nth memory cell and the target threshold voltage of the n−1 memory cell are the same. And when the target threshold voltage of the n-th memory cell and the target threshold voltage of the n-th memory cell are different from each other, voltages applied to the word line are different from each other. The method of claim 8, The second step may further include reading data written to the n-1 memory cell. And the third step further comprises reading data written to the nth memory cell. A nonvolatile memory recording apparatus for recording data by adjusting a threshold voltage of a memory cell, An instruction storage unit for storing a first instruction set and a second instruction set for programming an operation of writing to a memory cell array; And When writing to adjacent memory cells n-1 and n sequentially written, data is written to all memory cells in a block of a memory cell array, or data is written only to some memory cells in the block of the memory cell array. And when the nth memory cell is not the last memory cell of the some memory cells, the first instruction set is loaded from the instruction storage unit and executed. The data is written only to the some memory cells in the block of the memory cell array. And a control unit which loads and executes the second instruction set from the instruction storage unit when the n-th word line is the last memory cell of the partial memory cells.  The first instruction set executes a program at a level lower than a target threshold voltage of the nth memory cell in the nth memory cell, and programs the target threshold voltage of the n-1 memory cell in the n-1 memory cell. , The second instruction set is programmed to the n th memory cell at a level lower than the nth target cell voltage and the n-1 memory cell to the target threshold voltage of the n-1 memory cell. And programming the n th memory cell with a target threshold voltage of the n th memory cell. The method of claim 12, The first instruction set is A first step of programming the n th memory cell with a first target voltage lower than a target threshold voltage of the n th memory cell; And And programming a second threshold voltage into the n-1 memory cell as a target threshold voltage of the n-1 memory cell. The second instruction set is The first step of programming the first target voltage to the nth memory cell; The second step of programming the second threshold voltage into the n-1 memory cell; And And programming a third threshold voltage to the n th memory cell as a target threshold voltage of the n th memory cell. A nonvolatile memory device that writes data by adjusting a threshold voltage of a memory cell, A memory cell array that stores data at different threshold voltages in a nonvolatile manner; An instruction storage unit for storing at least one instruction set for programming an operation of writing the memory cell array; And A control unit which loads the instruction set from the instruction storage unit and outputs an address signal and write data to the memory cell array according to the instruction set, When the controller writes to the adjacent n-1 and nth memory cells that are sequentially written, When data is written to all memory cells in a block of a memory cell array, or when data is written to only some memory cells in the block of the memory cell array, and the nth memory cell is not the last of the some memory cells. The first instruction set for performing a program at a level lower than the target threshold voltage of the n-th memory cell to the n-th memory cell and programming the target threshold voltage of the n-1 memory cell to the n-1 memory cell Load and run from storage, When data is written only to the some memory cells in the block of the memory cell array and the nth memory cell is the last memory cell of the some memory cells, the nth memory cell is smaller than the target threshold voltage of the nth memory cell. After programming to a low level, the n-1 memory cell is programmed to the target threshold voltage of the n-1 memory cell and the n memory cell to program the target threshold voltage of the n th memory cell 2. A nonvolatile memory device which executes a command set by loading the instruction set from the instruction storage unit. The method of claim 14, The first instruction set is A first step of programming the n th memory cell with a first target voltage lower than a target threshold voltage of the n th memory cell; And And programming a second threshold voltage into the n-1 memory cell as a target threshold voltage of the n-1 memory cell. The second instruction set is The first step of programming the first target voltage to the nth memory cell; The second step of programming the second threshold voltage to the n-1 memory cell; And And programming a third threshold voltage into the nth memory cell as a threshold voltage of the nth memory cell.

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