KR20080102927A - Apparatus and method for address generation of data interleaver/deinterleaver - Google Patents

Abstract

An apparatus and a method for generating an address of a data interleaver/deinterleaver remove an address generation error of the deinterleaver by generating the address by an address generation polynomial of the interleaver. An address generation device of an interleaver includes an exponent decision unit, a coefficient calculation unit, and an address generation unit. The exponent decision unit(210) calculates a prime factor comprising the size of a bit and decides the exponent according to the number of the prime factor. The coefficient calculation unit(230) calculates the coefficient of the address generation polynomial of the interleaver base on the prime factor and the exponent. The address generation unit(250) generates the address by the polynomial using the coefficient.

Description

Apparatus and method for address generation of data interleaver / deinterleaver}

The present invention relates to an apparatus and method for generating an address of a data interleaver / deinterleaver, and more particularly, in a system for performing data interleaving and deinterleaving in parallel, a coefficient calculated based on a prime factor constituting a length of input data. Address generation device of interleaver by generating address by polynomial to enable deinterleaver to generate correct address, and interleaver / deinterleaver address generation device that can perform data interleaving and deinterleaving in parallel without address conflict And to a method.

The present invention is derived from the research conducted as part of the IT new growth engine core technology development project of the Ministry of Information and Communication [Task management number: 2005-S-404-13, task name: 3G Evolution wireless transmission technology development].

Channel coding such as turbo coding is used to increase data transmission efficiency in communication systems.

1 is a representative turbo encoder in the related art, which is described in "3GPP TS 25.212, 3GPP TS GRAN" Multiplexing and channel coding (FDD) "(hereinafter referred to as 'Reference 1').

Referring to FIG. 1, the turbo encoder 100 includes two eight state component encoders 101 and 103 and one turbo coded interleaver 102, and a parallel concatenated convolutional code (PCCC). Perform channel coding using. The output data of the data Xk input to the turbo encoder are Xk, Zk, Z'k, and X'k.

The interleaver 102 includes an address generator for generating an address of the input data using the address generation polynomial, and interleaves the input data according to the generated address.

The document "On Maximum Contention-Free Interleavers and Permutation Polynomials Over Integer Rings" (IEEE Trans. On Information Theory, Vol. 52, No. 3, March 2006, Oscar Y. Takeshita) (hereinafter referred to as 'Ref. 2') A data interleaving method is proposed to perform data interleaving and deinterleaving in parallel, to prevent address collisions in parallel processing, and to simplify hardware complexity. The data interleaving scheme described in Reference 2 calculates an interleaving address of data using an interleaver's address generation polynomial, and interleaves data according to this address.

In the present invention, in the method of calculating the coefficients f ₁ and f ₂ of the address generation polynomial of the conventional interleaver, a method of calculating f ₂ capable of eliminating the address generation error of the deinterleaver and calculating the correct interleaver and deinterleaver address is provided. Suggest.

An object of the present invention is to provide a method for calculating coefficient values of an address generation polynomial of an interleaver used for address generation of a turbo internal interleaver and a deinterleaver used in a turbo encoder and a turbo decoder.

Another object of the present invention is to provide a method for generating a correct address of a deinterleaver generated using coefficients of an address generation polynomial of an interleaver generated according to the present invention.

Other objects and advantages of the present invention can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

In order to solve the above technical problem, an address generator of an interleaver for input data of a predetermined bit of the present invention includes: an exponent determining unit configured to calculate a prime factor constituting the bit size and determine an index according to the number of each prime factor. ; A coefficient calculator which calculates coefficients of the address generation polynomial of the interleaver based on the prime factors and the exponent; And an address generator for generating an address by the polynomial using the coefficient.

In order to solve the above technical problem, an address generator of a deinterleaver for a predetermined bit of interleaving data of the present invention calculates a coefficient of an address generation polynomial of the deinterleaver based on a coefficient of an address generation polynomial of the interleaving data. Coefficient calculating unit; And an address generator configured to generate an address of the deinterleaver by using the coefficient generation polynomial of the deinterleaver, wherein the coefficient of the address generation polynomial of the interleaving data includes: a prime factor constituting the size of the bit; Characterized in accordance with the index according to the number of each prime factor.

In order to solve the above technical problem, an address generation method of an interleaver for input data of a predetermined bit, the method comprising: calculating a prime factor constituting the size of the bit; Determining an index according to the number of each of the prime factors; Calculating coefficients of the address generation polynomial of the interleaver based on the prime factors and exponents; And generating an address by the polynomial using the coefficients.

In order to solve the above technical problem, a method of generating an address of a deinterleaver for a predetermined bit of interleaving data according to the present invention includes calculating a coefficient of an address generation polynomial of the deinterleaver based on a coefficient of an address generation polynomial of the interleaving data. step; And generating the address of the deinterleaver by the address generation polynomial of the deinterleaver using the coefficients, wherein the coefficients of the address generation polynomial of the interleaving data comprise a prime factor and the respective constituents of the bit size. Characterized in that calculated based on the index according to the number of prime factors.

The present invention for achieving the above technical problem can provide a computer-readable recording medium recording a program for executing the address generation method of the interleaver and the address generation method of the deinterleaver.

According to the present invention, the exponent of each prime factor is determined according to the number of the prime factors constituting the length of the interleaver input data, and the coefficient of the interleaver address generation polynomial is calculated, and the address of the deinterleaver is generated by using the coefficient of the deinterleaver. You can eliminate errors at generation time and calculate the correct interleaver and deinterleaver address.

In particular, if the prime factor contains 2, the interleaver address generation polynomial f (x) = mod (f ₁ x + f ₂ x ² , K) (x = 0,…, K-1, where K is the interleaver input data size By calculating at least two coefficients of f ₂ , multiply the address generation of the deinterleaver using the calculated f ₂ poly (g) = mod (g ₁ x + g ₂ x ² , K) (x = 0, ..., K-1, where K is an interleaver input data size, and by calculating the coefficients g ₁ , g ₂ and generating the deinterleaver address, accurate deinterleaver address generation is possible.

In addition, the present invention provides a system for performing data interleaving and deinterleaving in parallel, to perform data interleaving and deinterleaving in parallel without collision of addresses, and without interleaving and deinterleaver address to store the interleaver and deinterleaver address Compute the address using a generator polynomial to simplify hardware complexity.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the same elements among the drawings are denoted by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

In the present invention, the address generation polynomial f (x) = mod (f ₁ x + f ₂ x ² , K) (x = 0, ..., K-1, where K is the interleaver input data size) for generating the address of the interleaver A method of generating coefficient f ₂ is proposed, and the address generation polynomial of the deinterleaver using f ₂ generated in this way is defined as g (x) = mod (g ₁ x + g ₂ x ² , K) (x = 0, ..., K-1, where K can provide the correct deinterleaver address when generating coefficients g ₁ , g ₂ of interleaver input data size).

In the present invention, since the input data is described as an example of K bits, the bit size K may be used interchangeably as the length or size of the input data.

In Reference 2, the address generation polynomial of the data interleaver is

f (x) = mod (f ₁ x + f ₂ x ² , K) (x = 0,…, K-1, where K is the interleaver input data size),

The deinterleaver's address generation polynomial is

g (x) = mod (g ₁ x + g ₂ x ² , K) (x = 0, ..., K-1, where K is the interleaver input data size).

Here, mod (a, b) is a modulus operation value for b of a, which is the remainder of a divided by b. For example, mod (3,10) = 3 and mod (-3,10) = 3.

A method of calculating the coefficients f ₁ and f ₂ of the address generation polynomial of the interleaver is as follows.

이다. 일 예로, K=40 인 경우, P={2,5} 이며 K = 2³x5 이다. The length of the input data of the interleaver is K, the set of prime factors constituting K is P, and the elements of P are P = {p ₁ , p ₂ , .. p _N }. At this time

to be. For example, when K = 40, P = {2,5} and K = 2 ³ x5.

1) if K is not a multiple of 2 or K is a multiple of 4,

Calculate f ₁ : f ₁ satisfying gcd (f ₁ , K) = ₁

Calculate f ₂ :

2) if K is a multiple of 2 and K is not a multiple of 4,

Calculate f ₁ : f ₁ satisfying gcd (f ₁ , K / 2) = ₁

f ₂ calculation: f ₁ + f ₂ is odd,

Where gcd (a, b) is the greatest common divisor of a and b.

Therefore, when K = 40, P = {2,5} and K = 2 ³ x5, so f ₁ ∈ {3,7,9,11,13, .. 39} and f ₂ ∈ {10, 20,30,40}.

However, the method of calculating f ₂ does not apply to all K.

이고,

를 계산하기 위하여 아래의 조건을 만족해야 한다.Document "On Quadratic Inverses for Quadratic Permutation Polynomials Over Interger Rings" (IEEE Trans. On Information Theory, Vol. 52, No. 3, March 2006, Jonghoon Ryu and Oscar Y. Takeshita) Describes how to calculate f ₂ for all K's. In reference 3 above.

ego,

The following conditions must be met to calculate.

(식 1)

(Equation 1)

(식 2)

(Equation 2)

(식 3)

(Equation 3)

In this case, the address generation polynomial of the deinterleaver is g (x) = mod (g ₁ x + g ₂ x ² , K) (x = 0,…, K-1, where K is the interleaver input data size), and this is calculated. See reference 3 for a way to do this. For example, K = 40 and (g ₁ , g ₂ ) = (27,10) or (7,30) for (f ₁ , f ₂ ) = (3,10).

The address generation method of the data interleaver according to the reference 2, the address generation polynomial f (x) = mod (f ₁ x + f ₂ x ² , K) (x = 0, ..., K-1, where K is the interleaver Input data size) and the deinterleaver's address generation polynomial g (x) = mod (g ₁ x + g ₂ x ² , K) (x = 0,…, K-1, where K is the interleaver input data size ), We use the computed f ₁ and f ₂ to obtain the interleaver address. Also, referring to Reference 3, g ₁ and g ₂ may be calculated using the obtained f ₁ and f ₂ , and the address of the deinterleaver may be obtained using the calculated g ₁ and g ₂ . However, the address of the deinterleaver using f ₁ and f ₂ obtained by the reference 2 is not accurate.

For example, in the case of K = 96, since P = {2,3} and K = 2 ⁵ x3, f ₁ ∈ {5,7,11,13, .. 95} and f ₂ ∈ {2x3x1,2x3x2, 2x3x3, 2x3x4, 2x3x5,... , 2x3x16}. At this time, each of the values of f ₁ and f ₂ is selected to interleave data according to the address generation polynomial f (x) = mod (f ₁ x + f ₂ x ² , K) of the interleaver, and based on reference 3 After generating g ₁ , g ₂ using f ₁ , f ₂ , we perform data deinterleaving according to the address generation polynomial g (x) = mod (g ₁ x + g ₂ x ² , K) of the deinterleaver. If f _{2 2} {2x3x1,2x3x3,2x3x5,... 2x3x15}, the wrong deinterleaver address is generated. That is, the method of generating f _{2 according} to Reference 1 has a problem that an error occurs when generating an address of some deinterleaver.

Further, according to Reference 3, when K = 90, P = {2,3,5} and K = 2x3 ² x5, so f _{1 1} {7,11,13, .. 89} and f ₂ ∈ {3x5x1 , 3x5x2,3x5x3,3x5x4,3x5x5,3x5x6}. At this time, each of the values of f ₁ and f ₂ is selected to interleave the data according to the address generation polynomial f (x) = mod (f ₁ x + f ₂ x ² , K) of the interleaver. The deinterleaver calculates g ₁ , g ₂ using f ₁ , f ₂ and then deinterleaves the data according to the address generation polynomial g (x) = mod (g ₁ x + g ₂ x ² , K) of the deinterleaver. In this case, an incorrect deinterleaver address is generated for f ₂ ∈ {3x5x1,3x5x3,3x5x5}. That is, the method of generating f _{2 according} to Reference 3 has a problem that an error occurs when generating some deinterleaver addresses.

The address generation apparatus of the interleaver for data interleaving in the present invention is based on the data interleaving scheme described in Reference 2 above.

In Reference 2, the address generation polynomial of the data interleaver is f (x) = mod (f ₁ x + f ₂ x ² , K) (x = 0,…, K-1, where K is the interleaver input data size), The deinterleaver's address generation polynomial is g (x) = mod (g ₁ x + g ₂ x ² , K) (x = 0, ..., K-1, where K is the interleaver input data size). Here, mod (a, b) is a modulus operation value for a of b, which is the remainder of a divided by b.

이다. The length of the input data of the interleaver is K, the set of prime numbers constituting K is P, and the elements of P are P = {p ₁ , p ₂ , _{... ,} p _N }. At this time

to be.

이고,

를 계산하기 위하여 소인수 p의 지수 n_{F ,p}는 아래의 조건 식에 따라 결정된다.

ego,

In order to calculate, the exponent n _{F ,} p of the prime factor p is determined according to the following conditional expression.

(식 4)

(Equation 4)

(식 5)

(Eq. 5)

(식 6)

(Equation 6)

The final f ₂ calculated using the results calculated in Equations 4, 5, and 6 is shown in Equation 7 below.

(식 7)

(Eq. 7)

Referring to Equations 4 to 6, f ₂ is calculated by multiplying each prime factor constituting K of the K bit input data and an arbitrary integer. The exponent of the prime factor to be multiplied depends on the prime factors (minors 2, 3, 2 and 3) and the number of prime factors, so f ₂ is a multiple of the prime factor.

Referring to Equation 4, when two of the constituent prime factors of K are present, if the number of two is one or more and four or less, the index of 2 is determined to be 1, and the coefficient f ₂ has a multiple value of 2. If the number of 2 is 5 or more, that is, (2 xn + 1) or (2 xn + 2) (where n is an integer of 2 or more), the exponent of ₂ is determined as n, and the coefficient f ₂ is 2 has a multiple of ⁿ

Referring to Equation 5, when three of the constituent prime factors of K are present, if the number of two is one or more and three or less, the index of three is determined to be one, and the coefficient f ₂ has a multiple of three. If the number of 3 is four or more, that is, (2 x n) or (2 x n + 1), where n is an integer of 2 or more, the exponent of 3 is determined by n, and the coefficient f ₂ is 3 ⁿ . Has a multiple value.

Referring to Equation 6, if there is a prime number p except for 2 and 3 among the constituent factors of K, the number of prime factors p is one or more, that is, (2 xn-1) or (2 xn) (where, n is an integer of 1 or more), the index of p is determined by n, and the coefficient f ₂ has a multiple of p ⁿ .

2 is a block diagram schematically illustrating an apparatus for generating an address of an interleaver according to an exemplary embodiment of the present invention. 4 is a flowchart illustrating an address generation method by an address generator of an interleaver according to an embodiment of the present invention.

Hereinafter, the operation of the address generator of the interleaver of FIG. 2 will be described with reference to FIG. 4, and a detailed description of the overlapping configuration will be omitted.

2 and 4, the address generator 200 of the interleaver according to the present invention includes an index determiner 210, a coefficient calculator 230, and an address generator 250.

The index determining unit 210 calculates the prime factors constituting the length K of the K bit input data (S410), and determines the index of each prime factor according to the calculated number of prime factors (S430). The exponential determination formula of the prime factor may refer to Equations 4 to 6.

Coefficient calculating unit 230 is an address generated based on the determined prime factor and index polynomial f (x) = mod (f 1 x + f 2 x 2, K) (x = 0, ..., K-1) coefficient f ₁ of And f ₂ is calculated (S450). The coefficient f ₁ is calculated by the product of the prime factors excluding the prime factors constituting K. The coefficient f ₂ is calculated as the product of each prime factor constituting K and a random integer, and by the exponent of each prime factor determined, f ₂ has a multiple of the power of the prime factor.

The address generator 250 generates an address by the polynomial f (x) using coefficients f ₁ and f ₂ (S470).

3 is a block diagram schematically illustrating an apparatus for generating an address of a deinterleaver according to an exemplary embodiment of the present invention. 5 is a flowchart illustrating an address generation method by the address generator of the deinterleaver according to an exemplary embodiment of the present invention.

Hereinafter, the operation of the apparatus for generating the address of the deinterleaver of FIG. 3 will be described with reference to FIG. 5, and a detailed description of the overlapping configuration will be omitted.

3 and 5, the address generator 300 of the deinterleaver includes a coefficient calculator 310 and an address generator 350. In general, the deinterleaver has the same structure in that the memory write sequence and the read sequence are opposite to the interleaver during address generation.

The coefficient calculating unit 310 is a polynomial g (x) = mod (g ₁ x + g ₂ x ² , K) (x = 0, ..., K-1 for generating a deinterleaver address for K-bit interleaving data. Coefficients g ₁ and g ₂ are calculated (S510). The coefficients g ₁ and g ₂ are the polynomials calculated from the address generator of the interleaver f (x) = mod (f 1 x + f 2 x 2, K) (x = 0, ..., K-1) coefficient f ₁ of And f ₂ . The quadratic coefficient f ₂ of the polynomial f (x) is a value calculated based on the prime factors constituting the K and the exponents of the prime factors determined according to the number of the prime factors.

If the prime factors constituting K include 2 and the number of 2 is (2 xn + 1) or (2 xn + 2) (where n is an integer of 2 or more), the coefficients g ₁ and g ₂ are coefficients Calculated based on the coefficient f ₂ with multiples of f ₁ and 2 ⁿ . If the number of prime factors 2 is 1 or more and 4 or less, the coefficients g ₁ and g ₂ are calculated based on the coefficient f ₂ with multiples of the coefficients f ₁ and 2.

If 3 is included in the prime factors constituting K, and the number of 3 is one or more and three or less, the coefficients g ₁ and g ₂ are calculated based on f ₂ having a multiple of the coefficients f ₁ and 3. If the number of prime factors 3 is (2 xn) or (2 xn + 1) (where n is an integer of 2 or more), the coefficients g ₁ and g ₂ are f ₂ with multiples of the coefficients f ₁ and 3 ⁿ Is calculated on the basis of

If the prime factors constituting K include prime factors p except 2 and 3, and the number of prime factors p is (2 x n-1) or (2 x n), where n is an integer of 1 or more, the coefficient g ₁ and g ₂ are calculated based on f ₂ with multiples of the coefficients f ₁ and p ⁿ .

The address generator 350 generates a deinterleaver address by the polynomial g (x) using the coefficients g ₁ and g ₂ (S550).

In the case of applying the interleaver address and deinterleaver address generation method according to the present invention, when K = 90, P = {2,3,5} and K = 2x3 ² x5, so that f _{1 1} {7,11,13, ..89} and f ₂ ∈ {2x3x5x1,2x3x5x2,2x3x5x3}.

At this time, the address generator of the interleaver in the encoder selects one of the values of f ₁ and f ₂ and interleaves data according to the address generation polynomial f (x) = mod (f ₁ x + f ₂ x ² , K). .

The decoder receives the interleaved data from the encoder, the address generator of the deinterleaver in the decoder calculates g ₁ , g ₂ using f ₁ , f ₂ , and then deinterleaver address generation polynomial g (x) = mod ( Perform data deinterleaving according to g ₁ x + g ₂ x ² , K).

Therefore, the correct interleaver address and deinterleaver address can be obtained for all (f ₁ , f ₂ ) and (g ₁ , g ₂ ).

The table below coefficients f ₁ and f of the method used by address generator polynomial of the interleaver to the input data length K to the interleaver f (x) = mod (f 1 x + f 2 x 2, K) the proposed in the present invention _An example of the result of generating ₂ is shown.

Interleaver Input Bits (K) f ₁ (the product of decimals except for (p ₁ , p ₂ ,…, p _n )) f ₂ (m = 1,2,3,…) Remarks 24 (2,3) mod (2 x 3 x m, K) 25 (5) mod (5 x m, K) 26 (2,13) mod (2 x 13 x m, K) 27 (3) mod (3 x m, K) 28 (2,7) mod (2 x 7 x m, K) 29 (29) mod (29 x m, K) 30 (2,3,5) mod (2 x 3 x 5 x m, K) 31 (31) mod (31 x m, K) 32 (2) mod (4 x m, K) 33 (3,11) mod (3 x 11 x m, K) 34 (2,17) mod (2 x 17 x m, K) 35 (5,7) mod (5 x 7 x m, K) 36 (2,3) mod (2 x 3 x m, K) 37 (37) mod (37 x m, K) 38 (2,19) mod (2 x 19 x m, K) 39 (3,13) mod (3 x 13 x m, K) 40 (2,5) mod (2 x 5 x m, K) 42 (2,3,7) mod (2 x 3 x 7 x m, K) 44 (2,11) mod (2 x 11 x m, K) 46 (2,23) mod (2 x 23 x m, K) 48 (2,3) mod (2 x 3 x m, K) 50 (2,5) mod (2 x 5 x m, K) 52 (2,13) mod (2 x 13 x m, K) 54 (2,3) mod (2 x 3 x m, K) 56 (2,7) mod (2 x 7 x m, K) 58 (2,29) mod (2 x 29 x m, K) 60 (2,3,5) mod (2 x 3 x 5 x m, K) 62 (2,31) mod (2 x 31 x m, K) 64 (2) mod (4 x m, K) 66 (2,3,11) mod (2 x 3 x 11 x m, K) 68 (2,17) mod (2 x 17 x m, K) 70 (2,5,7) mod (2 x 5 x 7 x m, K)  Interleaver Input Bits (K) f ₁ (the product of decimals except for (p ₁ , p ₂ ,…, p _n )) f ₂ (m = 1,2,3,…) Remarks 72 (2,3) mod (2 x 3 x m, K) 80 (2,5) mod (2 x 5 x m, K) 88 (2,11) mod (2 x 11 x m, K) 96 (2,3) mod (4 x 3 x m, K) 104 (2,13) mod (2 x 13 x m, K) 112 (2,7) mod (2 x 7 x m, K) 120 (2,3,5) mod (2 x 3 x 5 x m, K) 128 (2) mod (8 x m, K) 136 (2,17) mod (2 x 17 x m, K) 144 (2,3) mod (2 x 3 x m, K) 152 (2,19) mod (2 x 19 x m, K) 160 (2,5) mod (4 x 5 x m, K) 168 (2,3,7) mod (2 x 3 x 7 x m, K) 176 (2,11) mod (2 x 11 x m, K) 184 (2,23) mod (2 x 23 x m, K) 192 (2,3) mod (4 x 3 x m, K)  200 (2,5) mod (2 x 5 x m, K) 208 (2,13) mod (2 x 13 x m, K) 216 (2,3) mod (2 x 3 x m, K) 224 (2,7) mod (4 x 7 x m, K) 232 (2,29) mod (2 x 29 x m, K) 240 (2,3,5) mod (2 x 3 x 5 x m, K) 248 (2,31) mod (2 x 31 x m, K) 256 (2) mod (8 x m, K) 264 (2,3,11) mod (2 x 3 x 11 x m, K) 272 (2,17) mod (2 x 17 x m, K) 280 (2,5,7) mod (2 x 5 x 7 x m, K) 288 (2,3) mod (4 x 3 x m, K) 296 (2,37) mod (2 x 37 x m, K) 304 (2,19) mod (2 x 19 x m, K) 312 (2,3,13) mod (2 x 3 x 13 x m, K) 320 (2,5) mod (4 x 5 x m, K)  Interleaver Input Bits (K) f ₁ (the product of decimals except for (p ₁ , p ₂ ,…, p _n )) f ₂ (m = 1,2,3,…) Remarks 328 (2,41) mod (2 x 41 x m, K) 336 (2,3,7) mod (2 x 3 x 7 x m, K) 344 (2,43) mod (2 x 43 x m, K) 352 (2,11) mod (4 x 11 x m, K) 360 (2,3,5) mod (2 x 3 x 5 x m, K) 368 (2,23) mod (2 x 23 x m, K) 376 (2,47) mod (2 x 47 x m, K) 384 (2,3) mod (8 x 3 x m, K) 392 (2,7) mod (2 x 7 x m, K) 400 (2,5) mod (2 x 5 x m, K) 408 (2,3,17) mod (2 x 3 x 17 x m, K) 416 (2,13) mod (4 x 13 x m, K) 424 (2,53) mod (2 x 53 x m, K) 432 (2,3) mod (2 x 3 x m, K) 440 (2,5,11) mod (2 x 5 x 11 x m, K) 448 (2,7) mod (4 x 7 x m, K) 456 (2,3,19) mod (2 x 3 x 19 x m, K) 464 (2,29) mod (2 x 29 x m, K) 472 (2,59) mod (2 x 59 x m, K) 480 (2,3,5) mod (4 x 3 x 5 x m, K) 488 (2,61) mod (2 x 61 x m, K) 496 (2,31) mod (2 x 31 x m, K) 504 (2,3,7) mod (2 x 3 x 7 x m, K) 512 (2) mod (16 x m, K)  Interleaver Input Bits (K) f ₁ (the product of decimals except for (p ₁ , p ₂ ,…, p _n )) f ₂ (m = 1,2,3,…) Remarks 528 (2,3,11) mod (2 x 3 x 11 x m, K) 544 (2,17) mod (4 x 17 x m, K) 560 (2,5,7) mod (2 x 5 x 7 x m, K) 576 (2,3) mod (4 x 3 x m, K) 592 (2,37) mod (2 x 37 x m, K) 608 (2,19) mod (4 x 19 x m, K) 624 (2,3,13) mod (2 x 3 x 13 x m, K) 640 (2,5) mod (8 x 5 x m, K)  656 (2,41) mod (2 x 41 x m, K) 672 (2,3,7) mod (4 x 3 x 7 x m, K) 688 (2,43) mod (2 x 43 x m, K) 704 (2,11) mod (4 x 11 x m, K) 720 (2,3,5) mod (2 x 3 x 5 x m, K) 736 (2,23) mod (4 x 23 x m, K) 752 (2,47) mod (2 x 47 x m, K) 768 (2,3) mod (8 x 3 x m, K) 784 (2,7) mod (2 x 7 x m, K) 800 (2,5) mod (4 x 5 x m, K) 816 (2,3,17) mod (2 x 3 x 17 x m, K) 832 (2,13) mod (4 x 13 x m, K) 848 (2,53) mod (2 x 53 x m, K) 864 (2,3) mod (4 x 3 x m, K) 880 (2,5,11) mod (2 x 5 x 11 x m, K) 896 (2,7) mod (8 x 7 x m, K) 912 (2,3,19) mod (2 x 3 x 19 x m, K) 928 (2,29) mod (4 x 29 x m, K) 944 (2,59) mod (2 x 59 x m, K) 960 (2,3,5) mod (4 x 3 x 5 x m, K) 976 (2,61) mod (2 x 61 x m, K) 992 (2,31) mod (4 x 31 x m, K) 1008 (2,3,7) mod (2 x 3 x 7 x m, K) 1024 (2) mod (16 x m, K)  Interleaver Input Bits (K) f ₁ (the product of decimals except for (p ₁ , p ₂ ,…, p _n )) f ₂ (m = 1,2,3,…) Remarks 1056 (2,3,11) mod (4 x 3 x 11 x m, K) 1088 (2,17) mod (4 x 17 x m, K) 1120 (2,5,7) mod (4 x 5 x 7 x m, K) 1152 (2,3) mod (8 x 3 x m, K) 1184 (2,37) mod (4 x 37 x m, K) 1216 (2,19) mod (4 x 19 x m, K) 1248 (2,3,13) mod (4 x 3 x 13 x m, K) 1280 (2,5) mod (8 x 5 x m, K) 1312 (2,41) mod (4 x 41 x m, K) 1344 (2,3,7) mod (4 x 3 x 7 x m, K) 1376 (2,43) mod (4 x 43 x m, K) 1408 (2,11) mod (8 x 11 x m, K) 1440 (2,3,5) mod (4 x 3 x 5 x m, K) 1472 (2,23) mod (4 x 23 x m, K) 1504 (2,47) mod (4 x 47 x m, K) 1536 (2,3) mod (16 x 3 x m, K) 1568 (2,7) mod (4 x 7 x m, K) 1600 (2,5) mod (4 x 5 x m, K) 1632 (2,3,17) mod (4 x 3 x 17 x m, K) 1664 (2,13) mod (8 x 13 x m, K) 1696 (2,53) mod (4 x 53 x m, K) 1728 (2,3) mod (4 x 3 x m, K) 1760 (2,5,11) mod (4 x 5 x 11 x m, K) 1792 (2,7) mod (8 x 7 x m, K) 1824 (2,3,19) mod (4 x 3 x 19 x m, K) 1856 (2,29) mod (4 x 29 x m, K) 1888 (2,59) mod (4 x 59 x m, K) 1920 (2,3,5) mod (8 x 3 x 5 x m, K)  1952 (2,61) mod (4 x 61 x m, K) 1984 (2,31) mod (4 x 31 x m, K) 2016 (2,3,7) mod (4 x 3 x 7 x m, K) 2048 (2) mod (32 x m, K)  Interleaver Input Bits (K) f ₁ (the product of decimals except for (p ₁ , p ₂ ,…, p _n )) f ₂ (m = 1,2,3,…) Remarks 2112 (2,3,11) mod (4 x 3 x 11 x m, K) 2176 (2,17) mod (8 x 17 x m, K) 2240 (2,5,7) mod (4 x 5 x 7 x m, K) 2304 (2,3) mod (8 x 3 x m, K) 2368 (2,37) mod (4 x 37 x m, K) 2432 (2,19) mod (8 x 19 x m, K) 2496 (2,3,13) mod (4 x 3 x 13 x m, K) 2560 (2,5) mod (16 x 5 x m, K) 2624 (2,41) mod (4 x 41 x m, K) 2688 (2,3,7) mod (8 x 3 x 7 x m, K) 2752 (2,43) mod (4 x 43 x m, K) 2816 (2,11) mod (8 x 11 x m, K) 2880 (2,3,5) mod (4 x 3 x 5 x m, K) 2944 (2,23) mod (8 x 23 x m, K) 3008 (2,47) mod (4 x 47 x m, K) 3072 (2,3) mod (16 x 3 x m, K) 3136 (2,7) mod (4 x 7 x m, K) 3200 (2,5) mod (8 x 5 x m, K) 3264 (2,3,17) mod (4 x 3 x 17 x m, K) 3328 (2,13) mod (8 x 13 x m, K) 3392 (2,53) mod (4 x 53 x m, K) 3456 (2,3) mod (8 x 3 x m, K) 3520 (2,5,11) mod (4 x 5 x 11 x m, K) 3584 (2,7) mod (16 x 7 x m, K) 3648 (2,3,19) mod (4 x 3 x 19 x m, K) 3712 (2,29) mod (8 x 29 x m, K) 3776 (2,59) mod (4 x 59 x m, K) 3840 (2,3,5) mod (8 x 3 x 5 x m, K) 3904 (2,61) mod (4 x 61 x m, K) 3968 (2,31) mod (8 x 31 x m, K) 4032 (2,3,7) mod (4 x 3 x 7 x m, K) 4096 (2) mod (32 x m, K) 4160 (2,5,13) mod (4 x 5 x 13 x m, K) 4224 (2,3,11) mod (8 x 3 x 11 x m, K) 4288 (2,67) mod (4 x 67 x m, K) 4352 (2,17) mod (8 x 17 x m, K) 4416 (2,3,23) mod (4 x 3 x 23 x m, K) 4480 (2,5,7) mod (8 x 5 x 7 x m, K) 4544 (2,71) mod (4 x 71 x m, K) 4608 (2,3) mod (16 x 3 x m, K) 4672 (2,73) mod (4 x 73 x m, K) 4736 (2,37) mod (8 x 37 x m, K) 4800 (2,3,5) mod (4 x 3 x 5 x m, K) 4864 (2,19) mod (8 x 19 x m, K) 4928 (2,7,11) mod (4 x 7 x 11 x m, K) 4992 (2,3,13) mod (8 x 3 x 13 x m, K) 5056 (2,79) mod (4 x 79 x m, K) 5120 (2,5) mod (16 x 5 x m, K)  5184 (2,3) mod (4 x 9 x m, K) 5248 (2,41) mod (8 x 41 x m, K) 5312 (2,83) mod (4 x 83 x m, K) 5376 (2,3,7) mod (8 x 3 x 7 x m, K) 5440 (2,5,17) mod (4 x 5 x 17 x m, K) 5504 (2,43) mod (8 x 43 x m, K) 5568 (2,3,29) mod (4 x 3 x 29 x m, K) 5632 (2,11) mod (16 x 11 x m, K) 5696 (2,89) mod (4 x 89 x m, K) 5760 (2,3,5) mod (8 x 3 x 5 x m, K) 5824 (2,7,13) mod (4 x 7 x 13 x m, K) 5888 (2,23) mod (8 x 23 x m, K) 5952 (2,3,31) mod (4 x 3 x 31 x m, K) 6016 (2,47) mod (8 x 47 x m, K) 6080 (2,5,19) mod (4 x 5 x 19 x m, K) 6144 (2,3) mod (32 x 3 x m, K)

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. In addition, functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers in the art to which the present invention belongs.

So far, the present invention has been described with reference to preferred embodiments. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims.

Therefore, it will be understood by those skilled in the art that the present invention may be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

1 is a block diagram showing the configuration of a conventional turbo encoder to which the present invention is applicable.

2 is a block diagram schematically illustrating an apparatus for generating an address of an interleaver according to an exemplary embodiment of the present invention.

3 is a block diagram schematically illustrating an apparatus for generating an address of a deinterleaver according to an exemplary embodiment of the present invention.

4 is a flowchart illustrating an address generation method of an interleaver according to an embodiment of the present invention.

5 is a flowchart illustrating an address generation method of a deinterleaver according to an embodiment of the present invention.

Claims (19)

In the address generator of the interleaver for input data of a predetermined bit, An exponent determining unit for calculating a prime factor constituting the bit size and determining an index according to the number of each prime factor; A coefficient calculator which calculates coefficients of the address generation polynomial of the interleaver based on the prime factors and the exponent; And And an address generator for generating an address by the polynomial using the coefficients. The method of claim 1, The exponent determining unit determines that the exponent of 2 is 1 when 2 is included in the prime factors constituting the bit size and the number of 2 is 1 or more and 4 or less, And the coefficient of the second term of the polynomial calculated by the coefficient calculating unit based on the determined index of 2 has a multiple of 2. The method of claim 1, The exponent determining unit may include 2 in the prime factors constituting the bit size and the number of 2 is (2 xn + 1) or (2 xn + 2) (where n is an integer of 2 or more). Determine the exponent n, The coefficient of the second term of the polynomial calculated by the coefficient calculating unit based on the determined index of 2 has an ^integer multiple of 2 ⁿ . The method of claim 1, The exponent determination unit determines that the exponent of 3 is 1 when 3 is included in the prime factors constituting the bit size and the number of 3 is 1 or more and 3 or less, The coefficient of the second term of the polynomial calculated by the coefficient calculating unit based on the determined index of 3 has an integer multiple of 3. The address generator of the interleaver. The method of claim 1, The exponent deciding unit may determine the exponent of 3 when 3 is present in the prime factors constituting the bit size and the number of 3 is (2 x n) or (2 x n + 1) (where n is an integer of 2 or more). determined by n, And a coefficient of the second term of the polynomial calculated by the coefficient calculating unit based on the determined exponent of 3 has a multiple of 3 ⁿ . The method of claim 1, The exponent determining unit includes a prime factor p except 2 and 3 among the prime factors constituting the bit size, and the number of prime factors p is (2 xn-1) or (2 xn) (where , n is an integer of 1 or more), and the index of p is determined as n, And the coefficient of the second term of the polynomial calculated by the coefficient calculating unit based on the determined index of p has a multiple of p ⁿ . An apparatus for generating an address of a deinterleaver for interleaved data of a predetermined bit, A coefficient calculator for calculating a coefficient of the address generation polynomial of the deinterleaver based on the coefficient of the address generation polynomial of the interleaving data; And And an address generator for generating an address of the deinterleaver by using the coefficient generation polynomial of the deinterleaver. And a coefficient of the address generation polynomial of the interleaving data is calculated based on a prime factor constituting the bit size and an exponent according to the number of the prime factors. The method of claim 7, wherein the coefficient calculating unit, When the number of two constituents constituting the bit size includes 2 and the number of 2 is one or more than four, the address of the deinterleaver based on the coefficient of the second term of the polynomial of the address generation of the interleaving data having a multiple of two. An apparatus for generating an address of a deinterleaver, comprising calculating coefficients of a generated polynomial. The method of claim 7, wherein the coefficient calculating unit, If the prime number constituting the bit size includes 2, and the number of 2 is (2 xn + 1) or (2 xn + 2) (where n is an integer of 2 or more), it has a multiple of 2 ⁿ . And calculating a coefficient of an address generation polynomial of the deinterleaver based on coefficients of a secondary term of the address generation polynomial of the interleaving data. In the address generation method of the interleaver for input data of a predetermined bit, Calculating a prime factor constituting the size of the bit; Determining an index according to the number of each of the prime factors; Calculating coefficients of the address generation polynomial of the interleaver based on the prime factors and exponents; And Generating an address by the polynomial using the coefficients. The method of claim 10, The step of determining the exponent includes determining the exponent of 2 as 1 when 2 is included in the prime factors constituting the bit size and the number of 2 is 1 or more and 4 or less, And the coefficient of the second term of the polynomial calculated by the prime factor 2 has a multiple of two. The method of claim 10, The step of determining the exponent may include two of the prime factors constituting the bit size, and if the number of two is (2 x n + 1) or (2 x n + 2), where n is an integer of 2 or more, Determining an index of 2 as n; The coefficient of the second term of the polynomial calculated by the prime factor 2 has a multiple of 2 ⁿ . The method of claim 10, The determining of the exponent includes: determining the exponent of 3 as 1 when 3 is included in the prime factors constituting the bit size and the number of 3 is 1 or more and 3 or less. And the coefficient of the second term of the polynomial calculated by the prime factor 3 has a multiple of three. The method of claim 10, The step of determining the exponent may include three of the prime factors constituting the bit size, and if the number of three is (2 x n) or (2 x n + 1) (where n is an integer of 2 or more), Determining an index as n; And a coefficient of the second term of the polynomial calculated by the prime factor 3 has a multiple of 3 ⁿ . The method of claim 10, In the step of determining the exponent, if a prime factor excluding 2 and 3 is included in the prime factors constituting the bit size, and the number of prime factors p is (2 xn-1) or (2 xn) ( Wherein n is an integer of 1 or more), and determining the index of p as n; And a coefficient of the second term of the polynomial calculated by the prime factor 3 has a multiple of p ⁿ . In the method of generating a deinterleaver address for a predetermined bit of interleaving data, Calculating coefficients of the address generation polynomial of the deinterleaver based on coefficients of the address generation polynomial of the interleaving data; And Generating the address of the deinterleaver by using the coefficient generation polynomial of the deinterleaver using the coefficients; And a coefficient of the address generation polynomial of the interleaving data is calculated based on a prime factor constituting the bit size and an index according to the number of the prime factors. The method of claim 16, wherein the coefficient calculation step, When the number of two constituents constituting the bit size includes 2 and the number of 2 is one or more than four, the address of the deinterleaver based on the coefficient of the second term of the polynomial of the address generation of the interleaving data having a multiple of two. Computing coefficients of the generated polynomial; address generation method of a deinterleaver. The method of claim 16, wherein the coefficient calculation step, If the prime number constituting the bit size includes 2, and the number of 2 is (2 xn + 1) or (2 xn + 2) (where n is an integer of 2 or more), it has a multiple of 2 ⁿ . And calculating coefficients of the address generation polynomial of the deinterleaver based on coefficients of the second term of the address generation polynomial of the interleaving data. A computer-readable recording medium having recorded thereon a program for executing the method according to any one of claims 10 to 18.

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