KR20080097126A - Multi-level phase change memory device with improved read performance - Google Patents

Abstract

A reading method of multi-level phase change memory device is provided to supply a recovery current to the selected memory cell before the sensing operation is performed, so the distribution of the memory cells having the amorphous state is recovered. A reading method of the multi-level phase change memory device including the memory cells having one among a plurality of data states is comprised of steps: recovering the selected memory cells so that each resistance of the memory cell is recovered to initial resistance regardless of a plurality of data states respectively(241a); sensing data from the selected memory cells(241b). The selected memory cells are recovered so that each initial resistance of a plurality of data state values is not changed.

Description

MULTI-LEVEL PHASE CHANGE MEMORY DEVICE WITH IMPROVED READ PERFORMANCE}

1 is a diagram illustrating a cell structure of a general phase change memory device.

2 is a diagram illustrating a temperature profile of a memory cell during a write operation of a general phase change memory device.

3 is a view showing a change in the resistance value of the resistance element over time.

4 is a diagram illustrating distributions of a multi-level phase change memory device.

5 is a block diagram illustrating a multi-level phase change memory device according to exemplary embodiments of the present invention.

FIG. 6 is a circuit diagram illustrating the sense amplifier circuit of FIG. 5.

FIG. 7 is a block diagram schematically illustrating a clamp voltage generation circuit as part of the control logic shown in FIG. 5.

8 is a timing diagram illustrating a read operation of a multi-level phase change memory device according to the present invention.

9 is a circuit diagram illustrating a write driver circuit of a multi-level phase change memory device according to another exemplary embodiment of the present invention.

10 is a timing diagram illustrating a read operation of a multi-level phase change memory device according to another exemplary embodiment of the present invention.

FIG. 11 illustrates a flow of recovery current and sense current during a read operation of a multi-level phase change memory device according to another exemplary embodiment of the present invention.

12 is a block diagram illustrating a system including a multi-level phase change memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

210: PRAM cell array 220: row selection circuit

230: column selection circuit 240: control logic

250: high voltage generation circuit 260: sense amplification circuit

270: input / output buffer circuit 280: write driver circuit

290: bias voltage generation circuit

The present invention relates to a semiconductor memory device, and more particularly, to a multi-level phase change memory device and a reading method thereof.

There are many computer memory technologies currently used to store computer programs and data, which include dynamic random access memory (DRAM), static random access memory (SRAM), erasable and programmable read-only memory (EPROM), and Miraculously erased and programmable read-only memory (EEPROM), and the like. Some memory technologies require a voltage to hold stored data, while others do not require a voltage to hold stored data.

There is an increasing demand for repetitive read / write and nonvolatile memory. The primary nonvolatile memory currently in use is flash memory, which uses a floating gate transistor that retains charge on an isolated floating gate. Each memory cell can be electrically programmed to "1" or "0" by injecting / removing electrons to / from the floating gate. However, memory cells are more difficult to shrink to smaller sizes, are relatively slow to perform read and program operations, and can consume a relatively large amount of power.

As nonvolatile memory, phase change memory devices have also been known recently. These devices use materials that can be electrically switched between different structured states exhibiting different electrical readout characteristics. For example, memory devices made of a chalcogenide material (hereinafter referred to as "GST material") as a germanium-antimony-tellurium mixture (GST) are known, and the GST material has a relatively high resistivity. It is programmed between the representative amorphous state and the crystalline state exhibiting a relatively low resistivity. The GST material is programmed by heating the GST material. The size and duration of the heating determine whether the GST material remains in an amorphous or crystalline state. High and low resistivities represent programmed values "1" and "0", which can be detected by measuring the resistivity of the GST material.

In a typical phase change memory device, a memory cell is composed of a resistance element and a switching element. The switching device may be implemented using various devices such as MOS transistors, diodes, and the like. As shown in FIG. 1, the resistance element includes a phase change film 1 made of a GST material, an upper electrode 2 formed on the phase change film 1, and a lower electrode formed under the phase change film 1. It includes (3). When a pulse current is applied to the memory cell, the applied pulse current flows through the lower electrode 3. When a very short pulse current of about several tens to several tens of microseconds is applied to the memory cell, only the adjacent phase change film of the lower electrode 3 is heated with Joule heat. At this time, a part of the phase change film 1 (hatched in FIG. 1) becomes a crystalline state (or “SET state”) or an amorphous state (or “RESET state”) by the difference of the heating profile. Called "". For example, in order to make the phase change film 1 into an amorphous state (or a RESET state), as shown in FIG. 2, a pulse current i1 is applied to the memory cell for a short time, and applied within 1 μs. The pulse current is removed. In order to make the phase change film 1 into the crystalline state (or the SET state), as shown in FIG. 2, a pulse current i2 less than i1 is quantitatively applied to the memory cell, and the applied pulse current is phased. The change film 1 is maintained for 30 ms to 50 ms to be crystallized and then removed. Thus, the PRAM memory cell is set to either the crystalline state or the amorphous state in the manner described above.

The resistivity of the resistive element of the memory cell having an amorphous state will increase due to various causes. For example, the resistivity (or resistance value) of the resistive element will increase over time due to various causes. The resistance value of the resistive element having an amorphous state will increase more as the initial resistance value of the resistive element is higher. More specifically, it is as follows.

Referring to FIG. 3 showing a change in the resistance value of the resistive element over time, the horizontal axis represents the initial resistance value Rini of the memory cell when the memory cell is programmed to an amorphous state, and the vertical axis represents the progress of time over time. The changed resistance value Ro of the initial resistance value is shown. Ideally, the initial resistance value Rini will coincide with the changed resistance value Ro, as shown by the solid line marked " 10 ". However, the initial resistance value Rini will gradually change to a higher resistance value as time passes (or after a certain time). As can be seen in Figure 3, the higher the initial resistance value (Rini), the greater the change in resistance value will be. Therefore, as the initial resistance value of the resistive element having the amorphous state is increased, the threshold voltage of the memory cell will increase.

A paper on the change in resistance value was published on May 5, 2004 in IEEE TRANSACTIONS ON ELECTRON DEVICES (VOL. 51, NO.5) entitled "LOW-FIELD AMORPHOUS STATE RESISTANCE AND THRESHOLD VOLTAGE DRIFT IN CHALCOGENIDE MATERIALS." have.

Multi-level techniques, well known in the art, will be applied to phase change memory devices to increase memory capacity. Such memory devices are hereinafter referred to as multi-level phase change memory devices. The aforementioned change in the initial resistance value is a limiting factor in implementing a multi-level phase change memory device, which will be described in detail below.

For convenience of explanation, assume that 2-bit data is stored in one memory cell. For example, as shown in FIG. 4, the 2-bit data will have one of four possible states "11", "10", "01", and "00". In FIG. 3, the distribution 101 corresponding to the " ST0 " state will include memory cells having a decision state. In FIG. 4, the distributions 102, 103, 104 corresponding to the remaining states ST1, ST2, ST3 will include memory cells having amorphous states. The resistance values of the memory cells included in the distribution 102 corresponding to the "ST1" state may be smaller than the resistance values of the memory cells included in the distribution 103 corresponding to the "ST2" state. The resistance values of the memory cells included in the distribution 103 corresponding to the "ST2" state may be smaller than the resistance values of the memory cells included in the distribution 104 corresponding to the "ST3" state. Distributions 101, 102, 103, and 104 indicated by solid lines in FIG. 4 are curves obtained after programming memory cells, and distributions 101 ', 102', 103 'and 104' indicated by dotted lines are defined after the program. These curves are obtained after elapse of time. Such a change in distribution / threshold voltage / resistance value means difficulty in determining which state the memory cell has. In other words, this distribution / threshold voltage / resistance change causes the read margin to be reduced. In the worst case, such a distribution / threshold voltage / resistance change will cause a read error. This problem will become more serious as the number of data bits stored in the memory cell increases.

Therefore, there is an urgent need for a multi-level phase change memory device capable of stably performing a read operation regardless of distribution change, threshold voltage change, or resistance value change.

It is an object of the present invention to provide a multi-level phase change memory device having improved read performance and a read method thereof.

Exemplary embodiments of the present invention provide a method of reading a multi-level phase change memory device each including memory cells having one of a plurality of data states, wherein a resistance value of each of the selected memory cells is selected from among the memory cells. Recovering the selected memory cells to return to an initial resistance value of each of the plurality of data states irrespective of the plurality of data states; And sensing data from the selected memory cells.

Other exemplary embodiments of the present invention provide a method of reading a multi-level phase change memory device, each memory cell having one of a plurality of data states, wherein the read method comprises selected memory cells of the memory cells. Supplying a recovery current to the furnace; And sensing data from the selected memory cells by supplying a sensing current to the selected memory cells, wherein the recovery current is quantitatively greater than the sensing current.

Still other exemplary embodiments of the present invention provide a method of reading a multi-level phase change memory device each including memory cells having one of a plurality of data states, the read method comprising bits coupled to selected memory cells. Activating a word line coupled to the selected memory cells while precharging lines to a precharge voltage; Supplying a recovery current to selected ones of the memory cells; After supplying the recovery current, supplying a sensing current to the selected memory cells to sense data from the selected memory cells, wherein the recovery current is quantitatively greater than the sensing current.

Still other exemplary embodiments of the present invention provide a method of reading a multi-level phase change memory device each including memory cells having one of a plurality of data states, the read method comprising bits coupled to selected memory cells. Precharging the lines to a precharge voltage; Activating a word line coupled to the selected memory cells; Supplying a recovery current to selected ones of the memory cells; After supplying the recovery current, supplying a sensing current to the selected memory cells to sense data from the selected memory cells, wherein the recovery current is quantitatively greater than the sensing current.

Still other exemplary embodiments of the present invention include a memory cell array having memory cells arranged in word lines and bit lines; Each of the memory cells has one of a plurality of data states corresponding to multi-level data; Sense amplifier circuitry configured to sense data from selected memory cells of the memory cell array; A write driver circuit configured to supply a write current to selected memory cells of the memory cell array in accordance with data input during a write operation; And a control logic for controlling one of the sense amplifying circuit and the write driver circuit to supply a recovery current to the selected memory cells before a sensing period of a read operation.

Still other exemplary embodiments of the present invention include a memory cell array having memory cells arranged in word lines and bit lines; Each of the memory cells has one of a plurality of data states corresponding to multi-level data; Sense amplifier circuitry configured to sense data from selected memory cells of the memory cell array; And a control logic for controlling the sense amplifier circuit to supply a recovery current to the selected memory cells before a sensing period of a read operation.

Still other exemplary embodiments of the present invention include a memory cell array having memory cells arranged in word lines and bit lines; Each of the memory cells has one of a plurality of data states corresponding to multi-level data; Sense amplifier circuitry configured to sense data from selected memory cells of the memory cell array; A write driver circuit configured to supply a write current to selected memory cells of the memory cell array in accordance with data input during a write operation; And a control logic for controlling the write driver circuit to supply a recovery current to the selected memory cells before a sensing period of a read operation.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided.

Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, the same reference numerals are used in the description and the drawings to refer to the same or similar parts.

In the following, a multi-level phase change memory device is used as an example for explaining the features and functions of the present invention. However, one of ordinary skill in the art will readily appreciate the other advantages and performances of the present invention in accordance with the teachings herein. The present invention may be implemented or applied through other embodiments as well. In addition, the detailed description may be modified or changed according to aspects and applications without departing from the scope, technical spirit and other objects of the present invention.

5 is a block diagram illustrating a multi-level phase change memory device according to exemplary embodiments of the present invention.

Referring to FIG. 5, the phase change memory device 200 according to the present invention includes a memory cell array 210 that stores N-bit data information (N is an integer of 2 or greater). Although not shown in FIG. 210, a plurality of memory cells will be arranged in rows (or word lines) and columns (or bit lines). Each memory cell will consist of a switching element and a resistive element. The switching device may be implemented using various devices such as MOS transistors, diodes, and the like. The resistive element will be configured to include a phase change film made of the GST material described above. Each memory cell is an overwritable memory cell. Exemplary resistive elements are described in U.S. Pat. AND METHODS OF DRIVING THE SAME, and US Patent No. 6982913, entitled "DATA READ CIRCUIT FOR USE IN A SEMICONDUCTOR MEMORY AND A MEMORY THEREOF," each of which is hereby incorporated by reference.

5, the row select circuit 220 selects at least one of the rows (or word lines) in response to the row address RA, and the column select circuit 230 selects the column address CA. Select some of the columns (or bit lines). The control logic 240 may be configured to control overall operations of the multi-level phase change memory device 200 in response to a read / write command from the outside. The high voltage generator circuit 250 is controlled by the control logic 240 to generate the high voltage used in the row and column select circuits 220, 230, the sense amplifier circuit 260, and the write driver circuit 280. It is composed. For example, the high voltage generation circuit 250 may be implemented using a charge pump. However, it is apparent to those skilled in the art that the implementation of the high voltage generator circuit 250 is not limited to that disclosed herein.

The sense amplifier circuit 260 is controlled by the control logic 240, and senses cell data through columns (or bit lines) selected by the column select circuit 230 in a read operation. The sensed data will be output to the outside through the data input / output buffer circuit 270. The sense amplifier circuit 260 is connected to the data bus DL and will supply the sense current I_SENSE to the data bus DL during a read operation. The write driver circuit 280 is controlled by the control logic 240 and supplies the write current to the data line DL according to the data provided through the input / output buffer circuit 270. The bias voltage generation circuit 290 is controlled by the control logic 240 and may be configured to generate bias voltages to be supplied to the sense amplifier circuit 260 and the write driver circuit 280.

According to the multi-level phase-change memory device of the present invention, in particular, the control logic 240 may change the threshold voltage change / distribution change / resistance change of the decision and amorphous states 101, 102, 103, 104 (see FIG. 3). Control the sense amplifier circuit 260 or / and the write driver circuit 280 to supply a recovery current (quantitatively greater than the sense current) to the memory cells selected prior to the sense operation to prevent read errors due to something to do. This will be explained in detail later. In an exemplary embodiment, the amount of recovery current will be determined such that the initial resistance value of each of the plurality of data states does not change after the supply of recovery current. By supplying the recovery current to the selected memory cells, the resistance value of the resistive element of each of the selected memory cells will be restored to the initial resistance value (ie, the resistance value determined when programmed or representing the resistance value before being changed). This characteristic (recovery to initial resistance value) is described in detail in the aforementioned paper, and a description thereof will therefore be omitted. This operation is hereinafter referred to as "recovery operation". After the recovery operation, it is possible to accurately sense multi-level data from the selected memory cells by supplying a sense current to the selected memory cells.

FIG. 6 is a circuit diagram illustrating the sense amplifier circuit of FIG. 5. Although a sense amplification circuit corresponding to one bit line is shown in FIG. 6, it is apparent to those skilled in the art that more sense amplification circuits corresponding to a bit organization are further provided. For example, if the bit structure is x8, eight sense amplifier circuits would be required. If the bit structure is x16, 16 sense amplifier circuits will be required. However, it is apparent that the number of sense amplifier circuits is not limited to the bit structure.

Referring to FIG. 6, the sense amplifier circuit 260 according to the present invention includes PMOS transistors 261, 262, and 265, NMOS transistors 263, 266, and 267, and a sense amplifier 264. The PMOS transistors 261 and 262 are connected in series between the power supply terminal 268 and the signal line NSA (or an input terminal of the sense amplifier), and the power supply terminal 268 has a power supply voltage VCC or higher voltage ( V _SA ) may be applied. Here, the V _SA voltage may be higher than the power supply voltage by the threshold voltage of the diode. However, it is apparent to those skilled in the art that the V _SA voltage is not limited to that disclosed herein. The PMOS transistor 261 is turned on / off by the control signal nPBAIS indicating the sensing period, and the PMOS transistor 262 is turned on by the bias voltage VBIASi (i = 1 to 3) (see FIG. 3). On / off The control signal nPBAIS may be provided from the control logic 240 of FIG. 5, and the bias voltage VBIASi may be provided from the bias voltage generation circuit 290 of FIG. 5.

The NMOS transistor 263 is connected between the signal line NSA and the column select circuit 230 (or the data line DL) and limits the voltage of the bit line BL or the current to the bit line BL. Controlled by the clamp voltage VCLP. The clamp voltage VCLP is used to maintain the voltage of the bit line below the threshold voltage at which the reset state of the phase change film changes and to supply the recovery current (quantitatively greater than the sense current) to the bit line during the recovery period. . Sense amplifier 264 (denoted "AMP" in the figure) detects whether the voltage on the bit line is lower or higher than the reference voltage VREF via column select circuit 230, and detects the detected result. The data is output to the data input / output buffer circuit 270 as data.

Here, the sense amplifier 264 may be configured to sense one of two data bits stored in the memory cell. Alternatively, the sense amplifier 264 may be configured to sense both data bits stored in the memory cell. However, it will be apparent to those skilled in the art that the structure of the sense amplifier 264 may be variously modified according to multi-level read schemes.

The PMOS transistor 265 is connected between the precharge voltage V _PRE and the signal line NSA and will be controlled by the control signal nPRE from the control logic 240 of FIG. 5. The NMOS transistor 266 is connected between the input (or data line DL) of the column select circuit 230 and the ground voltage and will be controlled by the control signal PDIS from the control logic 240 of FIG. 5. . The NMOS transistor 267 is connected between the signal line NSA and the ground voltage and will be controlled by the control signal PDIS. The PMOS transistors 261 and 262 provide a sense current for supplying a positive current (or sense current I_SENSE) determined by the bias voltage VBIASi to the signal line NSA, that is, the bit line BL, during the sensing period. The supply unit will be configured. The sense current I_SENSE will be supplied to the memory cell through the bit line during the sense period. The PMOS transistor 265 may configure a precharge current supply unit supplying a precharge current to the signal line NSA during the precharge period. The clamp voltage VCLP applied to the NMOS transistor 263 will have first and second clamp voltages to supply precharge current and recovery current to the bit line prior to the sensing operation. The first clamp voltage will be lower than the second clamp voltage and higher than the ground voltage. This will be explained in detail later.

FIG. 7 is a block diagram schematically illustrating a clamp voltage generation circuit as part of the control logic shown in FIG. 5.

Referring to FIG. 7, the clamp voltage generator circuit 241 may include a pulse generator 241a and a level shifter 241b. The pulse generator 241a may be configured to generate a pulse signal in response to the enable information of the word line. In an exemplary embodiment, the pulse signal has a duration of about 10 Hz to 10 Hz (Vth-0.3 to Vth + 0.1) (Vth represents the threshold voltage of a multi-level cell having a "11" state). Will be set to have The level shifter 241b operates in response to the output of the pulse generator 241a and is supplied with the first clamp voltage V1 and the second clamp voltage V2. The level shifter 241b outputs the clamp voltage VCLP having the first clamp voltage V1 when the output of the pulse generator 241a has a low level, and the level shifter 241b outputs the pulse generator 241a. When it has this high level it will output the clamp voltage VCLP with the second clamp voltage V2. The clamp voltage VCLP will be applied to the gate of the NMOS transistor 263 of the sense amplifier circuit 260 mentioned above.

8 is a timing diagram illustrating a read operation of a multi-level phase change memory device according to the present invention. A read operation of the multi-level phase change memory device according to the present invention will be described in detail below with reference to the drawings.

Before describing the read operation, when 2-bit data is stored in one memory cell, the read operation may be performed through various read methods. For example, as is well known in the art, one of two data bits (eg, LSB data bits or MSB data bits) will be sensed by the sense amplifier circuit 260. To this end, the sensing operation to be described later will be performed once or more depending on the coding scheme of the four possible states 11, 10, 01, 00. The recovery operation will be performed once before the first sensing operation regardless of the number of sensing operations. In contrast, it is apparent to those skilled in the art that recovery operations may be performed each time prior to sensing operations. For convenience of description, the read operation of the multi-level phase change memory device will be described through one recovery operation and one detection operation. However, the manner in which the recovery operation is applied will vary depending on the manner of reading the multi-level data.

As shown in FIG. 8, the read operation of the multi-level phase change memory device according to the present invention will largely include a precharge period and a detection period. Before the bit line / signal line BL / NSA is precharged, that is, before the precharge period, the control signals PDIS and nPBIAS have a high level and the control signal nPRE has a low level. At this time, the clamp voltage VCLP has a first clamp voltage V1 (for example, 2.2V). Under these conditions, transistors 261, 262, 265 of sense amplifier circuit 260 will be turned off, while transistors 263, 266, 267 of sense amplifier circuit 260 will be turned on. This means that the data line DL and the signal line NSA are discharged to the ground voltage.

During the precharge period, the selected bit line BL, the data line DL, and the signal line NSA will be precharged with the precharge voltage V _PRE . Specifically, during the precharge period, the control signals nPRE and PDIS have a low level, while the control signal nPBIAS has a high level. At this time, as the column select signal YA is activated high, the bit line BL may be electrically connected to the data line DL. According to this condition, in the state where the first clamp voltage V1 (for example, 2.2 V) is applied as the clamp voltage VCLP to the gate of the NMOS transistor 263, the signal line NSA and the bit line BL are applied. ) Will be charged to the precharge voltage (V _PRE ) supplied through the PMOS transistor 265. Here, the precharge voltage V _PRE may be equal to the reference voltage VREF applied to the sense amplifier 264.

As shown in FIG. 8, the word line WL may be activated in the precharge period. Next, the second clamp voltage V2 (eg, 3V) as the clamp voltage VCLP will be supplied to the gate of the NMOS transistor 263. In other words, as shown in FIG. 8, the clamp voltage VCLP will be increased from the first clamp voltage V1 to the second clamp voltage V2. As the second clamp voltage V2 (e.g., 3V) is supplied to the gate of the NMOS transistor 263, a greater amount of recovery current than the precharge current is passed through the NMOS transistor 263 for a given time. The line BL will be supplied to the memory cell. When a recovery current is applied to the memory cell, as mentioned above, the resistance value of the resistance element of the memory cell will return to the initial resistance value.

After the clamp voltage VCLP is lowered from the second clamp voltage V2 to the first clamp voltage V1, as shown in FIG. 8, the control signal nPRE transitions from the low level to the high level, and the control signal. (nPBIAS) transitions from high level to low level. In this case, an appropriate bias voltage VBIASi will be supplied to the PMOS transistor 262. According to this condition, the sense current flowing through the PMOS transistors 261 and 262 will be supplied to the bit line BL through the NMOS transistor 263 and the column select circuit 230. In this case, as shown in FIG. 8, the voltage of the bit line BL / signal line NSA may be changed to be above or below the reference voltage VREF according to the state of the memory cell. The change in voltage of the signal line NSA will be sensed through the sense amplifier 264. The sensed data SAOUT will be output to the input / output buffer circuit 270. The sensing operation will then end.

9 is a circuit diagram illustrating a write driver circuit of a multi-level phase change memory device according to another exemplary embodiment of the present invention. The multi-level phase change memory device according to another embodiment of the present invention is substantially the same as that shown in Fig. 5 except that the recovery current is supplied to the selected memory cell through the write driver circuit instead of the sense amplifier circuit. The description will therefore be omitted. That is, in the case of the multi-level phase change memory device shown in Fig. 5, the write driver circuit 280 will not operate during the read operation. In contrast, the write driver circuit 280 ′ shown in FIG. 8 will supply the recovery current to the selected bit line under control of the control logic 240 before the sensing operation is performed. This will be explained in detail later.

Referring to Fig. 9, the write driver circuit 280 'includes a driver controller 281, a selector 282, a PMOS transistor 283 acting as a pull-up driver, an NMOS transistor 284 acting as a pull-down driver, and an NMOS. Will include a transistor 285. The driver controller 281 is U.S. It is described in detail in Patent No. 7,012,834, and a description thereof will therefore be omitted. In particular, in the case of the present invention, during the read operation, the pull-up driver 283 may be controlled by the drive signal transmitted through the selector 282, not by the drive signal output from the driver controller 281. . The selector 282 may selectively output the control signal nRCV to the pull-up and pull-down drivers 283 and 284 according to the operation mode. For example, the selector 282 may output the control signal nRCV during a read operation, and the control signal nRCV may be output to the pull-up and pull-down drivers 283 and 284 through the NMOS transistor 285. The NMOS transistor 285 will be controlled by the operation mode signal RM. Here, the control signal nRCV is a flag signal indicating a recovery operation, and may be provided from the control logic 240 of FIG. 5.

With continued reference to FIG. 9, the selector 282 may include a driver 282a and a switch 282b. The switch 282b will connect the output of the driver 282a to the gates of the pull-up and pull-down transistors 283 and 284 in response to an operation mode signal RM indicating the operation mode. Here, the switch 282b may be switched on when the operation mode signal RM indicates a read operation and switched off when the operation mode signal RM indicates a write operation. Driver 282a will drive pull-up and pull-down transistors 283 and 284 through switch 282b in response to control signal nRCV. For example, when the control signal nRCV has a low level, the pull up transistor 283 will be turned off and the pull down transistor 284 will be turned on. In contrast, when the control signal nRCV has a high level, the pull-up transistor 283 will be turned on and the pull-down transistor 284 will be turned off. Here, the pull-up / pull-down driving capability of the driver 282a will be set larger than that of the PMOS transistor TR7 and the inverter INV1 of the driver controller 281.

Here, the control signal nRCV has a duration of about 10 Hz to 10 Hz and has a magnitude (Vth-0.3 to Vth + 0.1) (Vth represents a threshold voltage of a multi-level cell having a "11" state). Will be set.

Although not shown in the drawings, it is to be understood by those skilled in the art that the write driver circuit 280 'can be configured to connect to the data line only during a read operation (especially during the supply of recovery current). Self-explanatory For example, this may be achieved by providing a switch between the output of the write driver circuit 280 'and the data line and turning the switch on in the write period and the supply of recovery current. However, it is apparent to those skilled in the art that the electrical connection between the data line and the write driver circuit is not limited to that disclosed herein.

10 is a timing diagram illustrating a read operation of a multi-level phase change memory device according to another embodiment of the present invention, and FIG. 11 is a read of the multi-level phase change memory device according to another embodiment of the present invention. A diagram showing the flow of recovery current and sense current during operation. A read operation of the multi-level phase change memory device according to the present invention will be described in detail below with reference to the drawings. The precharge and sensing operations are substantially the same as described above, and a description thereof will therefore be omitted.

As can be seen in FIG. 10, after the control signal nPRE transitions from the low level to the high level, that is, after the precharge operation is completed, the word line WL is activated and the control signal nRCV is at the high level. Will transition to the low level. This means that the control signal nRCV is applied to the pull-up driver 283 through the selector 282 of the write driver circuit 280 '. That is, the recovery current will be supplied to the selected bit line BL through the pull-up driver 283. As the recovery current is supplied to the selected bit line BL through the pull-up driver 283, the resistance value of the resistance element will be restored to the initial resistance value. After the recovery current is supplied to the selected bit line for a given time, the control signal nRCV will transition from low level to high level. This will cause the pullup driver 283 to turn off. Thereafter, a sensing operation on the selected memory cell will be performed. The sensing operation is substantially the same as described above, and a description thereof will therefore be omitted.

In conclusion, as shown in FIG. 11, a recovery current (see an arrow denoted by 1) is supplied to the selected bit line through the write driver circuit 280 ′, and sensed by the selected bit line through the sense amplifier circuit 260. The current (see arrow marked with ②) will be supplied.

Multi-level phase change memory devices are nonvolatile memory devices capable of retaining stored data even when power is cut off. Phase change memory devices support random data access and provide fast data reading and processing. This means that phase-change memory devices are ideal for code storage. With the increasing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, phase change memory devices are becoming more widely used as data storage as well as code storage. Phase change memory devices are also used in home applications such as HDTV, DVD, routers, and GPS. A system including a multi-level phase change memory device according to the present invention is schematically illustrated in FIG. System 1000 according to the present invention, such as a computing system, a mobile device, etc. may include a modem 1300, such as a microprocessor 1100, a user interface 1200, a baseband chipset, electrically connected to a bus 1001. And a phase change memory device 1400 (denoted as " PRAM " in the drawing), wherein the phase change memory device 1400 is implemented with the same multi-level phase change memory device as described in FIGS. Will be. The multi-level phase change memory device 1400 will store N-bit data (N is an integer of 2 or greater) processed / to be processed by the microprocessor 1100. When the system 1000 according to the present invention is a mobile device, a battery 1500 for supplying an operating voltage of the system 1000 will be additionally provided. Although not shown in the drawings, the system 1000 according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, a NAND flash memory device, and the like. Is evident to those who have acquired common knowledge in this field.

In an exemplary embodiment of the invention, the chalcogenide material will consist of Te, Se, S, mixtures thereof, or alloys thereof. Alternatively, the chalcogenide material will consist of a material obtained by adding impurities (eg, Bi, Sr, Si, C, N, O, etc.) to Te, Se, S, mixtures thereof, or alloys thereof. . Alternatively, the chalcogenide material may be made of any one selected from Ge, Sb, Sn, As, Si, Pb, Te, Se, S, mixtures thereof, and alloys thereof. Alternatively, the chalcogenide material may include impurities (eg, Bi, Sr, Si, C, N, Ge, Sb, Sn, As, Si, Pb, Te, Se, S, mixtures thereof, or alloys thereof). O, etc.).

It will be apparent to those skilled in the art that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is believed that the present invention includes modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

As described above, the distribution of memory cells having an amorphous state is restored by supplying a recovery current to the selected memory cell before the sensing operation is performed, and as a result, it is possible to secure a read margin. Thus, it is possible to prevent read errors due to resistance changes.

Claims (47)

A method of reading a multi-level phase change memory device, each memory cell including one of a plurality of data states: Recovering the selected memory cells such that a resistance value of each of the selected memory cells of the memory cells is restored to an initial resistance value of each of the plurality of data states regardless of the plurality of data states; And, And detecting data from the selected memory cells. The method of claim 1, And wherein the selected memory cells are recovered such that an initial resistance value of each of the plurality of data states is not changed. The method of claim 1, And precharging the bit lines connected to the selected memory cells with a precharge voltage. The method of claim 3, wherein And wherein said selected memory cells are recovered during said precharge step. The method of claim 3, wherein And wherein the selected memory cells are recovered after the bit lines are precharged and before data is sensed from the selected memory cells. The method of claim 1, Wherein each of the memory cells stores N-bit data (N is an integer of 2 or greater). The method of claim 1, Wherein said recovery and sensing operations for said selected memory cells are performed by a sense amplifier circuit. The method of claim 1, And wherein said recovery operation on said selected memory cells is performed by a write driver circuit and said sensing operation on said selected memory cells is performed by a sense amplifier circuit. A method of reading a multi-level phase change memory device, each memory cell including one of a plurality of data states: Supplying a recovery current to selected ones of the memory cells; And, And supplying a sense current to the selected memory cells to sense data from the selected memory cells, wherein the recovery current is quantitatively greater than the sense current. The method of claim 9, When the recovery current is supplied to the selected memory cells, a resistance value of each of the selected memory cells is restored to an initial resistance value of each of the plurality of data states regardless of the plurality of data states. Way. The method of claim 9, And the amount of recovery current is determined such that an initial resistance value of each of the plurality of data states does not change after the supply of the recovery current. The method of claim 9, And precharging the bit lines connected to the selected memory cells with a precharge voltage. The method of claim 12, The recovery current is supplied to the selected memory cells during the precharge step. The method of claim 12, The recovery current is supplied to the selected memory cells after the bit lines are precharged and before data is sensed from the selected memory cells. The method of claim 9, Wherein each of the memory cells stores N-bit data (N is an integer of 2 or greater). The method of claim 9, The recovery current and the sense current are supplied from a sense amplifier circuit. The method of claim 9, The recovery current is supplied from a write driver circuit, and the sense current is supplied from a sense amplifier circuit. A method of reading a multi-level phase change memory device, each memory cell including one of a plurality of data states: Activating a word line coupled to the selected memory cells while precharging the bit lines coupled to the selected memory cells with a precharge voltage; Supplying a recovery current to selected ones of the memory cells; After supplying the recovery current, supplying a sensing current to the selected memory cells to sense data from the selected memory cells, wherein the recovery current is quantitatively greater than the sensing current. Way. The method of claim 18, When the recovery current is supplied to the selected memory cells, a resistance value of each of the selected memory cells is restored to an initial resistance value of each of the plurality of data states regardless of the plurality of data states. Way. The method of claim 18, And the amount of recovery current is determined such that an initial resistance value of each of the plurality of data states does not change after the supply of the recovery current. The method of claim 18, The recovery current and the sense current are supplied from a sense amplifier circuit. The method of claim 18, The recovery current is supplied from a write driver circuit, and the sense current is supplied from a sense amplifier circuit. A method of reading a multi-level phase change memory device, each memory cell including one of a plurality of data states: Precharging the bit lines connected to the selected memory cells with a precharge voltage; Activating a word line coupled to the selected memory cells; Supplying a recovery current to selected ones of the memory cells; After supplying the recovery current, supplying a sensing current to the selected memory cells to sense data from the selected memory cells, wherein the recovery current is quantitatively greater than the sensing current. Way. The method of claim 23, When the recovery current is supplied to the selected memory cells, a resistance value of each of the selected memory cells is restored to an initial resistance value of each of the plurality of data states regardless of the plurality of data states. Way. The method of claim 23, And the amount of recovery current is determined such that an initial resistance value of each of the plurality of data states does not change after the supply of the recovery current. The method of claim 23, The recovery current and the sense current are supplied from a sense amplifier circuit. The method of claim 23, The recovery current is supplied from a write driver circuit, and the sense current is supplied from a sense amplifier circuit. A memory cell array having memory cells arranged in word lines and bit lines; Each of the memory cells has one of a plurality of data states corresponding to multi-level data; Sense amplifier circuitry configured to sense data from selected memory cells of the memory cell array; A write driver circuit configured to supply a write current to selected memory cells of the memory cell array in accordance with data input during a write operation; And And control logic to control one of the sense amplifying circuit and the write driver circuit to supply a recovery current to the selected memory cells before a sensing period of a read operation. The method of claim 28, When the recovery current is supplied to the selected memory cells, the resistance value of each of the selected memory cells is restored to the initial resistance value of each of the plurality of data states regardless of the plurality of data states. Memory device. The method of claim 28, And the recovery current is quantitatively greater than the sense current supplied from the sense amplifier circuit. The method of claim 28, And the amount of recovery current is determined such that an initial resistance value of each of the plurality of data states does not change after supply of the recovery current. The method of claim 28, And the control logic controls the sense amplifier circuit to supply the recovery current to the selected memory cells before the sense period. The method of claim 32, And the control logic controls the sense amplifier circuit to supply the recovery current to the selected memory cells during the precharge period before the sense period. The method of claim 28, And the control logic controls the write driver circuit to supply the recovery current to the selected memory cells before the sensing period. The method of claim 24, And the control logic controls the sense amplifying circuit to precharge selected bit lines prior to supply of the recovery current and to supply sense current to the selected bit lines during the sense period. The method of claim 34, wherein And the write driver circuit is activated by the control logic during the supply of the recovery current in the read operation. A memory cell array having memory cells arranged in word lines and bit lines; Each of the memory cells has one of a plurality of data states corresponding to multi-level data; Sense amplifier circuitry configured to sense data from selected memory cells of the memory cell array; And And control logic to control the sense amplifier circuit to supply a recovery current to the selected memory cells prior to a sense interval of a read operation. The method of claim 37, wherein When the recovery current is supplied to the selected memory cells, the resistance value of each of the selected memory cells is restored to the initial resistance value of each of the plurality of data states regardless of the plurality of data states. Memory device. The method of claim 37, wherein And the recovery current is quantitatively greater than the sense current. The method of claim 37, wherein And the amount of recovery current is determined such that an initial resistance value of each of the plurality of data states does not change after supply of the recovery current. The method of claim 37, wherein And the control logic controls the sense amplifier circuit to supply the recovery current to the selected memory cells during the precharge period before the sense period. The method of claim 37, wherein And a word line coupled to the selected memory cells is activated before the recovery current is supplied to the selected memory cells. A memory cell array having memory cells arranged in word lines and bit lines; Each of the memory cells has one of a plurality of data states corresponding to multi-level data; Sense amplifier circuitry configured to sense data from selected memory cells of the memory cell array; A write driver circuit configured to supply a write current to selected memory cells of the memory cell array in accordance with data input during a write operation; And And control logic to control the write driver circuit to supply a recovery current to the selected memory cells prior to a sensing interval of a read operation. The method of claim 43, When the recovery current is supplied to the selected memory cells, the resistance value of each of the selected memory cells is restored to the initial resistance value of each of the plurality of data states regardless of the plurality of data states. Memory device. The method of claim 43, And the recovery current is quantitatively greater than the sense current supplied from the sense amplifier circuit. The method of claim 43, And the amount of recovery current is determined such that an initial resistance value of each of the plurality of data states does not change after supply of the recovery current. The method of claim 43, And the recovery current is supplied for a time of about 10 mA to 10 mA.

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