KR20080095676A

KR20080095676A - Clock and data recovery method

Info

Publication number: KR20080095676A
Application number: KR1020070040483A
Authority: KR
Inventors: 조범식
Original assignee: 삼성전자주식회사
Priority date: 2007-04-25
Filing date: 2007-04-25
Publication date: 2008-10-29

Abstract

A clock and data recovery method is provided to solve a power consumption problem when applying a CDR test to all pins by applying a CDR test to only a specific pin. A clock and data recovery method is comprised of steps: determining one of data pins at the semiconductor memory device as a specific pin(220); testing a CDR test to the specific pin(230); removing a skew of the other pine excepting the specific pin by using phase difference which is determined at the CDR test(240).

Description

CDR method {Clock and Data Recovery Method}

BRIEF DESCRIPTION OF THE DRAWINGS In order to more fully understand the drawings recited in the detailed description of the invention, a brief description of each drawing is provided.

1 shows power consumption according to the application of the conventional CDR method.

2 is a flowchart illustrating a CDR method according to the present invention.

3 is a block diagram illustrating a CDR method according to the present invention.

4 is a timing diagram for explaining a CDR method according to the present invention.

The present invention relates to a method for removing skew between a clock signal and a data signal of a semiconductor memory device, and more particularly, to a clock and data recovery (CDR) method.

In a system including an arithmetic processing unit, a semiconductor memory device, and the like, in order to perform a high speed arithmetic or signal processing, a number of data bits that can be processed simultaneously by the arithmetic processing unit must be large. In addition, a large number of bits of data to be processed must be continuously supplied to the processing unit at the same time. To this end, a semiconductor memory device including data must simultaneously output a large number of bits of output data. The transmission and reception of data related to each other can improve the operation speed of the system.

As described above, when a large number of bits of output data simultaneously perform a switching operation to improve the operation speed of the system, a large amount of current is supplied from the power line to the switching device. At this time, the consumed current generates switching noise by parasitic components of the power line, resulting in delay and distortion of the output data. This different delay time between the output data causes skew between the output data, which increases as the number of bits of the output data of the semiconductor memory device increases, the larger the parasitic component and the higher the speed. The bigger it gets.

Here, skew means that the timing between data does not match. During the operation of the system, the delay time between the data outputted by the change of temperature or voltage is different, which may cause skew between the output data.

As a method for removing skew between data when reading data from or writing data to a semiconductor memory device (for example, a DRAM), data training and a clock and data recovery (CDR) method and the like. Is used.

The data training method is a method of adjusting skew between data using a data pattern previously promised between a controller controlling a semiconductor memory device and a memory device. The CDR method is mainly used in the field of serial link as a method of continuously removing skew while the semiconductor memory device is operating. The present invention particularly relates to CDR methods.

As can be seen in Figure 1, when applying the CDR method, it can be seen that the power consumption is doubled when compared based on 1 DQ. In particular, for X32 (when 32 DQ is applied overall), the current consumption is 320mA, so the excessive power consumption problem requires improvement.

Korean Patent Publication No. 2006-0106552 discloses such a CDR technology.

An object of the present invention is to provide a CDR method that can solve the above power consumption problem.

According to an aspect of the present invention, there is provided a Clock and Data Recovery (CDR) method comprising: determining one of the data pins of a semiconductor memory device as a representative pin, performing a CDR test on the representative pin; And removing skew of the data pins other than the representative pin by using the phase difference information determined in the CDR test on the representative pin.

The CDR method according to an embodiment of the present invention may further include CDR testing all data pins upon initialization of the semiconductor memory device. The method may further include CDR testing all data pins during the operation of the semiconductor memory device after the initialization is completed.

Preferably, the determining of the representative pin may include determining, by the controller that controls the semiconductor memory device, a pin having an intermediate value among the phase difference information determined by performing a CDR test on all the data pins. It features. In addition, after the representative pin is determined, the representative pin may be stored using a mode register set (MRS) of the semiconductor memory device.

Therefore, since the present invention applies the CDR test only to the representative pin, there is an effect of solving the power consumption problem that occurs when applying the CDR test on all pins.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a flowchart of a clock and data recovery (CDR) method according to the present invention.

Referring to FIG. 2, in the method of clock and data recovery (CDR) according to the present invention, determining one of the data pins of the semiconductor memory device as a representative pin (S220) and performing a CDR test on the representative pin (S230). And removing skew of the remaining data pins except the representative pin by using the phase difference information determined in the CDR test of the step S230. The CDR method according to the present invention may further include a step (S210) of CDR test all data pins at the time of initialization of the semiconductor memory device. In addition, the CDR test of all data pins (S210) may be used to CDR-test all data pins at the time of initialization of the semiconductor memory device as well as at the operation of the semiconductor memory device.

In operation S220, the controller that controls the semiconductor memory device may determine a pin having an intermediate value as the representative pin among phase difference information determined by performing a CDR test on all data pins of the semiconductor memory device. have. In operation S220, the representative pin may be stored using a mode register set (MRS) of the semiconductor memory device.

In step S230, the CDR test is performed on the representative pin, so that the current is consumed by applying the CDR test only to the representative pin, thereby solving the power consumption problem that occurs when the CDR test is applied to all the pins.

Referring to FIG. 3, a semiconductor memory device 320 and a controller 310 controlling the same are shown. 3 shows one byte, i.e., 8 bits.

In the CDR method according to the present invention, all data pins [0-7] are CDR-tested at the time of initialization of the system including the semiconductor memory device 320 to eliminate skew of each pin.

Even if the skew of each pin is removed at the time of initialization, after entering the system operation, the delay of the circuits may occur due to temperature or voltage change, and thus skew may occur. However, the delay occurring in the data according to the temperature or voltage change during the operation, the delay is almost the same for all data pins [0-7]. Accordingly, it is possible to eliminate skew by placing a representative pin without applying a CDR test to all the DQ pins, applying a CDR test only to the representative pins, and then transmitting the same phase difference information to the remaining DQ pins.

Referring to FIG. 3 again, among the DQ pins 0 to 7, the DQ pin 314 is designated as the representative pin. In this case, the CDR test is applied to only the 4th pin, and the remaining DQ pins except for the 4th pin are transferred to the phase difference information (OUT [4]) obtained by performing a CDR test only on the 4th pin. Remove skew.

The current is consumed by applying the CDR test on only pin 4, which solves the power consumption problem of applying the CDR test on all pins.

In FIG. 3, DQ [4] is illustrated as a representative pin. However, in determining the representative pin, it is preferable to designate a pin having a phase difference information of intermediate values among the phase difference information of actual DQ pins as a representative pin. This is because the error can be minimized.

According to the present invention, in order to find the representative pin, the controller 310 may apply a CDR test on all pins [0-7], and then, among the phase difference information, may determine a pin having an intermediate value as the representative pin. In addition, after the representative pin is determined, the representative pin may be stored using an MRS (not shown) of the semiconductor memory device 320, and then, the representative pin may be entered again into the CDR test mode.

4 is a timing diagram for explaining a CDR method according to the present invention. 4 shows one byte, i.e., 8 bits.

The timing diagram 410 shows the phase difference of the skew that may occur on all data pins [0-7] upon initialization of the system including the semiconductor memory device.

Timing diagram 420 shows the CDR test of all data pins [0-7] to remove skew of each pin.

As in the timing diagram 420, even if skew of each pin is removed at initialization, the circuit may be delayed by a change in temperature or voltage after entering system operation. However, the delay during the operation generally occurs with almost the same delay for all data pins [0-7].

Timing diagram 430 shows that for all data pins [0-7], the phase difference A has occurred due to almost the same delay. Therefore, removing the skew by putting the representative pin without applying the CDR test to all the DQ pins, applying the CDR test only to the representative pins, and passing the same phase difference information (A) to the remaining DQ pins. It is possible.

The timing diagram 440 illustrates a method of removing skew by transmitting the same phase difference information A to the remaining DQ pins except for the representative pin. Because the CDR test is applied only to the representative pin, its current is consumed only on the representative pin, eliminating the power dissipation that occurs when applying the CDR test to all pins.

Unlike in FIG. 4, in the case of determining the representative pin when the same phase difference information A does not occur and has an error, the pin having the intermediate value of phase difference information among the phase difference information of the actual DQ pins is represented as the representative pin. It is desirable to decide. This is because the error can be minimized.

In the above described the present invention with reference to the specific embodiment shown in the drawings, but this is only an example, those of ordinary skill in the art to which the present invention pertains various modifications and variations therefrom. Therefore, the protection scope of the present invention should be interpreted by the claims to be described later, and all technical ideas within the equivalent and equivalent ranges should be construed as being included in the protection scope of the present invention.

As described above, the present invention applies the CDR test only to the representative pin, and thus has an effect of solving the power consumption problem that occurs when the CDR test is applied to all the pins.

Claims

In a clock and data recovery (CDR) method for removing skew between a clock signal and a data signal of a semiconductor memory device,

(a) determining one of the data pins of the semiconductor memory device as a representative pin;

(b) CDR testing the representative pin; And

(c) removing skew of the remaining data pins except for the representative pin by using the phase difference information determined in the CDR test of step (b).

The method of claim 1, wherein the CDR method is

And CDR testing all the data pins upon initialization of the semiconductor memory device.

The method of claim 1, wherein the CDR method is

And CDR testing all of the data pins during operation of the semiconductor memory device.

The method of claim 1, wherein the determining of the representative pin of the step (a),

The controller controlling the semiconductor memory device determines a pin having an intermediate value among the phase difference information determined by performing a CDR test on all the data pins as the representative pin.

The method of claim 4, wherein the determining of the representative pin of the step (a),

After determining the representative pin, storing the representative pin using a mode register set (MRS) of the semiconductor memory device.