KR20080095043A

KR20080095043A - Plasma display apparatus

Info

Publication number: KR20080095043A
Application number: KR1020070039337A
Authority: KR
Inventors: 권유진
Original assignee: 엘지전자 주식회사
Priority date: 2007-04-23
Filing date: 2007-04-23
Publication date: 2008-10-28

Abstract

A plasma display device is provided to reduce a manufacturing cost by omitting a transmission line for delivering control signals to the plasma display device from the display device by using a data line. A plasma display device includes a PDP(100), a data driver(130), and a data IC(120). Address electrodes are formed on the PDP(Plasma Display Panel). The data driver processes input image signals. The data IC supplies data signals to the address electrodes according to an image signal, which is processed in the data driver. A data line, a strobe line, and a clock line are arranged between the data driver and the data IC. A control signal and the data are supplied from the data driver to the data IC through the data lines.

Description

Plasma Display Apparatus {Plasma Display Apparatus}

BRIEF DESCRIPTION OF THE DRAWINGS The figure for demonstrating the structure of the plasma display apparatus of this invention.

2A to 2B are views for explaining an example of the structure of the plasma display panel.

3 is a view for explaining an example of the operation of the plasma display device according to an embodiment of the present invention;

4A to 4C are diagrams for explaining a data driver and a data integrated circuit unit.

5A to 5B are diagrams for explaining signal transmission between a data driver and a data integrated circuit unit.

FIG. 6 is a diagram for explaining the reason why a control signal and data are supplied together to a data line; FIG.

7 is a diagram for explaining data.

FIG. 8 is a diagram for explaining an example of a configuration for supplying data to a plurality of data integrated circuits in one data line. FIG.

9 is a view for explaining an example of a data transmission method in the case of FIG.

10 is a diagram for explaining the supply of a clock signal in more detail.

100: plasma display panel 110: heat dissipation frame

120: data integrated circuit unit 130: data driver

140: flexible board 150: connector

The present invention relates to a plasma display device.

The plasma display apparatus includes a plasma display panel.

In general, a phosphor layer is formed in a discharge cell (Cell) partitioned by a partition, and a plurality of electrodes is formed in the plasma display panel.

The driving signal is supplied to the discharge cell through the electrode.

Then, the discharge is generated by the drive signal supplied in the discharge cell. Here, when discharged by a drive signal in the discharge cell, the discharge gas filled in the discharge cell generates vacuum ultraviolet rays, and the vacuum ultraviolet light emits the phosphor formed in the discharge cell to emit visible light. Generate. The visible light displays an image on the screen of the plasma display panel.

One embodiment of the present invention is to provide a plasma display device having a reduced manufacturing cost by improving a method of transmitting data and control signals.

According to an embodiment of the present invention, a plasma display apparatus includes a plasma display panel having an address electrode, a data driver for signal processing an input image signal, and data for supplying a data signal to an address electrode according to an image signal processed by the data driver. An integrated circuit unit, and a data line, a strobe line, and a clock line are disposed between the data driver and the data integrated circuit unit, and a control signal and data are transferred through the data line. From the data integrated circuit.

In addition, during one period of the strobe signal STB supplied from the data driver to the data integrated circuit through the strobe line, the control signal and the data may be supplied together through the data line.

In addition, the control signal may be placed in front of the data.

In addition, the control signal may include an enable signal.

In addition, the clock signal may be supplied from the data driver to the data integrated circuit unit through the clock line in the first period, and the clock signal may not be supplied in the second period different from the first period.

In addition, the first period may be a period during which the control signals and data are supplied, and the second period may be a period during which the control signals and data are not supplied.

Hereinafter, a plasma display device of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining the configuration of the plasma display device of the present invention.

Referring to FIG. 1, the plasma display apparatus of the present invention includes a plasma display panel 100, a data driver 130, and a data drive integrated circuit 120. In addition, the plasma display apparatus of the present invention may further include a heat dissipation frame 110, a flexible substrate 140, and a connector 150.

An address electrode (not shown) is formed in the plasma display panel 100.

The data driver 130 processes the input image signal.

The data integrated circuit unit 120 supplies a data signal to the address electrode X of the plasma display panel 100 by performing a predetermined switching operation according to the image signal processed by the data driver 130.

The data integrated circuit unit 120 is preferably disposed on a flexible circuit board, that is, the flexible substrate 140. The flexible substrate 140 may be a kind of a tape carrier package (TCP), a chip on film (COF), or the like.

Here, one end of the flexible substrate 140 may be connected to the address electrode X of the plasma display panel 100, and the other end thereof may be connected to the data driver 130 through the connector 150.

The heat dissipation frame 110 is disposed on the rear surface of the plasma display panel, and provides a space in which the data driver 130 can be disposed.

Here, in FIG. 1, only the data driver 130 is disposed on the rear surface of the heat dissipation frame. However, the scan driver and the sustain electrode (not shown) supply a driving signal to a scan electrode (not shown) of the plasma display panel 100. It is also possible to further include a sustain driving unit for supplying a driving signal to the.

2A to 2B are diagrams for explaining an example of the structure of the plasma display panel.

First, referring to FIG. 2A, a plasma display panel that may be included in a plasma display apparatus according to an embodiment of the present invention includes a front substrate 201 in which scan electrodes 202 and Y and sustain electrodes 203 and Z are parallel to each other. ) And the rear substrate 211 on which the address electrodes 213 and X intersecting the scan electrodes 202 and Y and the sustain electrodes 203 and Z are formed.

The front substrate 201 on which the scan electrodes 202 and Y and the sustain electrodes 203 and Z are formed has a dielectric layer such as an upper dielectric layer 204 to cover the scan electrodes 202 and Y and the sustain electrodes 203 and Z. ) May be arranged.

The upper dielectric layer 204 limits the discharge current of the scan electrodes 202 and Y and the sustain electrodes 203 and Z and may insulate between the scan electrodes 202 and Y and the sustain electrodes 203 and Z.

A protective layer 205 may be formed on the front substrate 201 where the upper dielectric layer 204 is formed to facilitate discharge conditions. The protective layer 205 may include a material having a high secondary electron emission coefficient such as magnesium oxide (MgO).

Meanwhile, electrodes, for example, address electrodes 213 and X are formed on the rear substrate 211, and the address electrodes 213 and X are covered on the rear substrate 211 on which the address electrodes 213 and X are formed. Dielectric layer, such as lower dielectric layer 215 may be formed.

The lower dielectric layer 215 may insulate the address electrodes 213 and X.

On top of the lower dielectric layer 215, a partition 212, such as a stripe type, a well type, a delta type, a honeycomb type, for partitioning a discharge cell, that is, a discharge cell, is formed. Can be formed. Accordingly, red (R), green (G), and blue (B) discharge cells may be formed between the front substrate 201 and the rear substrate 211.

In addition to the red (R), green (G), and blue (B) discharge cells, it is also possible to further form a white (W) or yellow (Yellow: Y) discharge cell.

Meanwhile, although the widths of the red (R), green (G), and blue (B) discharge cells in the plasma display panel that can be applied to the plasma display device according to an embodiment of the present invention may be substantially the same, red ( The width of at least one of the R), green (G), and blue (B) discharge cells may be different from that of the other discharge cells.

For example, the width of the red (R) discharge cell is the smallest, and the width of the green (G) and blue (B) discharge cells can be made larger than the width of the red (R) discharge cell.

Here, the width of the green (G) discharge cell may be substantially the same as or different from the width of the blue (B) discharge cell.

As such, when formed, the width of the phosphor layer 214 to be described later formed in the discharge cell is also changed in relation to the width of the discharge cell. For example, the width of the blue (B) phosphor layer formed in the blue (B) discharge cell is wider than the width of the red (R) phosphor layer formed in the red (R) discharge cell, and at the same time in the green (G) discharge cell. The width of the green (G) phosphor layer formed may be wider than the width of the red (R) phosphor layer formed in the red (R) discharge cell.

Then, color temperature characteristics of the image to be implemented may be improved.

In addition, the plasma display panel that can be applied to the plasma display apparatus according to an exemplary embodiment of the present invention may have not only the structure of the partition 212 illustrated in FIG. 2 but also the structure of the partition having various shapes. For example, the partition 212 includes a first partition 212b and a second partition 212a, where the height of the first partition 212b and the height of the second partition 212a are different from each other. At least one of the first barrier rib 212b and the second barrier rib 212a, and a channel type barrier rib structure having a channel usable as an exhaust passage, at least one of the first barrier rib 212b and the second barrier rib 212a. Grooved partition wall structure having a groove formed in the groove will be possible.

In the case of the differential partition wall structure, the height of the first partition wall 212b may be lower than the height of the second partition wall 212a. In addition, in the case of the channel-type partition wall structure, a channel may be formed in the first partition wall 212b.

In addition, in the plasma display panel applicable to the plasma display device according to the exemplary embodiment of the present invention, the red (R), green (G), and blue (B) discharge cells are illustrated and described as being arranged on the same line. It may be possible to arrange them in other shapes. For example, a delta type arrangement in which red (R), green (G) and blue (B) discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may also be a variety of polygonal shapes, such as pentagonal, hexagonal, as well as rectangular.

In addition, in FIG. 2, only the case where the barrier rib 212 is formed on the rear substrate 211 is illustrated, but the barrier rib 212 may be formed on at least one of the front substrate 201 and the rear substrate 211.

Here, a predetermined discharge gas may be filled in the discharge cell partitioned by the partition wall 212.

In addition, a phosphor layer 214 that emits visible light for image display may be formed in the discharge cells partitioned by the partition wall 212. For example, red (R), green (G), and blue (B) phosphor layers may be formed.

In addition to the red (R), green (G), and blue (B) phosphors, it is also possible to further form a white (W) and / or yellow (Y) phosphor layer.

In addition, the thickness of the phosphor layer 214 in at least one of the red (R), green (G), and blue (B) discharge cells may be different from other discharge cells. For example, the thickness of the phosphor layer of the green (G) discharge cell, ie the phosphor layer in the green (G) phosphor layer or the blue (B) discharge cell, ie the blue (B) phosphor layer, is It may be thicker than the thickness of the phosphor layer, ie the red (R) phosphor layer. Here, the thickness of the green (G) phosphor layer may be substantially the same as or different from the thickness of the blue (B) phosphor layer.

Meanwhile, only the example of the plasma display panel which can be applied to the plasma display apparatus according to the exemplary embodiment of the present invention is shown and described, and the present invention is not limited to the plasma display panel having the above-described structure. . For example, the description hereinabove illustrates only the case where the top dielectric layer at number 204 and the bottom dielectric layer at number 215 are each one layer, but one or more of these top dielectric layers and bottom dielectric layers are a plurality of layers. It can also be layered.

In addition, a black matrix (not shown) may be further disposed on the partition 212 to prevent reflection of the external light due to the partition 212.

In addition, another black matrix (not shown) may be further formed at a specific position on the front substrate 201 corresponding to the partition 212.

In addition, the address electrode 213 formed on the rear substrate 211 may have substantially the same width or thickness, but the width or thickness inside the discharge cell may be different from the width or thickness outside the discharge cell. . For example, the width or thickness inside the discharge cell may be wider or thicker than that outside the discharge cell.

Next, referring to FIG. 2B, an example of another structure of the scan electrode and the sustain electrode is illustrated.

The scan electrode 202 and the sustain electrode 203 may each have a multi-layer structure. For example, the scan electrode 202 and the sustain electrode 203 may include the transparent electrodes 202a and 203a and the bus electrodes 202b and 203b.

Here, the bus electrodes 202b and 203b include substantially opaque materials such as silver (Ag), gold (Au) and aluminum (Al), and the transparent electrodes 202a and 203a are substantially transparent materials, for example It may include an indium tin oxide (ITO) material.

In addition, when the scan electrode 202 and the sustain electrode 203 include the bus electrodes 202b and 203b and the transparent electrodes 202a and 203a, the reflection of external light by the bus electrodes 202b and 203b is prevented. The black layers 220 and 230 may be further included between the transparent electrodes 202a and 203a and the bus electrodes 202b and 203b.

On the other hand, the transparent electrodes 202a and 203a may be omitted from the scan electrode 202 and the sustain electrode 203. That is, the scan electrode 202 and the sustain electrode 203 can also be ITO-Less electrodes in which the transparent electrodes 202a and 203a are omitted.

3 is a view for explaining an example of the operation of the plasma display device according to an embodiment of the present invention.

Referring to FIG. 3, a reset signal may be supplied to a scan electrode in a reset period for initialization. The reset signal may include a ramp-up signal and a ramp-down signal.

For example, in the set-up period, the voltage gradually increases from the second voltage V2 to the third voltage V3 after the voltage rises rapidly from the first voltage V1 to the second voltage V2 with the scan electrode. Rising rising ramp signals may be supplied. Here, the first voltage V1 may be a voltage of the ground level GND.

In this setup period, a weak dark discharge, that is, a setup discharge occurs in the discharge cell by the rising ramp signal. By this setup discharge, some wall charges can be accumulated in the discharge cells.

In the set-down period after the setup period, the rising ramp signal may be supplied to the scan electrode after the rising ramp signal in the opposite polarity direction.

Here, the falling ramp signal may gradually fall from the peak voltage of the rising ramp signal, that is, the fourth voltage V4 lower than the third voltage V3 to the fifth voltage V5.

As the falling ramp signal is supplied, a weak erase discharge, that is, a setdown discharge, occurs in the discharge cell. By this set-down discharge, wall charges such that address discharge can be stably generated in the discharge cells remain uniformly.

In the address period after the reset period, a scan bias signal that substantially maintains the lowest voltage of the falling ramp signal, that is, a voltage higher than the fifth voltage V5, for example, the sixth voltage V6, is supplied to the scan electrode.

In addition, a scan signal falling from the scan bias signal may be supplied to the scan electrode.

Meanwhile, the pulse width of the scan signal supplied to the scan electrode in the address period of at least one subfield may be different from the pulse width of the scan signal of another subfield. For example, the width of the scan signal in the subfield located later in time may be smaller than the width of the scan signal in the subfield located in front. In addition, the reduction of the scan signal width according to the arrangement order of the subfields can be made gradually, such as 2.6 Hz (microseconds), 2.3 Hz, 2.1 Hz, 1.9 Hz, or 2.6 Hz, 2.3 Hz, 2.3 Hz, 2.1 Hz. .... 1.9 ㎲, 1.9 ㎲ and so on.

As such, when the scan signal is supplied to the scan electrode, the data signal may be supplied to the address electrode corresponding to the scan signal. The data signal is supplied by the data integrated circuit unit 120 through a predetermined switching operation according to the image signal processed by the data driver 130 of FIG. 1.

When the scan signal and the data signal are supplied, an address discharge may be generated in the discharge cell to which the data signal is supplied while the voltage difference between the scan signal and the data signal and the wall voltage generated by the wall charges generated in the reset period are added. .

Here, the sustain bias signal may be supplied to the sustain electrode in order to prevent the address discharge from becoming unstable due to the interference of the sustain electrode in the address period.

The sustain bias signal can keep the sustain bias voltage Vz smaller than the voltage of the sustain signal supplied in the sustain period and larger than the voltage of the ground level GND.

Subsequently, in the sustain period for displaying an image, a sustain signal may be supplied to at least one of the scan electrode and the sustain electrode. For example, a sustain signal may be alternately supplied to the scan electrode and the sustain electrode.

When such a sustain signal is supplied, the discharge cell selected by the address discharge is added with the wall voltage in the discharge cell and the sustain voltage Vs of the sustain signal, and a sustain discharge, i.e., display between the scan electrode and the sustain electrode when the sustain signal is supplied. Discharge may occur.

Meanwhile, in the at least one subfield, a plurality of sustain signals are supplied in the sustain period, and the pulse width of at least one sustain signal of the plurality of sustain signals may be different from the pulse widths of other sustain signals. For example, the pulse width of the sustain signal that is supplied first of the plurality of sustain signals may be larger than the pulse width of other sustain signals. Then, the sustain discharge can be more stabilized.

Next, FIGS. 4A to 4C are diagrams for describing the data driver and the data integrated circuit.

First, referring to FIG. 4A, a plurality of data integrated circuit units 411 ˜ 418 may be provided, and the data driver 400 may supply data Data to the plurality of data integrated circuit units 411 ˜ 418.

For example, as shown in FIG. 4A, data lines are disposed from the data driver 400 to each of the data integrated circuit units 411 to 418, and data is transferred to each of the data integrated circuit units 411 to 418 through these data lines. Each can be supplied. In the figure, data lines to which data can be supplied are indicated by arrows.

Next, FIG. 4B shows the connection of the data driver and the data integrated circuit in more detail.

Referring to FIG. 4B, a data line 420, a strobe line 421, and a clock line 422 are disposed between the data driver 400 and the data integrated circuit 411.

The clock signal CLK is supplied from the data driver 400 to the data integrated circuit unit 411 through the clock line 422.

The strobe signal STB is supplied from the data driver 400 to the data integrated circuit unit 411 through the strobe line 421.

The data and the control signal CTR are supplied from the data driver 400 to the data integrated circuit unit 411 through the data line 420.

At least one of the strobe line 421 and the clock line 422 may be commonly connected to the plurality of data integrated circuits 411 to 418. For example, one strobe line 421 is commonly connected to the data driver 400 and the data integrated circuit parts 411 to 418, and each of the strobe lines 421 is connected to the data driver 400 through the one strobe line 421. The strobe signal may be supplied to the data integrated circuits 411 to 418.

Alternatively, one clock line may supply a clock signal in common to four data integrated circuit units.

Next, Fig. 4C shows an example of the configuration of the data driver.

Referring to FIG. 4C, the data driver may further include an inverse gamma correction unit 401, a halftone correction unit 402, a subfield mapping unit 403, and a data alignment unit 404.

The reverse gamma correction unit 401 may correct the input image signal by reverse gamma.

The halftone corrector 402 may correct halftones of an input image signal through an error diffusion method, a dithering method, or the like.

The subfield mapping unit 403 may subfield map the reverse gamma corrected and halftone corrected image data.

The data aligner 404 may align the subfield mapped signal to correspond to the address electrode of the plasma display panel.

The data driver having such a configuration may sub-field map and output the corrected image signal after inverse gamma correction and halftone correction. Accordingly, the data supplied from the data driver to the data integrated circuit unit may be subfield mapped data.

Next, FIGS. 5A to 5B are diagrams for explaining signal transmission between a data driver and a data integrated circuit.

First, referring to FIG. 5A, a strobe signal is supplied through a strobe line, and a control signal CTR and data are supplied together through a data line while a clock signal is supplied through a clock line. That is, the control signal and data are supplied through the same transmission line.

Preferably, the control signal and the data are supplied together through the data line during one period T of the strobe signal supplied from the data driver to the data integrated circuit part via the strobe line.

For example, as shown in FIG. 5B, the control signal CTR is supplied to correspond to the four clock signals in the period of ① and the data (Data) to correspond to the total of 32 clock signals in the period of ② after the ① period. ) Can be supplied.

Here, when one period of the strobe signal is excessively long, the transmission speed of the data may be excessively slow, while data transmission may become unstable when one period of the strobe signal is excessively short. Accordingly, it may be desirable that one period of the strobe signal is 1200 ns or more and 1800 ns or less.

Such a control signal may include an enable signal to confirm data, and may be preferably placed in front of the data. In other words, the Data Enable signal is supplied in front of the data to confirm that the signal supplied through the data line is data.

Then, the data integrated circuit may recognize the signal supplied after the enable signal as data and read the recognized data.

Thereafter, the data integrated circuit unit performs a predetermined switching operation according to the read data to supply the data signal to the address electrode of the plasma display panel.

On the other hand, the control signal may be disposed before and after the data, respectively.

In addition, the control signal may include various control signals such as a BLK signal, a test mode signal, a POC signal, a CSR signal, and an F / R signal.

The reason for supplying the control signal and the data together through the data line as described above will be described with reference to FIG. 6.

FIG. 6 is a diagram for explaining a reason why a control signal and data are supplied together to a data line.

Referring to FIG. 6, an example of the case of further including a control line CTR for supplying a control signal is illustrated.

In this case, a control signal such as an enable signal can be supplied through the control line, but the manufacturing cost may increase according to the addition of the control line.

On the other hand, when the control signal and data are supplied together to the data line as shown in FIGS. 5A to 5B, the manufacturing cost may be lowered because it is not necessary to arrange additional control lines.

Next, FIG. 7 is a diagram for explaining data.

Referring to FIG. 7, the data supplied from the data driver to the data integrated circuit unit may be a differential signal.

The differential signal includes a first signal having a predetermined swing width based on the reference voltage V _Ref and a second signal inverted from the first signal.

These differential signals include Low Voltage Differential Signals (LVDS), Bus Low Voltage Differential Signals (BLVDS), Multipoint Low Voltage Differential Signals (MLVDS), Mini Low The voltage differential signal may be at least one of Mini Low Voltage Differential Signals and Reduced Swing Differential Signals.

Here, the first signal and the second signal have a predetermined voltage difference (VV). The voltage difference (V) between the first signal and the second signal may vary according to the type of the differential signal. For example, the difference (ㅿ V) between the voltages of the first signal and the second signal of the low voltage differential signal type, the mini low voltage differential signal type, and the reduced width differential signal type may be different from each other.

For example, in the low voltage differential signal type, the voltage difference (ㅿ V) of the first signal and the second signal is approximately 350 mV, and in the mini low voltage differential signal type, the voltage difference (ㅿ V) of the first signal and the second signal Can be set to approximately 200 mV.

As such, when data is transmitted in the form of differential signals, the influence of noise can be reduced. For example, even when the voltage level of the differential signal drops due to the resistance and inductance components parasitic in the transmission line during data transmission, the difference between the voltage level between the first signal and the second signal is kept constant, so that even if noise occurs. Stable data transmission is possible.

Next, FIG. 8 is a diagram for explaining an example of a configuration for supplying data to a plurality of data integrated circuits in one data line.

Referring to FIG. 8, a plurality of data integrated circuit units 811 to 818 are provided, and the data driver 800 supplies data to the plurality of data integrated circuit units 811 to 818, and the data driver 800 is one. The data line can supply data to the plurality of data integrated circuits.

For example, as shown in FIG. 8, the data driver 800 may supply data to two data integrated circuits as one data line. In the figure, data lines to which data can be supplied are indicated by arrows.

In this manner, when data is supplied to the plurality of data integrated circuits in one data line, the number of data lines can be reduced, and manufacturing cost can be reduced.

Next, FIG. 9 is a diagram for explaining an example of a data transmission method in the case of FIG. 8.

9, the strobe signal is supplied through the strobe line, and the control signals CTR 1 and CTR 2 and the data Data 1 and Data 2 are supplied together through the data line while the clock signal is supplied through the clock line. do.

For example, suppose that data is supplied to the first data integrated circuit unit and the second data integrated circuit unit from the data driver through one data line.

First, as shown in FIG. 9, the first control signal CTR 1 may be supplied, and thereafter, the first data may be supplied with Data 1. Here, the first control signal may be an enable signal for confirming that data supplied later, that is, the first data corresponds to data corresponding to the first data integrated circuit unit.

Then, the first data integrated circuit unit may read the first data according to the first control signal.

After the first data is supplied, the second control signal CTR 2 may be supplied, and thereafter, the second data Data 2 may be supplied. Here, the second control signal may be an enable signal for confirming that data supplied later, that is, the second data corresponds to data corresponding to the second data integrated circuit unit.

Then, the second data integrated circuit unit may read the second data according to the second control signal.

Thereafter, the first and second data integrated circuit units perform a predetermined switching operation according to the read data to supply the data signal to the address electrode of the plasma display panel.

As described above, when data is supplied to a plurality of data integrated circuits through one data line, the number of data lines may be reduced, thereby lowering the manufacturing cost.

10 is a diagram for explaining the supply of the clock signal in more detail.

Referring to FIG. 10, a clock signal may be supplied through a clock line during a period in which a control signal and a data signal are supplied to a data line, and the clock signal may not be supplied in the remaining period.

For example, as shown in FIG. 10, a period in which control signals and data are supplied is referred to as a first period, and a period in which control signals and data are not supplied is referred to as a second period.

In the first period, a clock signal is supplied from the data driver to the data integrated circuit unit. In the second period, the data driver calculates a clock signal therein but does not generate a clock signal.

As a result, the number of clock generating operations for generating the clock signal in the data driver may be reduced, thereby reducing the load of the data driver and heat generated by the data driver.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

In the plasma display apparatus according to the exemplary embodiment of the present invention, since the control signal and the data are supplied together to the data line, the transmission line of the control signal can be omitted, thereby reducing the manufacturing cost.

Claims

A plasma display panel having an address electrode formed thereon;

A data driver which processes an input video signal; And

A data integrated circuit unit which supplies a data signal to the address electrode according to an image signal processed by the data driver;

Including,

A data line, a strobe line, and a clock line are disposed between the data driver and the data integrated circuit.

And a control signal and data are supplied from the data driver to the data integrated circuit through the data line.

The method of claim 1,

And the control signal and data are supplied together through the data line during one period of the strobe signal (STB) supplied from the data driver to the data integrated circuit unit through the strobe line.

The method of claim 1,

And the control signal is disposed in front of the data.

The method of claim 1,

And the control signal comprises an enable signal.

The method of claim 1,

In a first period, a clock signal is supplied from the data driver to the data integrated circuit through the clock line.

And the clock signal is not supplied in a second period different from the first period.

The method of claim 5, wherein

And the first period is a period during which the control signal and data are supplied, and the second period is a period during which the control signal and data are not supplied.