KR20080092731A - Non-volatile memory device and method of manufacturing the same - Google Patents

Abstract

A nonvolatile memory device and a method for manufacturing the same are provided to prevent electrons from being implanted into a floating gate of a non-select memory transistor by forming a gate dielectric after an insulating pattern is formed on a substrate. An active region is defined on a substrate(100). A gate insulating pattern is formed on the substrate. A gate dielectric(120) including the gate insulating pattern is formed along the substrate surface. A select line(SL) and a word line(WL) are formed on the gate dielectric. A part of the select line is overlapped with the gate insulating pattern. The word line is separated from the select line. The word line is separated from the gate insulating pattern. The select line and the word line are extended in a direction being intersected with the active region. When the gate insulating pattern is formed, a first dielectric is formed on the substrate. A mask pattern is formed on the first dielectric. The first dielectric is etched by using the mask pattern.

Description

Nonvolatile memory device and manufacturing method thereof {NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME}

1 is a plan view of an ypyrom device according to an embodiment of the present invention.

2 and 3 are cross-sectional views taken along the line II ′ of FIG. 1 showing an ypyrom device according to embodiments of the present invention.

4 to 13 are cross-sectional views taken along line II ′ of FIG. 1 illustrating a method of manufacturing an ypyrom device according to example embodiments.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to an ypyrom device having two transistors and a method of manufacturing the same.

A nonvolatile memory device may retain stored information even when power supply is interrupted. Among the nonvolatile memory devices, an electrically erasable and programmable read only memory (EEPROM) device is a memory device that can electrically program and erase data. Among the Y pyrom elements, FLOTOX (floating gate tunnel oxide type) Y pyrom includes a memory transistor for storing information and a selection transistor for controlling electrical access to the memory transistor. do. The memory transistor includes a floating gate insulated from the surroundings.

The floating gate stores one or zero levels of data by injecting or emitting electrons by Fowler-Nordheim tunneling. For example, during a write operation, electrons are injected into the floating gate. The amount of electrons injected into the floating gate affects the channel potential of the memory transistor to determine the information stored in the memory transistor.

In order to improve the data processing speed, a high capacity device is required. Therefore, the unit cell size of the ypyrom must be reduced to increase the memory capacity of the unit cell. As the unit cell size is reduced, cell characteristics may deteriorate. For example, as the cell size is reduced, the effective channel length of the memory transistor may be shortened. Therefore, depletion layers between adjacent impurity regions may be connected to cause a punch through phenomenon. Cell characteristics may be deteriorated by the punch-through phenomenon. Therefore, the characteristics of the Y-pyrom device may be degraded, and further reduction of the unit cell of the FLOTOX type Y-pyrom device is difficult.

In order to compensate for this, a two transistor type eeprom device has been proposed. The two transistor type Y pyrom device includes a selection transistor arranged along a selection line and a memory transistor arranged along a word line. In this case, the memory transistor does not need a separate tunnel region. Therefore, since the unit cell can be further reduced, a more integrated semiconductor device can be manufactured. However, as the distance between the selection transistor and the memory transistor is reduced, program disturbance may become serious. The program disturbance means that electrons are injected and programmed into the floating gate of the non-selected memory transistor when the specific memory transistor is programmed. For example, when a particular memory transistor is programmed, a negative voltage is applied across the select line. At this time, a negative voltage is also applied to the selection transistors paired with the unselected memory transistors, and the adjacent floating region is in the ground state. Accordingly, an electron-hole pair may be generated by the voltage difference between the selection transistor and the floating region, and the electrons may be hot electrons and injected into the floating gate of the non-selection memory transistor. As a result, unwanted programs may occur in the unselected memory transistors.

An object of the present invention for solving the above problems is to provide a nonvolatile memory device having an improved reliability and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, the method including: defining an active region in a substrate, forming a gate insulating pattern on the substrate, and forming a gate along the surface of the substrate. Forming a gate insulating layer including an insulating pattern, and forming a selection line partially overlapping the gate insulating pattern and a word line spaced apart from the selection line on the gate insulating layer.

In example embodiments, the word line may be formed to be spaced apart from the insulating pattern.

In example embodiments, the word line may be formed to partially overlap the insulating pattern.

In example embodiments, the selection line and the word line may extend in a direction crossing the active region.

In example embodiments, the forming of the gate insulating pattern may include forming a first insulating film on the substrate, forming a mask pattern on the first insulating film, and using the mask pattern. And etching the insulating film.

In example embodiments, the forming of the gate insulating layer may include oxidizing the gate insulating pattern and the substrate, wherein the gate insulating layer has a first thickness on the substrate on which the gate insulating pattern is formed. It is possible to have a second region adjacent to the first region and the first region and having a second thickness thinner than the first thickness.

In addition, a nonvolatile memory device according to an embodiment of the present invention for achieving the above object is a substrate, a selection line extending on the substrate, a word line and spaced apart from the selection line and the selection line and the word line; A gate insulating film interposed between the substrate, the gate insulating film including a first region and a second region thinner than the first region, the first region overlapping a portion of the selection line, the portion being the It is an edge of the selection line, which edge is in the word line direction.

In example embodiments, the word line may be spaced apart from the first region.

In example embodiments, the first region may overlap a portion of the word line, the portion may be an edge of the word line, and the edge may be in the direction of the selection line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following examples and can be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Parts denoted by the same reference numerals throughout the specification represent the same components.

1 to 3, an ypyrom device according to embodiments of the present invention is described. 1 and 2, an ypyrom device according to an embodiment of the present invention is described.

1 and 2, the substrate 100 includes an active region 115 defined by the device isolation region 110. The selection line SL and the word line WL extend in a direction crossing the active region 115. A plurality of select transistors are arranged along the select line SL, and a plurality of memory transistors are arranged along the word line WL. The pair of select lines SL and the word lines WL are unit lines and are repeated on the substrate.

The substrate 100 includes an impurity region. The impurity region may include a source region 170, a drain region 174, and a floating region 172. The source region 170 is located at one side of the selection line SL, the drain region 174 is located at one side of the word line WL, and the floating region 172 is at the selection line SL. And between the word line WL. The source region 170 is a common source CS. The drain region 174 is connected to a contact C electrically connected to a bit line (not shown).

The selection line SL may include a gate insulating layer 120, a first conductive polysilicon pattern 130, a first dielectric pattern 133, and a second conductive polysilicon pattern 135. The word line WL may include a gate insulating layer 120, a floating gate 140, a second dielectric pattern 143, and a control gate 145. The gate insulating layer 120 includes a first region 121 having a first thickness T1 and a second region 122 having a second thickness T2. The first thickness T1 is thicker than the second thickness T2. The first region 121 extends along an edge of the selection line SL. The edge faces the word line WL. That is, the first region 121 may overlap the selection line SL and a portion of the floating region 172. Therefore, the selection line SL may contact both the first region 121 and the second region 122 of the gate insulating layer 120. As a result, a portion of the selection line SL facing the word line WL may be higher than an opposite portion thereof. The word line WL is in contact with the second region 122 of the gate insulating layer 120.

Since the device has a first region, it is possible to obtain an effect of increasing an interval between a selection line and a word line. The first region may reduce the voltage difference between the gate and the floating region of the adjacent selection line to reduce the generation of the electron hole pair. Thus, during programming, electrons can be prevented from being injected into the unselected memory transistors of the word line.

1 and 3, an ypyrom device according to another embodiment of the present invention is described. Hereinafter, the same content as described above will be briefly described.

On the substrate 100 where the active region 115 is defined by the device isolation region 110, the selection line SL and the word line WL extend in the direction crossing the active region 115, respectively.

The substrate 100 may include an impurity region of the source region 170, the drain region 174, and the floating region 172. The source region 170 is located on one side of the selection line SL, the drain region 174 is located on one side of the word line WL, and the floating region 172 is the selection line SL. ) And the word line WL.

The selection line SL may include a gate insulating layer 150, a first conductive polysilicon pattern 160, a first dielectric pattern 163, and a second conductive polysilicon pattern 165. The word line WL may include a gate insulating layer 150, a floating gate 170, a second dielectric pattern 173, and a control gate 175. The gate insulating layer 150 may include a first region 151 having a first thickness T1 and a second region 152 having a second thickness T2. The first thickness T1 is thicker than the second thickness T2. The selection line SL and the word line WL may contact both the first region 151 and the second region 152 of the gate insulating layer 150. Both edges of the first region 151 extend with the selection line SL and the word line WL, respectively. Therefore, the first region 151 may be symmetrical with respect to the floating region F. FIG. As a result, portions of the selection line SL and the word line WL may be higher than opposite portions thereof.

The device has a first region, thereby preventing electrons from being injected into the floating gate of an unselected memory transistor of a word line by preventing the generation of an electron hole pair. Thus, the device can prevent program disturbance.

For example, in the above embodiments, a P type well may be formed in the substrate 100, and the impurity region may be doped with an N type impurity. The selection line SL may include a butting contact in the dielectric patterns 133 and 163. Alternatively, the selection line SL may be formed in one conductive pattern.

A method of manufacturing an ypyrom device according to embodiments of the present invention is described. 4 to 8, a method of manufacturing an ypyrom device according to an embodiment of the present invention will be described.

Referring to FIG. 4, a substrate 200 is provided. For example, the substrate 200 may include a P-type well. An isolation region (not shown) is formed on the substrate 200. An active region is defined by the device isolation region. The device isolation region may be formed by a shallow trench isolation (STI) process.

The first insulating layer 202 is formed on the substrate 200. The first insulating layer 202 may be formed by a thermal oxidation process, and may be a silicon oxide layer. A mask pattern 205 is formed on the first insulating layer 202. The mask pattern 205 may be formed by a lithography process.

4 and 5, an insulating pattern 204 is formed by etching the first insulating layer 202 using the mask pattern 205. Thereafter, the mask pattern 205 may be removed.

Referring to FIG. 6, the gate insulating layer 220 is formed by oxidizing a surface of the substrate 200 including the insulating pattern 204. For example, the oxidation may be performed by a thermal oxidation process. Due to the insulating pattern 204, the gate insulating layer 220 may include first and second regions 221 and 222 having different thicknesses. The first region 221 is an oxidized region in which the insulating pattern 204 is formed, and the second region 222 is an oxidized region in the other region. Therefore, the first region 221 may be formed thicker than the second region 222.

Referring to FIG. 7, a first conductive layer 230 is formed on the gate insulating layer 220. The first conductive film 230 forming process may include a polysilicon film forming process and an impurity implantation process. A dielectric layer 240 is formed on the first conductive layer 230. The second conductive layer 250 is formed on the dielectric layer 240. The second conductive film 250 forming process may include a polysilicon film forming process and an impurity implantation process. A metal film and / or a silicide film may be further formed on the second conductive film 250. A gate mask pattern 260 is formed on the second conductive layer 250. The gate mask pattern 260 may be formed by a lithography process.

7 and 8, the second conductive layer 250, the dielectric layer 240, and the first conductive layer 230 are sequentially etched using the gate mask pattern 260. Therefore, the selection line and the floating gate 235 including the first conductive pattern 233, the first dielectric pattern 243, and the second conductive pattern 253, the second dielectric pattern 245, and the control gate 255 are included. A word line comprising a is formed. In this case, the selection line is formed on the first region 221 and the second region 222. The word line is spaced apart from the first region 221 and extends in the same direction as the selection line. The gate mask pattern 260 is removed.

Impurity regions are formed in the substrate 200. For example, the impurity region may be formed by ion implantation of N-type impurities. The impurity regions may include a source region 270, a floating region 272, and a drain region 274. The floating region 272 is formed between the selection line and the word line, and the source region 270 and the drain region 274 are formed in the opposite direction in which the floating region 272 is formed.

9 to 13, a method of manufacturing an ypyrom device according to another embodiment of the present invention will be described. Hereinafter, the same contents as those mentioned above will be briefly described.

9, a substrate 300 is provided. For example, the substrate 300 may include a P-type well. The substrate 300 includes an active region defined by an isolation region (not shown). The first insulating layer 302 is formed on the substrate 300. A mask pattern 305 is formed on the first insulating layer 302.

9 and 10, an insulating pattern 304 is formed by etching the first insulating layer 302 using the mask pattern 305. Thereafter, the mask pattern 305 is removed.

Referring to FIG. 11, a gate insulating layer 320 is formed by oxidizing a surface of the substrate 300 including the insulating pattern 304. Due to the insulating pattern 304, the gate insulating layer 320 may include first and second regions 321 and 322 having different thicknesses. The first region 321 is an oxidized region in which the insulating pattern 304 is formed, and the second region 322 is an oxidized region in the other region. Therefore, the first region 321 may be formed thicker than the second region 322.

12, a first conductive layer 330, a dielectric layer 340, and a second conductive layer 350 are sequentially formed on the gate insulating layer 320. A gate mask pattern 360 is formed on the second conductive layer 350. The layers 330, 340, and 350 may be formed along the profile of the gate insulating layer 320.

12 and 13, the second conductive layer 350, the dielectric layer 340, and the first conductive layer 330 are sequentially etched using the gate mask pattern 360. Accordingly, the selection line and the floating gate 335 including the first conductive pattern 333, the first dielectric pattern 343, and the second conductive pattern 353, the second dielectric pattern 345, and the control gate 355 may be formed. A word line comprising a is formed. In this case, the selection line and the word line may be formed on the first region 321 and the second region 322. Facing portions of the selection line and the word line may extend over the first region 321. Thus, opposite portions of the select line and the word lines facing each other extend on the second region 322. The gate mask pattern 360 is removed.

A source region 370, a floating region 372, and a drain region 374 are formed in the substrate 300. The floating region 372 is formed between the selection line and the word line, and the source region 370 and the drain region 374 are formed in the opposite direction in which the floating region 372 is formed.

The nonvolatile memory device according to the embodiment of the present invention includes a gate insulating film having a different thickness for each region. In addition, the method of manufacturing a nonvolatile memory device according to an embodiment of the present invention may provide a gate insulating film having different thicknesses by forming an insulating pattern on a substrate and then forming a gate insulating film. As a result, the device may obtain the same effect as that between the lines because of the gate insulating film having a partly thick thickness even if the gap between the select line and the word line is kept narrow. Accordingly, embodiments of the present invention can provide an ypyrom device having excellent reliability by preventing electrons from being injected into a floating gate of an unselected memory transistor.

Claims (9)

Defining an active region in the substrate; Forming a gate insulating pattern on the substrate; Forming a gate insulating film including the gate insulating pattern along the surface of the substrate; And Forming a select line partially overlapping the gate insulating pattern and a word line spaced apart from the select line on the gate insulating layer. The method of claim 1, The word line may be formed to be spaced apart from the insulating pattern. The method of claim 1, And the word line is formed to overlap a part of the insulating pattern. The method of claim 1, And the selection line and the word line extend in a direction crossing the active region. The method of claim 1, Forming the gate insulating pattern may include: Forming a first insulating film on the substrate; Forming a mask pattern on the first insulating film; And And etching the first insulating layer by using the mask pattern. The method of claim 1, Forming the gate insulating film is: And oxidizing the gate insulating pattern and the substrate, wherein the gate insulating layer is adjacent to the first region and has a first thickness having a first thickness on the substrate on which the gate insulating pattern is formed. And a second area having a thin second thickness. Board; A selection line extending on the substrate; A word line extending apart from the selection line; And A gate insulating film interposed between the selection line and the word line and the substrate; The gate insulating layer includes a first region and a second region that is thinner than the first region, wherein the first region overlaps a portion of the selection line, the portion is an edge of the selection line, and the edge is the word. Non-volatile memory device in the line direction. The method of claim 7, wherein And the word line is spaced apart from the first region. The method of claim 7, wherein And wherein the first region overlaps a portion of the word line, the portion is an edge of the word line, and the edge is in the direction of the selection line.

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