JP2012109390A - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize variation in characteristics of two storage elements facing each other due to a gate length of the control gate.SOLUTION: The nonvolatile semiconductor memory device (1) is configured as follows. A first nonvolatile memory cell (1a) includes a first channel region (11a), a first floating gate (5a), and a first control gate (6a). A second nonvolatile memory cell (1b) includes a second channel region (11b), a second floating gate (5b), and a second control gate (6b). The first channel region (11a) includes a first floating gate side channel region (13a) and a first control gate side channel region (12a), and the first control gate side channel region (12a) includes a high concentration pocket region (10) having high impurity concentration.

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device, and more particularly to a split gate nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device.

  2. Description of the Related Art A semiconductor memory device (hereinafter referred to as a non-volatile semiconductor memory device) that can rewrite data and can continue to hold written data even when power supply is interrupted is known. The nonvolatile semiconductor memory device includes a plurality of memory elements. 2. Description of the Related Art As a structure of a storage element of a nonvolatile semiconductor memory device that has been widely used, a structure including a floating gate transistor that stores data and a selection transistor that operates when data of the storage element is read is known. . The floating gate transistor includes a floating gate for accumulating charges and a control gate to which an operating voltage is applied. The selection transistor has a selection gate.

  In response to the progress of information processing apparatuses, non-volatile semiconductor memory devices have been required to operate at higher speeds and have finer structures. In response to such demands, non-volatile semiconductor memory devices having a memory element having a structure in which a floating gate transistor and a select transistor are integrally formed have become widespread. The storage element includes a control gate that covers the upper portion of the floating gate and is arranged next to the floating gate, and the control gate provides a function of a selection gate. Further, there is known a nonvolatile semiconductor memory device (hereinafter, referred to as a split gate nonvolatile semiconductor memory device) having an integrated structure as described above and having a structure in which adjacent memory elements are symmetrically arranged. ing.

  In the manufacturing process of a split gate type nonvolatile semiconductor memory device that is currently widely used, the control gate is formed by patterning using a lithography technique. The gate length of each of the control gates of the two opposing storage elements is determined by alignment of the control gate with respect to the floating gate in lithography. When misalignment occurs in the alignment with respect to the floating gate, the gate lengths of the control gates of the two opposing storage elements may be different.

  A technique for reducing variation in effective gate length of a control gate in a split gate nonvolatile semiconductor memory device is known (see, for example, Patent Document 1). FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile semiconductor memory device 100 described in Patent Document 1. As shown in FIG. 1, the nonvolatile semiconductor memory device 100 includes a first memory cell 100a and a first memory cell 100b. The first memory cell 100a is connected to the floating gate 104a via the floating gate 104a formed on the tunnel oxide film 103 on the silicon substrate 101, the selective oxide film 105a, and the tunnel oxide film 103 covering the floating gate 104a. A control gate 106a formed so as to overlap, and a source / drain region 107 formed on the substrate surface layer so as to be adjacent to the floating gate 104a control gate 106a are provided.

  Similarly, the first memory cell 100b includes a floating gate 104b, a selective oxide film 105b, and a control gate 106b formed to overlap the floating gate 104b via a tunnel oxide film 103 covering the floating gate 104b. And a source / drain region 107 formed on the surface layer of the substrate so as to be adjacent to the floating gate 104b and the control gate 106b.

  In the technique described in Patent Document 1, in the nonvolatile semiconductor memory device 100, when adjacent floating gate transistor portions (the first memory cell 100 a and the first memory cell 100 b) share the source / drain region 107, The position of the drain region 107 is determined by the same process as the mask alignment process of the floating gates of the adjacent floating gate transistor parts (the first memory cell 100a and the first memory cell 100b). The non-volatile semiconductor memory device 100 is formed such that effective gate length (effective gate length La, effective gate length Lb) variation is suppressed, and effective gate length La = effective gate length Lb.

  Patent Document 1 describes a manufacturing process for manufacturing the nonvolatile semiconductor memory device 100. In the manufacturing process, a gate oxide film and a floating gate polysilicon film are formed on the silicon substrate 101, and a silicon nitride film having a plurality of first openings is formed on the floating gate polysilicon film. Using this silicon nitride film as a mask, the floating gate polysilicon film is selectively oxidized to form a selective oxide film on the region where the floating gate of the adjacent floating gate transistor portion is formed. At this time, a dummy selective oxide film is formed on the region where the drain region is formed.

  Next, the selective oxide film is covered with a resist film, and the dummy selective oxide film is removed to form a second opening. Thereafter, using the resist film and the silicon nitride film as a mask, the floating gate polysilicon film under the second opening is removed by anisotropic etching to form a third opening on the gate oxide film.

  Subsequently, N-type impurities (for example, phosphorus ions and arsenic ions) are implanted into the surface layer of the silicon substrate through the third opening to form source / drain regions 107. Further, the resist film and the silicon nitride film are removed, and then a new polysilicon film is formed on the entire surface including the third opening. Subsequently, by removing the new polysilicon film and the floating gate polysilicon film by anisotropic etching, the selective oxide film 105 acts as a mask, and the floating gate 104 is formed under the selective oxide film 105. .

  Then, after forming a tunnel oxide film 103 so as to cover the floating gate 104 and the selective oxide film 105, a control gate 106 having a region overlapping with the floating gate 104 through the tunnel oxide film 103 is formed.

JP 2000-228511 A

  In the technique described in Patent Document 1, patterning for determining the position of the floating gate and patterning for determining the position of the source diffusion layer are performed in the same lithography process. Specifically, the position of the drain diffusion layer is determined by lithography, and after forming the drain diffusion layer, the control gate is patterned. As a result, the effective gate length (La, Lb) is determined regardless of the alignment accuracy, so that the characteristic variation of the left and right transistors (first memory cell 100a, first memory cell 100b) is reduced.

In the technique described in Patent Document 1, a considerable number of processes are added as compared with the manufacturing process in which the source diffusion layer and the drain diffusion layer are formed after the control gate is formed. Specifically, for example, a step of protecting the selective oxide film on the floating gate polysilicon film, a step of etching the polysilicon and oxide film on the drain diffusion layer after removing the dummy selective oxide film, etc. Have been added. In addition, a step of protecting the drain diffusion layer is added when etching for forming the floating gate is performed.
The problem to be solved by the present invention is to provide a technique for reducing variations in characteristics of memory elements due to the gate lengths of the control gates of two opposing memory elements while suppressing an increase in the number of steps in the manufacturing process. It is in.

  [Means for Solving the Problems] will be described below using the numbers used in [DETAILED DESCRIPTION]. These numbers are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

In order to solve the above problems, the first nonvolatile memory cell (1a) and the first source / drain region (3a) provided on the substrate (2) are shared with the first nonvolatile memory cell (1a). The nonvolatile semiconductor memory device (1) including the second nonvolatile memory cell (1b) disposed so as to face the first nonvolatile memory cell (1a) is configured as follows.
Here, the first non-volatile memory cell (1a) includes a first channel corresponding between the second source / drain region (4a) and the first source / drain region (3a) provided on the substrate (2). A region (11a), a first floating gate (5a) provided on the first channel region (11a) via the first gate insulating film (7a), and a first tunnel insulating film (8a) And a first control gate (6a) provided next to the first floating gate (5a).
The second nonvolatile memory cell (1b) includes a second channel region corresponding to a region between the third source / drain region (4b) and the first source / drain region (3a) provided on the substrate (2). (11b), a second floating gate (5b) provided on the second channel region (11b) through the second gate insulating film (7b), and a second tunnel insulating film (8b) through the second tunnel insulating film (8b). 2 and a second control gate (6b) provided next to the floating gate (5b).
Here, the first channel region (11a) corresponds to the first floating gate side channel region (13a) below the first floating gate (5a) and the first control gate (6a), and the first floating gate side (11a) corresponds to the first floating gate (5a). It is preferable to provide a first control gate side channel region (12a) between the gate side channel region (13a) and the first source / drain region (3a). The first control gate side channel region (12a) is connected to the first source / drain region (3a) and has a higher concentration pocket region (10) having a higher impurity concentration than the first floating gate side channel region (13a). ).

In addition, the nonvolatile semiconductor memory device is preferably manufactured by the following manufacturing method, for example. In the manufacturing method, a floating gate forming step for forming a floating gate, a control gate forming step for forming a control gate partially covering the floating gate, and a pocket region for forming a high concentration pocket region in a substrate under the control gate And forming step. Here, the control gate formation step is
[A] measuring the gate length of the control gate;
[B] A step of specifying a control gate having a gate length shorter than the ideal gate length determined at the time of design as a correction target control gate based on a measurement result obtained by executing the measuring step. Preferably it is. And the pocket region formation step
[C] It is preferable to provide a step of ion-implanting impurities under the control gate to be corrected.

  To briefly explain the effects obtained by typical inventions among inventions disclosed in the present application, it is caused by the gate lengths of the control gates of two opposing memory elements while suppressing an increase in man-hours in the manufacturing process. Variations in the characteristics of the memory elements can be suppressed.

FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile semiconductor memory device 100 described in Patent Document 1. FIG. 2 is a cross-sectional view illustrating the configuration of the nonvolatile semiconductor memory device 1 of this embodiment. FIG. 3 is a graph illustrating the relationship between the gate length and the threshold voltage. FIG. 4 is a graph illustrating the relationship between the pocket injection amount and the threshold voltage. FIG. 5 is a graph illustrating the results of actual measurement of the pocket injection amount and the threshold voltage as a reference. FIG. 6 is a cross-sectional view illustrating the first stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 7 is a cross-sectional view illustrating the second stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 8 is a cross-sectional view illustrating a third stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 9 is a cross-sectional view illustrating the fourth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 10 is a cross-sectional view illustrating the fifth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 11 is a cross-sectional view illustrating the sixth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 12 is a cross-sectional view illustrating the seventh stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 13 is a cross-sectional view illustrating the eighth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 14 is a cross-sectional view illustrating the ninth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 15 is a cross-sectional view illustrating the tenth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 16 is a cross-sectional view illustrating the eleventh stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 17 is a cross-sectional view illustrating the twelfth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 18 is a cross-sectional view illustrating the thirteenth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. FIG. 19 is a cross-sectional view illustrating the fourteenth stage of the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. FIG. 2 is a cross-sectional view illustrating the configuration of the nonvolatile semiconductor memory device 1 of this embodiment. The nonvolatile semiconductor memory device 1 of the present embodiment includes a first nonvolatile memory cell 1a and a second nonvolatile memory cell 1b, which sandwich a first source / drain region 3 provided on a substrate 2. It arrange | positions so that it may oppose. The first nonvolatile memory cell 1a and the second nonvolatile memory cell 1b in FIG. 2 have a configuration when misalignment with respect to the floating gate occurs in the formation stage of the control gate in the manufacturing process of the nonvolatile semiconductor memory device 1. Illustrated.

  As shown in FIG. 2, the first nonvolatile memory cell 1a includes a first source / drain region 3, a second source / drain region 4a, a first floating gate 5a, and a first control gate 6a. And a high-concentration pocket region 10. The first floating gate 5a is provided on the substrate 2 via the first floating gate insulating film 7a. A first selective oxide film 9a is provided on the first floating gate 5a.

  The first control gate 6a is disposed next to the first floating gate 5a via the first tunnel insulating film 8a. The first tunnel insulating film 8a covers the first tunnel insulating film 8a and the first selective oxide film 9a. The first control gate 6a is provided so as to cover a part of the first floating gate 5a with the first tunnel insulating film 8a and the first selective oxide film 9a interposed therebetween. Further, the first tunnel insulating film 8 a is provided between the first control gate 6 a and the substrate 2. The first control gate 6a provides the function of a selection transistor by using the first tunnel insulating film 8a as a gate insulating film.

  The first nonvolatile memory cell 1a includes a first channel region 11a having a first channel length ch1 between the first source / drain region 3 and the second source / drain region 4a. The first channel region 11a includes a first control gate side channel region 12a, a first floating gate side channel region 13a, and a high concentration pocket region 10. The first control gate side channel region 12a is a region corresponding to the first control gate length CGL1 of the first control gate 6a. The first floating gate side channel region 13a is a region corresponding to the effective gate length of the first floating gate 5a.

  Similarly, the second nonvolatile memory cell 1b includes a first source / drain region 3, a third source / drain region 4b, a second floating gate 5b, and a second control gate 6b. The second floating gate 5b is provided on the substrate 2 via the second floating gate insulating film 7b. A second selective oxide film 9b is provided on the second floating gate 5b.

  The second control gate 6b is disposed next to the second floating gate 5b via the second tunnel insulating film 8b. The second tunnel insulating film 8b covers the second selective oxide film 9b. The second control gate 6b is provided so as to cover a part of the second floating gate 5b with the second tunnel insulating film 8b and the second selective oxide film 9b interposed therebetween. Further, the second tunnel insulating film 8 b is provided between the second control gate 6 b and the substrate 2. The second control gate 6b provides the function of a selection transistor by using the second tunnel insulating film 8b as a gate insulating film.

  The second nonvolatile memory cell 1b includes a second channel region 11b having a second channel length ch2 between the first source / drain region 3 and the third source / drain region 4b. The second channel region 11b includes a second control gate side channel region 12b and a second floating gate side channel region 13b. The second control gate side channel region 12b is a region corresponding to the second control gate length CGL2 of the second control gate 6b. The second floating gate side channel region 13b is a region corresponding to the effective gate length of the second floating gate 5b.

  The first control gate length CGL1 is an effective gate length when the first control gate 6a acts as the gate of the selection transistor. The first control gate 6a of the present embodiment is formed with a first control gate length CGL1 that is shorter than the reference control gate length CGL by a gate length deviation amount ΔL due to misalignment at the time of formation of the control gate. . The second control gate length CGL2 is an effective gate length when the second control gate 6b acts as the gate of the selection transistor. The second control gate 6b of the present embodiment is formed with a second control gate length CGL2 that is longer than the reference control gate length CGL by a gate length deviation amount ΔL due to misalignment during formation of the control gate. .

  Here, referring to FIG. 2, in the nonvolatile semiconductor memory device 1 of the present embodiment, a high concentration pocket region 10 is provided in the first control gate side channel region 12a of the first nonvolatile memory cell 1a. . The second nonvolatile memory cell 1 b is configured without having a region corresponding to the high concentration pocket region 10. The high concentration pocket region 10 is provided on the substrate 2 under the first control gate 6 a so as to be in contact with the first source / drain region 3.

  As described above, the first control gate length CGL1 of the first control gate 6a is shorter than the reference control gate length CGL. The reference control gate length CGL is set to the shortest length within a range where the influence of the short channel effect is small. Therefore, the threshold voltage becomes small at the first control gate length CGL1 shorter than the reference control gate length CGL, like the first control gate 6a. By providing the high concentration pocket region 10, the threshold voltage of the first nonvolatile memory cell 1a can be made the same as the threshold voltage when the gate length of the first control gate 6a is the reference control gate length CGL.

  Here, the operation of the nonvolatile semiconductor memory device 1 will be described. Selection of the first non-volatile memory cell 1a or the second non-volatile memory cell 1b is performed by selecting one control gate and one bit line connected to a drain diffusion layer not shown. . At the time of writing, a positive voltage (for example, 4.5 V) is applied to the source and a positive voltage (for example, 8.5 V) is applied to the control gate, and the drain is grounded. At this time, a part of the electrons flowing from the drain to the source is accelerated in the channel below the control gate, and a part is injected into the floating gate to perform writing. At the time of erasing, a positive voltage (for example, 11 V) is applied to the control gate, and the others are set to GND so that electrons in the floating gate are extracted to the control gate.

  At the time of reading, the source is grounded, and a positive voltage (for example, 2V) is applied to the control gate, and a positive voltage (for example, 1V) is applied to the drain, whereby a current flows between the drain and the source. At this time, the current is small in a state where electrons are accumulated in the floating gate (write state), and the current is large in a state where electrons are not accumulated or almost no electrons are accumulated (erasure state). Using this characteristic, data stored in the first nonvolatile memory cell 1a or the second nonvolatile memory cell 1b is read. If the characteristics of the transistors having the left and right control gates as gate electrodes are different, there will be a difference in characteristics between writing and reading. The nonvolatile semiconductor memory device 1 of this embodiment includes a high concentration pocket region 10 corresponding to the misalignment amount of the control gate. Even when the control gate 6 having an asymmetric gate length is formed by the action of the high-concentration pocket region 10, it is possible to suppress variations in characteristics of transistors having the left and right control gates as gate electrodes.

  FIG. 3 shows the effective gate length when the control gate 6 (first control gate 6a, second control gate 6b) acts as the gate of the selection transistor in the nonvolatile semiconductor memory device 1 of the present embodiment, It is a graph which illustrates the relationship with the threshold voltage of a selection transistor. As shown in FIG. 3, the reference control gate length CGL is set to the shortest length within a range where the influence of the short channel effect is small. When the difference between the reference control gate length CGL and the first control gate length CGL1 is the gate length deviation amount ΔL, the threshold voltage decreases from the reference threshold Vt1 by the threshold variation amount ΔVt to become the post-fluctuation threshold voltage Vt2.

  FIG. 4 shows the relationship between the implantation amount and the threshold voltage when pocket implantation is performed under the control gate 6 (first control gate 6a, second control gate 6b) in the nonvolatile semiconductor memory device 1 of this embodiment. It is a graph to illustrate. As shown in FIG. 4, when pocket implantation is performed, the threshold voltage can be increased depending on the implantation amount when the implantation amount of impurities is increased. By measuring the first control gate length CGL1 described above, a difference gate length deviation amount ΔL from the reference control gate length CGL is calculated. By specifying the threshold fluctuation amount ΔVt and the post-fluctuation threshold voltage Vt2 based on the gate length deviation amount ΔL, the impurity implantation amount of the high-concentration pocket region 10 can be determined based on the graph of FIG.

  FIG. 5 is a graph exemplarily showing a result of actual measurement of the pocket injection amount and the threshold voltage when the gate length of the control gate 6 is fixed to a predetermined length. The graph plots threshold voltages when the gate length is fixed and the pocket injection amount is changed in a plurality of stages. Referring to FIG. 5, it is shown that when pocket implantation is performed, the threshold voltage increases linearly in accordance with the amount of impurity implantation. Note that the correlation illustrated in FIG. 5 is for facilitating understanding of the present embodiment, and is not limited to the case where the correlation between the pocket injection amount and the threshold voltage is linear.

  Hereinafter, the manufacturing process of the nonvolatile semiconductor memory device 1 of the present embodiment will be described. In the description of the manufacturing process described below, when it is not necessary to distinguish between the first nonvolatile memory cell 1a and the second nonvolatile memory cell 1b, the branch codes “a” and “b” of the reference symbols are used. When the first nonvolatile memory cell 1a and the second nonvolatile memory cell 1b are required to be distinguished, branch codes “a” and “b” are added to the reference symbols for explanation. .

  FIG. 6 is a cross-sectional view illustrating the configuration of the first-stage semiconductor material in the manufacturing process of the nonvolatile semiconductor memory device 1 of this embodiment. In the first step in the manufacturing process of the nonvolatile semiconductor memory device 1, an oxide film 21 and a polysilicon film 22 are sequentially formed on the substrate 2, and a nitride film 23 is formed so as to cover the polysilicon film 22. The shape of the oxide film 21 is changed into a floating gate insulating film 7 by changing the shape in a later process. The shape of the polysilicon film 22 is changed into a floating gate 5 in a later process.

  FIG. 7 is a cross-sectional view illustrating a second stage in the manufacturing process of the nonvolatile semiconductor memory device 1 of this embodiment. In the second stage, a resist 24 having an opening in a region where the floating gate 5 is to be formed is formed on the nitride film 23. Using the resist 24, the nitride film 23 is selectively removed by anisotropic etching to form an opening 25 in the nitride film 23.

  FIG. 8 is a cross-sectional view illustrating a third stage in the manufacturing process of the nonvolatile semiconductor memory device 1 of this embodiment. In the third stage, the resist 24 is removed. As shown in FIG. 8, the semiconductor material in the third stage is in a state where a part of the polysilicon film 22 is exposed through the opening 25 formed in the nitride film 23. The surface of the nitride film 23 covered with the resist 24 is exposed.

  FIG. 9 is a cross-sectional view illustrating a fourth stage in the manufacturing process of the nonvolatile semiconductor memory device 1 of this embodiment. In the fourth step, the selective oxidation film 9 is formed by selectively oxidizing the polysilicon film 22 using the nitride film 23 having the opening as a mask.

  FIG. 10 is a cross-sectional view illustrating a fifth stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the fifth stage, the nitride film 23 is removed. As shown in FIG. 10, the semiconductor material in the fifth stage has a selective oxide film 9 formed in a region of the polysilicon film 22 where the floating gate 5 is formed.

  FIG. 11 is a cross-sectional view illustrating a sixth stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the sixth stage, the polysilicon film 22 is selectively removed by anisotropic etching using the selective oxide film 9 as a mask. Thereby, the floating gate 5 is formed. Thereafter, the selective oxide film 9 and the floating gate 5 are used as a mask, and the oxide film 21 is selectively removed by anisotropic etching. Thereby, the floating gate insulating film 7 is formed in a self-aligning manner.

  FIG. 12 is a cross-sectional view illustrating a seventh step in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the seventh stage, an oxide film 26 is formed so as to cover the entire surface of the semiconductor material in the manufacturing process. Thereafter, a polysilicon film 27 is formed on the oxide film 26. The oxide film 26 is processed into the tunnel insulating film 8 by changing the shape in a later process. The shape of the polysilicon film 27 is changed in a later process to become the control gate 6. As shown in FIG. 12, the semiconductor material in the seventh stage is selected from the surface of the substrate 2 where the oxide film 21 is exposed, the side surface of the floating gate insulating film 7, the side surface of the floating gate 5, The upper surface of the oxide film 9 is covered. The polysilicon film 27 is formed with a film thickness that can provide a function as the control gate 6 when the shape is changed in a later process.

  FIG. 13 is a cross-sectional view illustrating the eighth stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the eighth step, a resist 28 is formed to cover the region where the control gate 6 is to be formed. When the resist 28 is disposed at an ideal position, the control gate 6 formed in a later process is also formed in an ideal shape. The description of the manufacturing process described below corresponds to the case where the resist 28 is shifted from the region where the first nonvolatile memory cell 1a is formed.

  FIG. 14 is a cross-sectional view illustrating the ninth stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the ninth stage, the polysilicon film 27 is selectively removed by anisotropic etching using the resist 28 as a mask. Thereby, the polysilicon film 27 under the resist 28 is processed into the shape of the control gate 6.

  FIG. 15 is a cross-sectional view illustrating the tenth stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the tenth stage, the resist 28 is removed. As shown in FIG. 15, the semiconductor material in the tenth stage is formed such that the opposing control gates 6 have different gate lengths. In the manufacturing process of the nonvolatile semiconductor memory device 1 of this embodiment, after removing the resist 28, the gate length of the control gate 6 is measured. As a result of the measurement, when the control gate 6 shorter than the above-mentioned reference control gate length CGL is formed, the steps of FIGS. 16 to 18 described later are performed. As a result of the measurement, when the control gate 6 shorter than the reference control gate length CGL is not formed, the steps of FIGS. 16 to 18 described later are omitted. In the tenth stage, impurity implantation for forming LDD (Lightly Doped Drain) may be performed.

  FIG. 16 is a cross-sectional view illustrating an eleventh stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the eleventh stage, a resist 29 is formed to cover the upper portion of the floating gate 5 and a region where the source / drain region 4 is formed in a later process. As shown in FIG. 16, the semiconductor material in the eleventh stage is formed with a resist 29 having an opening in a region where the first source / drain region 3 is formed in a later process. As a result, the surface of the tunnel insulating film 8 between the opposing control gates 6 is exposed, and the tunnel insulating film 8 in other regions is protected by the resist 29.

  FIG. 17 is a cross-sectional view illustrating a twelfth stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the twelfth stage, an impurity for forming the high concentration pocket region 10 is implanted. At this time, when the control gate 6 shorter than the prescribed reference control gate length CGL is formed based on the measurement result in the tenth stage, the impurity enters only under the control gate 6. Impurity implantation is performed at a predetermined angle. Since only an impurity (for example, boron) is additionally implanted under the first control gate 6a only from one direction at an angle, the additional number of steps can be realized by a minimum of one step.

  The dose amount and the implantation energy at that time are determined based on values obtained from the gate length-threshold voltage characteristic graph illustrated in FIG. 3 and the pocket implantation amount-threshold voltage characteristic graph illustrated in FIG. Specifically, the threshold fluctuation amount ΔVt is defined as the gate length dimension is shortened and Vt is lowered. In order to compensate for the threshold fluctuation amount ΔVt, the injection amount is determined from the relationship diagram shown in FIG. By performing the additional implantation, it is possible to correct the amount of decrease in the gate length and Vt, and to reduce the variation in the left and right selection transistors.

  FIG. 18 is a cross-sectional view illustrating a thirteenth stage in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the thirteenth stage, the resist 29 is removed. As shown in FIG. 18, the semiconductor material in the thirteenth stage is formed with an impurity implantation region that becomes the high concentration pocket region 10 in a later process.

  FIG. 19 is a cross-sectional view illustrating the 14th step in the manufacturing process of the nonvolatile semiconductor memory device 1 according to this embodiment. In the fourteenth stage, impurities are implanted into the substrate 2 to form the first source / drain region 3 and the source / drain region 4. As shown in FIG. 19, the semiconductor material in the fourteenth stage is provided with the high concentration pocket region 10 only under the control gate 6 shorter than the prescribed reference control gate length CGL. By the action of 10, the threshold voltages of the first nonvolatile memory cell 1a and the second nonvolatile memory cell 1b facing each other are set to the same voltage. Note that the control gate 6 of the second nonvolatile memory cell 1b has a gate length longer than the reference control gate length CGL. Referring to the graph of the gate length-threshold voltage characteristic illustrated in FIG. 3, the threshold fluctuation is small when the gate length of the control gate 6 is longer than the reference control gate length CGL. Therefore, by forming the high-concentration pocket region 10 in the first nonvolatile memory cell 1a as in the present embodiment, variation in characteristics between the first nonvolatile memory cell 1a and the second nonvolatile memory cell 1b is reduced. It becomes possible.

  The embodiment of the present invention has been specifically described above. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 1 ... Nonvolatile semiconductor memory device 1a ... 1st non-volatile memory cell 1b ... 2nd non-volatile memory cell 2 ... Substrate 3 ... 1st source / drain region 4 ... Source / drain region 4a ... 2nd source / drain region 4b ... Third source / drain region 5 ... floating gate 5a ... first floating gate 5b ... second floating gate 6 ... control gate 6a ... first control gate 6b ... second control gate 7 ... floating gate insulating film 7a ... first floating gate Insulating film 7b ... second floating gate insulating film 8 ... tunnel insulating film 8a ... first tunnel insulating film 8b ... second tunnel insulating film 9 ... selective oxide film 9a ... first selective oxide film 9b ... second selective oxide film 10 ... High-concentration pocket region 11a ... first channel region 11b ... second channel region 12a ... 1 control gate side channel region 12b ... second control gate side channel region 13a ... first floating gate side channel region 13b ... second floating gate side channel region 21 ... oxide film 22 ... polysilicon film 23 ... nitride film 24 ... resist 25 ... opening 26 ... oxide film 27 ... polysilicon film 28 ... resist 29 ... resist ch1 ... first channel length ch2 ... second channel length CGL ... reference control gate length CGL1 ... first control gate length CGL2 ... second control gate length Vt1 ... reference threshold value Vt2 ... post-change threshold voltage ΔVt ... threshold change amount ΔL ... gate length deviation amount 100 ... nonvolatile semiconductor memory device 100a ... first memory cell 100b ... first memory cell 101 ... silicon substrate 103 ... tunnel oxide film 104a ... Floating game DOO 104b ... floating gates 105a ... selective oxide film 105b ... selective oxide film 106a ... control gate 106b ... control gate 107 ... source-drain region La ... effective gate length Lb ... effective gate length

Claims (10)

A first non-volatile memory cell;
A first source / drain region provided in a substrate is shared with the first nonvolatile memory cell, and a second nonvolatile memory cell is disposed so as to face the first nonvolatile memory cell;
The first nonvolatile memory cell is
A first channel region corresponding between the second source / drain region and the first source / drain region provided on the substrate;
A first floating gate provided on the first channel region via a first gate insulating film;
A first control gate provided next to the first floating gate via a first tunnel insulating film,
The second nonvolatile memory cell is
A second channel region corresponding between the third source / drain region and the first source / drain region provided in the substrate;
A second floating gate provided on the second channel region via a second gate insulating film;
A second control gate provided next to the second floating gate through a second tunnel insulating film,
The first channel region is
A first floating gate side channel region under the first floating gate;
A first control gate side channel region between the first floating gate side channel region and the first source / drain region, corresponding to the bottom of the first control gate;
The first control gate side channel region is
A nonvolatile semiconductor memory device including a high concentration pocket region connected to the first source / drain region and having an impurity concentration higher than that of the first floating gate side channel region. The nonvolatile semiconductor memory device according to claim 1,
The first control gate is
A first gate length shorter than a gate length of the second control gate;
The high concentration pocket region is
A non-volatile semiconductor memory device having a concentration of impurities such that a threshold voltage of the first non-volatile memory cell determined depending on the first gate length is the same as a threshold voltage of the second non-volatile memory cell. The nonvolatile semiconductor memory device according to claim 1 or 2,
The first control gate side channel region is
A nonvolatile semiconductor memory device including a normal concentration region which is provided between the high concentration pocket region and the first floating gate side channel region and has the same impurity concentration as the first floating gate side channel region. The nonvolatile semiconductor memory device according to claim 2 or 3,
The first control gate is
A nonvolatile semiconductor memory device, which is provided opposite to the second control gate across the first source / drain region and has a gate length shorter than an ideal control gate length determined at the time of design as the first gate length. The nonvolatile semiconductor memory device according to any one of claims 1 to 4,
The second channel region is
A second floating gate side channel region under the second floating gate;
A second control gate side channel region between the second floating gate side channel region and the first source / drain region, corresponding to under the second control gate;
Each of the second floating gate side channel region and the second control gate side channel region has the same impurity concentration as the first floating gate side channel region. The nonvolatile semiconductor memory device according to any one of claims 1 to 5,
The first control gate is
Provided on the substrate through a first control gate insulating film provided continuously from the first tunnel insulating film;
Covering a part of the first floating gate through the first tunnel insulating film covering the first floating gate;
The second control gate is
Provided on the substrate through a second control gate insulating film provided continuously from the second tunnel insulating film;
A non-volatile semiconductor memory device that covers a part of the second floating gate through the second tunnel insulating film that covers the second floating gate. A floating gate forming step for forming a floating gate;
A control gate forming step of forming a control gate partially covering the floating gate;
A pocket region forming step for forming a high concentration pocket region in the substrate under the control gate,
The control gate forming step includes
(A) measuring a gate length of the control gate;
(B) specifying a control gate having a gate length shorter than an ideal gate length determined at the time of design as a correction target control gate based on a measurement result obtained by executing the measuring step. ,
The pocket region forming step includes
(C) A method for manufacturing a nonvolatile semiconductor memory device, comprising: ion-implanting impurities under the control target control gate. The method for manufacturing a nonvolatile semiconductor memory device according to claim 7,
The control gate forming step includes
(D) forming an insulating film covering the floating gate and the substrate;
(E) forming a polysilicon film on the insulating film;
(F) etching the polysilicon film to form a pattern of the control gate;
With
The step (c) includes:
A method for manufacturing a nonvolatile semiconductor memory device, comprising the step of ion-implanting the impurities obliquely into the surface of the substrate exposed by removing the polysilicon film by the etching in the step (f). The method for manufacturing a nonvolatile semiconductor memory device according to claim 8,
The step (f)
Forming a resist having an opening extending along the first direction on the polysilicon film;
Removing the polysilicon film exposed by the opening of the resist, and
The step (c) includes:
A method for manufacturing a non-volatile semiconductor memory device, comprising the step of ion-implanting the impurities obliquely along a second direction perpendicular to the first direction. The method for manufacturing a nonvolatile semiconductor memory device according to any one of claims 7 to 9, further comprising:
A determination step for determining whether to execute the pocket region forming step;
The control gate forming step further includes:
(G) based on a measurement result obtained by executing the measuring step, the step of outputting correction target non-existence information indicating that the correction target control gate is not formed,
The determination step includes
A method for manufacturing a nonvolatile semiconductor memory device, wherein execution of the pocket region forming step is skipped based on the correction target absence information.

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