KR20080088973A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20080088973A
KR20080088973A KR1020070031909A KR20070031909A KR20080088973A KR 20080088973 A KR20080088973 A KR 20080088973A KR 1020070031909 A KR1020070031909 A KR 1020070031909A KR 20070031909 A KR20070031909 A KR 20070031909A KR 20080088973 A KR20080088973 A KR 20080088973A
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South Korea
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film
metal
amorphous silicon
gate
semiconductor device
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KR1020070031909A
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Korean (ko)
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박창수
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주식회사 하이닉스반도체
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Priority to KR1020070031909A priority Critical patent/KR20080088973A/en
Publication of KR20080088973A publication Critical patent/KR20080088973A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The method of manufacturing a semiconductor device according to the present invention includes forming an amorphous silicon film on a semiconductor substrate on which a polysilicon gate is formed, exposing the amorphous silicon film to a metal source gas, and exposing the amorphous silicon film on a surface of the amorphous silicon film through a silicon reduction reaction. Forming a metal film, heat treating the amorphous silicon film and the metal film to form a metal silicide film through mutual reaction, removing an unreacted metal film portion during the heat treatment, and heat treating the metal silicide film. Steps.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a perspective view showing the type of transistor according to the prior art.

2 and 3 is a photograph showing a conventional problem.

4A to 4B, 5A to 5B to 6A to 6B, and 7A to 7B are cross-sectional views and perspective views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

8 is a photograph showing the effect of the present invention.

Explanation of symbols on the main parts of the drawings

400: semiconductor substrate 402: device isolation film

404: pin pattern 406: gate insulating film

408: gate conductive film 410: mask pattern

412 spacer 414 metal silicide film

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving step coverage.

As is well known, a gate of a MOSFET device has usually used a polysilicon film as the conductive film. This is because the polysilicon film satisfies physical properties required as a gate such as high melting point, ease of thin film formation, ease of line pattern, stability to an oxidizing atmosphere, and flat surface formation. In addition, in the MOSFET, the polysilicon gate contains a dopant such as phosphorus (P), arsenic (As), and boron (B), thereby realizing a low resistance value.

In addition, CMOS devices have formed N + polysilicon gates in both the cell region and the NMOS and PMOS regions. In this case, the NMOS device has a surface channel characteristic. On the other hand, the PMOS device has a buried channel characteristic by count doping.

Meanwhile, when the width of the gate electrode, for example, the half-pitch of the gate is narrowed to 100 nm or less according to the trend of higher integration of semiconductor devices, unlike the NMOS device having the surface channel characteristic, the PMOS device is a buried channel. There is a disadvantage in that the short channel effect is intensified by the characteristics.

Accordingly, in recent years, a dual poly gate forming method of forming an N + poly gate doped with phosphorus (P) in the NMOS region and a P + poly gate doped with boron (B) in the PMOS region has been used. In the dual poly gate forming method, since the NMOS and PMOS devices have surface channel characteristics, the shortcomings due to the buried channel are solved.

On the other hand, as a material capable of such a dual poly gate work function process, molybdenum (Mo) having a low specific resistance and a thermal expansion coefficient similar to that of silicon is mainly used.

In addition, the work function of molybdenum (~ 5eV) on the oxide film is suitable as a P-channel gate material, and heat treatment after N + ion implantation with low energy to make it suitable for the N-channel gate also results in the N-channel gate. It has been reported to be applicable.

The gate work function using molybdenum decreases with increasing ion implantation dose and energy, and this work function reduction phenomenon is caused by Mo 2 at the interface between the injected segregation of the injected nitrogen and the gate and the gate dielectric layer. This is because N is formed.

Therefore, it is important to selectively adjust N + doses in order to apply molybdenum by work function adjustment to the structure of a semiconductor device requiring various voltage values.

Here, care should be taken to properly control the thickness and the ion implantation energy of molybdenum to prevent deterioration of characteristics at the interface between the gate oxide film and the fin pattern. The fin pattern is formed by etching a part of the thickness of the device isolation layer to expose the side surface of the active region, and when the gate is formed on the substrate including the fin pattern, the channel width may be increased to widen the channel region. .

 Therefore, in order to form the shallow junction required in the ultra-high density device, it is necessary to form an optimized transistor structure to control various process conditions.

On the other hand, in the ultra-high density device in which the junction depth of the CMOS element of 0.25 μm or less is reduced to 200 nm or less, the characteristics deterioration at the interface between the gate oxide film and the fin and the eddy current resistance of the transistor and the resistance of the source / drain regions are reduced. Salicide processes are generally applied to reduce.

Materials that are being applied to the salicide process technology as described above generally include TiSi 2 and CoSi 2 , both of them are formed through the heat treatment and wet etching after deposition by sputtering method after deposition of Ti and Co.

However, although not shown and described in detail, it is easy to control the thickness more than a certain amount due to the rapid deposition, which is an advantage of the sputtering method as described above, but there is a limit to uniform deposition thickness control when less than 10 nm is required.

In addition, when there is a problem in the thickness control and uniformity of the metal as described above, a junction leakage current due to non-uniform salicide occurs.

In addition, in the pin-pet transistor having a three-dimensional (3-D) structure, as shown in FIG. 1, the height of the fin where the area of the source / drain surface side portions exposed according to the shape of the transistor is formed and There is a big difference in cross section.

In particular, as shown in Figs. 2 and 3, in the case of a structure having a high silicon level or a narrow aspect ratio, the metals such as cobalt or nickel and molybdenum for the salicide formation on the exposed side of the fin are exposed. Lateral flaw defects occur on the side surface, which makes it difficult to stabilize electrical properties associated with junction regions such as source / drain regions.

In addition, as the length of the fin pattern decreases, the metal deposited thereon may become thin at the edge portion of the fin pattern, in which case the resistive properties of the junction region, such as source / drain regions, are degraded.

Therefore, the failure of the characteristics of the entire semiconductor device is increased due to the above problems.

Accordingly, the present invention provides a method of manufacturing a semiconductor device capable of improving step coverage of a metal silicide layer in forming a transistor having a fin-FET structure.

A method of manufacturing a semiconductor device according to the present invention includes the steps of forming an amorphous silicon film on a semiconductor substrate on which a polysilicon gate is formed; Exposing the amorphous silicon film to a metal source gas to form a metal film on the surface of the amorphous silicon film through a silicon reduction reaction; Heat treating the amorphous silicon film and the metal film to form a metal silicide film through mutual reaction; Removing the unreacted metal film portion during the heat treatment; And heat treating the metal silicide layer.

The polysilicon gate is formed of doped polysilicon.

The polysilicon gate is formed to have an insulating film spacer formed on the sidewall thereof.

The insulating film spacer is formed of a nitride film.

The forming of the amorphous silicon film is performed by heating the semiconductor substrate on which the polysilicon gate is formed to 350 to 450 ° C.

The amorphous silicon film is formed using SiH 4 or Si 2 H 6 gas.

The metal source gas is MoF 6 Or use Ar.

The forming of the metal film is performed in-situ after the forming of the amorphous silicon film.

The metal film is formed of any one of a molybdenum (Mo) film, a tungsten (W) film, a nickel (Ni) film, a titanium (Ti) film, a cobalt (Co) film, a tantalum (Ta) film, and a platinum (Pt) film.

The metal film is formed under a temperature of 200 to 400 ° C. and a pressure of 1 to 10 Torr.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides a metal film such as molybdenum (Mo) by using a chemical vapor deposition method to improve step coverage, which is a problem of the prior art in a transistor having a fin-pet gate structure. Deposited on the exposed silicon fin pattern and the polysilicon gate to form a metal silicide film.

In this way, instead of the conventional method of forming a metal silicide film by depositing a metal film by sputtering, a metal film is deposited by using a chemical vapor deposition method to form a metal silicide film, thereby improving the step coverage, thereby improving the pin-pet structure. Since the metal silicide film can be uniformly formed in the side portions and the source / drain regions of the transistors having the transistors, the step coverage can be improved.

In addition, in the conventional method of forming the metal silicide film using the sputtering method, damage may be caused by forming a damage on the gate insulating film of the thin film, but the deposition of molybdenum using the chemical vapor deposition method described above is PCT (Plasma). Without using a charge trap, it is possible to deposit a metal film uniformly without damage.

Therefore, in the manufacturing of a transistor having a fin-pet structure as described above, by improving the step coverage of the metal silicide film and depositing the metal film uniformly without damage, it is possible to improve the uniformity of the gate resistance. Can stabilize the operating characteristics.

4A to 4B, 5A to 5B to 6A to 6B, and 7A to 7B are cross-sectional views and perspective views illustrating processes for manufacturing a semiconductor device according to an embodiment of the present invention.

4A and 4B, a device isolation layer 402 defining the active region is formed in the device isolation region of the semiconductor substrate 400 having the active region including the gate formation region and the device isolation region. A portion of the isolation layer 402 is etched to form a fin pattern 404 protruding a portion of the active region.

Here, the non-explained reference numeral 406 denotes a hard mask formed to form the fin pattern 406 in the active region.

5A and 5B, a gate insulating film 406 is formed on a semiconductor substrate on which a portion of the device isolation layer 402 of the active region is etched, and a material such as polysilicon is formed on the gate insulating film 406. After the gate conductive layer 408 is formed, a mask pattern 410 for patterning the gate conductive layer 408 is formed on the gate conductive layer 408.

At this time, it is preferable that the polysilicon layer, which is the gate conductive layer 408, is formed of doped polysilicon.

Referring to FIGS. 6A and 6B, the gate conductive layer 408 and the gate insulating layer 406 are patterned to form a polysilicon gate having a fin-pet structure, and then a spacer is formed to surround both sidewalls of the polysilicon gate. 412 is formed.

7A and 7B, an amorphous silicon film (not shown) is deposited on a semiconductor substrate 400 on which the polysilicon gate of the fin-pet structure is formed, and the amorphous silicon film is exposed to a metal source gas to reduce silicon. Through the reaction, the metal silicide layer 414 is formed on the amorphous silicon layer in-situ through a silicon reduction reaction.

Here, since the thickness of the amorphous silicon film increases with exposure time, temperature, and pressure, it is determined based on the thickness of the subsequent metal film layer.

This is a self-limiting, which is a self-limiting phenomenon in which a metal film stops after a predetermined thickness is formed by the metal source gas on the amorphous silicon film, that is, reducing the bottom film. This is because the thickness of the metal film formed by reducing the amorphous silicon film is determined according to the thickness of the film, for example, the amorphous silicon film.

In addition, the deposition of the amorphous silicon film is performed in a state in which the substrate on which the polysilicon gate is formed is heated to a temperature of about 350 to 450 ° C., and the amorphous silicon film is formed using SiH 4 or Si 2 H 6 gas. .

In this case, the reason for heating the substrate on which the polysilicon gate is formed is about 350 to 450 ° C., because the metal film is thinly formed under a nitrogen atmosphere during the subsequent first phase transition heat treatment. When the ammonia remote plasma treatment is performed together with the prevention of silicide, the metal film is formed to be thicker only on the upper portion, so that the silicide reaction can be further suppressed.

In addition, another reason to limit the deposition temperature below 450 ° C. is to prevent the deposition of polycrystalline silicon. In addition, the amorphous silicon film is MoF 6 And a metal source gas and an argon carrier gas are preferably used to form the metal film. If increased thickness is required MoF 6 / H 2 on self-limiting deposited Mo It can be further deposited using a reduction reaction.

In addition, the metal film may be molybdenum (Mo) film, tungsten (W) film, nickel (Ni) film, titanium (Ti) film, cobalt (Co) film, tantalum (A) at a temperature of 200 to 400 ° C and a pressure of 1 to 10 Torr. It is preferable to form one of a Ta) film and a platinum (Pt) film.

On the other hand, the metal source gas is MoF 6 Or Ar, wherein the reason for using the metal source gas as Ar as an inert gas is to collide with the silicon-containing gas adsorbed on the surface to promote decomposition and surface movement of the silicon compound adsorbed on the gas phase and the substrate surface. This is to show a step coating improvement effect.

Thereafter, the unreacted metal film portion is removed by wet etching during the heat treatment, and the metal silicide film is heat-treated for resistance stabilization.

8 is a photograph showing the effect of the semiconductor device manufacturing method according to an embodiment of the present invention, it can be seen that the molybdenum silicide film is uniformly deposited in the fin channel region.

In this case, the present invention, unlike the conventional method of forming a metal silicide film by depositing a metal film by sputtering to form a gate silicide film, by forming a metal silicide film by depositing a metal film using a chemical vapor deposition method, accordingly As a result, it is possible to uniformly form the metal silicide film in the side region gate and the source / drain region of the transistor having the fin-pet structure, thereby improving the step coverage.

In addition, the conventional method of forming a metal silicide film using sputtering may cause a leakage current by forming a damage on the gate insulating film of the thin film, but by using a chemical vapor deposition method when forming a metal film such as molybdenum as described above, Even without using a PCT (Plasma Charge Trap) it is possible to deposit a metal film uniformly without damage (damage).

Therefore, the step coverage can be improved in the transistor having the pin-pet structure as described above, and the metal film can be uniformly deposited without damage, thereby maximizing stabilization of the operating characteristics of the transistor according to the improved resistance uniformity. have.

Meanwhile, in the exemplary embodiment of the present invention, only the fin-pet transistor having a polygate is illustrated and described. However, as described above, the fin-pet transistor having a pure metal film gate, and not the polygate, and the vertical type having increased fin height and fin spacing. Embodiments of the present invention can also be applied to pin-pet transistors.

In addition, a fin-pet transistor having a floating polygate for applying the gate tunneling oxide film and an inter-gate oxide film to the channel region and a fin-pet transistor and dielectric film for applying the dielectric film to the channel region are applied to the channel region, Embodiments of the present invention can also be applied to a pin-pet transistor, a gate tunneling oxide film, a dielectric film, and a blocking oxide film applied to an ion implantation in a channel region.

In addition, the embodiment of the present invention can be applied to the transistors of all semiconductor devices to which the metal silicide film including the transistors of various structures described above is applied.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

As described above, the present invention provides a metal silicide film by depositing a metal film on a polysilicon gate by using a chemical vapor deposition method, thereby improving the step coverage, thereby providing a gate and source side region of a transistor having a fin-pet structure. Since the metal silicide film can be formed uniformly in the / drain region, the step coverage can be improved accordingly.

In addition, unlike the conventional method of forming a metal silicide film using sputtering, which can cause leakage current by forming damage on the gate insulating film of the thin film, by using a chemical vapor deposition method in forming a metal film such as molybdenum In addition, even without using a PCT (Plasma Charge Trap) it is possible to deposit a metal film uniformly without damage (damage).

Accordingly, the present invention improves the step coverage in the transistor having a pin-pet structure as described above, and can deposit a metal film uniformly without damage, thereby stabilizing the operation characteristics of the transistor according to the improvement in resistance uniformity. It can be maximized.

Claims (10)

Forming an amorphous silicon film on the semiconductor substrate on which the polysilicon gate is formed; Exposing the amorphous silicon film to a metal source gas to form a metal film on the surface of the amorphous silicon film through a silicon reduction reaction; Heat treating the amorphous silicon film and the metal film to form a metal silicide film through mutual reaction; Removing the unreacted metal film portion during the heat treatment; Heat treating the metal silicide film; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The polysilicon gate is a method of manufacturing a semiconductor device, characterized in that formed of doped polysilicon. The method of claim 1, The polysilicon gate is formed to have an insulating film spacer formed on the sidewall. The method of claim 3, wherein And the insulating film spacer is formed of a nitride film. The method of claim 1, The forming of the amorphous silicon film may be performed by heating the semiconductor substrate on which the polysilicon gate is formed at 350 to 450 ° C. The method of claim 1, The amorphous silicon film is a method of manufacturing a semiconductor device, characterized in that formed using SiH 4 or Si 2 H 6 gas. The method of claim 1, The metal source gas is MoF 6 Or Ar is used. The method of claim 1, The forming of the metal film may be performed in-situ after the forming of the amorphous silicon film. The method of claim 1, The metal film may be formed of any one of a molybdenum (Mo) film, a tungsten (W) film, a nickel (Ni) film, a titanium (Ti) film, a cobalt (Co) film, a tantalum (Ta) film, and a platinum (Pt) film. A semiconductor device manufacturing method characterized by the above-mentioned. The method of claim 1, The metal film is a method of manufacturing a semiconductor device, characterized in that formed under a temperature of 200 ~ 400 ℃ and a pressure of 1 ~ 10 Torr.
KR1020070031909A 2007-03-30 2007-03-30 Method of manufacturing semiconductor device KR20080088973A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014004034A1 (en) * 2012-06-29 2014-01-03 Intel Corporation Preventing isolation leakage in iii-v devices
CN109003902A (en) * 2018-08-01 2018-12-14 中国科学院微电子研究所 A kind of semiconductor structure and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014004034A1 (en) * 2012-06-29 2014-01-03 Intel Corporation Preventing isolation leakage in iii-v devices
US9748338B2 (en) 2012-06-29 2017-08-29 Intel Corporation Preventing isolation leakage in III-V devices
CN109003902A (en) * 2018-08-01 2018-12-14 中国科学院微电子研究所 A kind of semiconductor structure and preparation method thereof
CN109003902B (en) * 2018-08-01 2021-07-27 中国科学院微电子研究所 Semiconductor structure and preparation method thereof

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