KR20080086893A - Process for producing soi wafer and soi wafer - Google Patents

Abstract

A process for producing an SOI wafer, in which the occurrence of thermal strain, peeling, cracking, etc. attributed to a difference in thermal expansion coefficient between transparent insulating substrate and SOI layer can be prevented through simple and easy processing, and in which upon formation of a semiconductor device on the SOI layer, a reduction of light leakage can be attained. A single-crystal silicon with its entire surface falling in N-region outside OSF-region is grown according to Czochralski technique and sliced to thereby produce an N-region single-crystal silicon wafer. An implantation of hydrogen ion or rare gas ion from a surface of the N-region single-crystal silicon wafer is carried out to thereby form an ion implantation layer in the wafer. The ion implantation surface of the N-region single-crystal silicon wafer and/or a surface of transparent insulating substrate are/is treated with plasma and/or ozone. The ion implantation surface of the N-region single-crystal silicon wafer and the surface of the transparent insulating substrate with the treated surfaces as junction surfaces are joined in close contact at room temperature. The ion implantation layer is impacted so as to attain mechanical detachment of the single-crystal silicon wafer, thereby accomplishing formation of an SOI layer on the transparent insulating substrate.

Description

Method for manufacturing SOI wafer and SOI wafer {PROCESS FOR PRODUCING SOI WAFER AND SOI WAFER}

The present invention relates to a method for producing an SOI wafer and an SOI wafer, and more particularly, to a method for producing an SOI wafer and an SOI wafer for forming an SOI layer on a transparent insulating substrate. In addition, this application relates to the following Japanese patent application. In a designated country where insertion by citing a document is recognized, the present invention is incorporated into the present application by referring to the contents described in the following application and is a part of the description of the present application.

Japanese Patent Application 2004-380587 Filed December 28, 2004

Japanese Patent Application 2005-374892 Filed December 27, 2005

SOI wafers having a silicon on insulator (SOI) structure in which a silicon single crystal layer is formed on an insulator are suitable for fabricating high-density semiconductor integrated circuits, for example, thin film transistor-liquid crystal displays (TFT-LCDs). It is also expected in such optical devices.

In such an optical device, for example, an SOI wafer having an SOI layer formed on a transparent quartz substrate is used. In this case, since the substrate is a complete insulator, the carrier mobility in the SOI layer becomes very high without being influenced by the substrate, and the effect in particular when driven at a high frequency is remarkable.

For example, when a thin film of polycrystalline silicon is formed on a quartz substrate by the CVD method or the like, the maximum value of electron mobility, which is an index of LCD display speed and high definition, is 100 cm 2 / Vsec in the P type, and 200 in the N type. Although about cm 2 / V · sec, in the case of the SOI layer, higher speed can be expected in comparison with this. Moreover, in such an SOI wafer, since a drive circuit can also be integrally formed around the TFT area, high-density mounting can be performed.

SOI wafers used in such optical devices must thin the thickness of the SOI layer to, for example, 0.5 μm or less. Therefore, the bonding of the quartz substrate to the SOI layer needs to be firmly bonded to withstand the thermal and mechanical stresses applied to the SOI layer during grinding, polishing, or device fabrication to thin the SOI layer to such a thickness. For this reason, it is required to raise the bonding force by high temperature heat processing.

However, since the coefficient of thermal expansion differs between the quartz substrate and the SOI layer, stresses due to thermal deformation occur during heat treatment for bonding, cooling after bonding, or during grinding and polishing, resulting in cracking of the quartz substrate or SOI layer. They may peel and break. This problem is not limited to the case where the insulating transparent substrate is a quartz substrate, and this problem inevitably occurs even when the single crystal silicon wafer is bonded with another substrate having a thermal expansion coefficient.

In order to solve such a problem, a method of manufacturing an SOI wafer using a hydrogen ion implantation peeling method is disclosed, in which a combined heat treatment step and a thinning step are alternately performed step by step to alleviate the effects of thermal stress generated during heat treatment. (For example, refer patent document 1).

On the other hand, when a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is fabricated as a TFT in the SOI layer of such an SOI wafer, since the substrate is transparent, light is emitted from the rear surface of the substrate to the channel region of the MOSFET. When incident, leakage current (photo leakage current) is generated, which may deteriorate the characteristics of the device.

On the other hand, the technique which forms a light shielding layer between a board | substrate and an SOI layer, prevents incidence of light from the back surface of a board | substrate, and prevents generation of a light leakage current is disclosed (for example, refer patent document 2).

Patent Document 1: Patent Publication No. Hei 11-145438

Patent Document 2: Japanese Patent Application Laid-Open No. 10-293320

The present invention provides a method of manufacturing an SOI wafer which forms an SOI layer on a transparent insulating substrate, wherein the occurrence of thermal deformation, peeling, and cracking due to a difference in thermal expansion coefficient between the transparent insulating substrate and the SOI layer is prevented by a simple process. It is an object of the present invention to provide a method for producing an SOI wafer and an SOI wafer capable of suppressing light leakage current when a semiconductor device is manufactured in an SOI layer.

In order to achieve the above object, the present invention provides a method for manufacturing an SOI wafer by bonding a single crystal silicon wafer and a transparent insulating substrate, and then forming a SOI layer on the transparent insulating substrate by thinning the single crystal silicon wafer. At least,

A step of growing a single crystal silicon whose entire surface becomes an N region outside the OSF region by the Czochralski method, slicing this to form a wafer, and

Implanting at least one of hydrogen ions or rare gas ions from the surface of the produced N-region single crystal silicon wafer to form an ion implantation layer in the wafer;

Treating the ion implantation surface of the N region single crystal silicon wafer and / or the surface of the transparent insulating substrate with plasma and / or ozone;

Bonding the surface of the N region single crystal silicon wafer and the surface of the transparent insulating substrate to be in close contact with each other at room temperature;

A method of manufacturing an SOI wafer is provided, wherein a step of forming an SOI layer on the transparent insulating substrate by mechanically peeling a single crystal silicon wafer by applying an impact to the ion implantation layer (claim 1).

As described above, in the present invention, a single crystal silicon whose front surface is an N region outside the OSF region is grown by the Czochralski method, and the wafer obtained by slicing this, that is, a defect caused by vacancy defects or interstitial silicon, etc. An N-region single crystal silicon wafer is used in which almost no Grown-in defects exist. When ion implantation is performed from the surface of the N region single crystal silicon wafer, and the ion implantation surface and / or the surface of the transparent insulating substrate are treated with plasma and / or ozone, the ion implantation surface of the wafer and / or the surface of the substrate is The OH group is increased and activated. Therefore, in this state, when the surface subjected to the above treatment is used as the bonding surface, and the N region single crystal silicon wafer and the transparent insulating substrate are brought into close contact with each other at room temperature, the bonded surface is firmly bonded by hydrogen bonding. The height becomes a sufficiently strong joint even without high temperature heat treatment. In addition, since the bonding surface is firmly bonded in this manner, the ion implantation layer is then impacted to mechanically peel off the N region single crystal silicon wafer, thereby forming a thin SOI layer on the transparent insulating substrate. Even if the heat treatment is not performed, the thin film can be formed. Therefore, the SOI wafer can be manufactured without causing thermal deformation, peeling, cracking or the like due to the difference in the thermal expansion coefficient between the transparent insulating substrate and the single crystal silicon wafer. In addition, since the hydrogen ion implantation and stripping method is used for the N region single crystal silicon wafer, an SOI wafer having an N region SOI layer having a thin, excellent film thickness uniformity and excellent crystallinity with little growth-in defects is provided. It can manufacture. In addition, since the SOI layer is composed of N regions, when fabricating a semiconductor device in the SOI layer, deterioration of characteristics of the device due to light leakage current can be suppressed.

Here, the relationship between the pulling rate in the case of growing single crystal silicon by the Czochralski (CZ) method and the defect of the grown single crystal silicon in the N region will be described.

In the case where the growth rate (V) is changed in the crystal axis direction by a CZ puller using an in-furnace structure (hot zone) that becomes a temperature gradient (G) near the solid-liquid interface in the crystal, a defect distribution diagram as shown in FIG. 2 can be obtained. have. The defect distribution has a vertical axis of V (mm / min), a V region in which many public defects exist such as FPD, LSTD, and COP, and an I region in which many defects due to interstitial silicon, such as LSEPD and LFPD, exist. However, there is a region called N region where there is little Grown-in defect between them, such as void type defect or defect caused by interstitial silicon. In addition, near the boundary of the V region, there exists an OSF region where a defect called an OSF (Oxidation induced Stack in Fault) occurs. In this way, the N region is outside the OSF region. In addition, the N region has an Nv region adjacent to the outside of the OSF region and a Ni region adjacent to the I region. By controlling the V / G by adjusting the design of the hot zone and the growth rate, it is possible to obtain single crystal silicon whose front surface is the N region outside the OSF region.

In this case, it is preferable that the grown single crystal silicon does not include the defect region detected by the Cu deposition method (claim 2).

In this way, when the grown single crystal silicon does not include the defect region detected by the Cu deposition method, the grown-in defects are further reduced, and a high-quality SOI layer having very high crystallinity can be formed. Thereby, generation | occurrence | production of a light leakage current can be suppressed further.

In addition, the Cu vapor deposition method is an evaluation method using a current in which a potential is applied to an oxide film formed on the wafer surface in a liquid in which Cu ions are melted, and a current flows to a portion where the oxide film is deteriorated and Cu ions become Cu. As shown in the defect distribution diagram of FIG. 2, a region where a defect is detected by the Cu deposition method exists in a region adjacent to the OSF region as part of the Nv region (hereinafter sometimes referred to as Cu deposition defect region). In such a Cu deposition defect area, it is known that defects, such as a very small COP, exist in the part which an oxide film tends to deteriorate.

In addition, after performing the bonding step, it is preferable to perform a step of increasing the bonding strength by heat-treating the bonded wafer at 100 to 300 ° C, and then forming the SOI layer (claim 3).

In this way, the bonded N region single crystal silicon wafer and the transparent insulating substrate are heat treated at a low temperature of 100 to 300 ° C. without thermal deformation to increase the bonding force, and then subjected to a mechanical peeling process by applying an impact to the ion implantation layer. In addition, the SOI wafer can be manufactured while more reliably preventing occurrence of peeling, cracking, or the like due to mechanical stress.

In addition, it is preferable to perform mirror polishing on the surface of the SOI layer of the SOI wafer obtained by the step of forming the SOI layer (claim 4).

As such, when mirror polishing the surface of the SOI layer of the SOI wafer obtained by the step of forming the SOI layer, the surface roughness of the SOI layer generated in the step of forming the SOI layer or the crystal defects generated in the ion implantation step can be removed. And an SOI wafer having a smooth SOI layer whose surface is mirror polished.

Moreover, it is preferable to make the said transparent insulating board | substrate into either a quartz substrate, a sapphire (alumina) board | substrate, or a glass substrate (claim 5).

Thus, when the transparent insulating substrate is any of a quartz substrate, a sapphire (alumina) substrate, and a glass substrate, since these are transparent insulating substrates with good optical characteristics, an SOI wafer suitable for optical device production can be produced.

Here, as a glass substrate, besides general blue plate glass, a white plate glass, borosilicate glass, an alkali free borosilicate glass, an alumino borosilicate glass, a crystallized glass, etc. can be used. In addition, in the case of using a glass substrate containing an alkali metal, such as blue glass, a diffusion preventing film by spin-on glass is formed on the surface of the glass substrate so as to prevent diffusion of the alkali metal from the surface. It is desirable to.

Moreover, it is preferable to make ion implantation dose at the time of forming the said ion implantation layer larger than 8 * 10 <^16> / cm <2> (claim 6).

Thus, by peeling an ion implantation dose at the time of forming an ion implantation layer more than 8x10 <^16> / cm <2>, mechanical peeling can be performed easily.

The present invention also provides an SOI wafer, which is produced by the manufacturing method of any one of the preceding claims (claim 7).

As described above, if the SOI wafer manufactured by the manufacturing method of any one of the above-mentioned items does not generate thermal deformation, peeling, cracking, etc. at the time of manufacture, it is also useful for manufacturing various devices, and is thin and has excellent film thickness uniformity. In addition, the crystallinity is particularly excellent as the N region, resulting in an SOI wafer having an SOI layer on a transparent insulating substrate having high carrier mobility. In the case where a MOSFET or the like is fabricated in the SOI layer, the SOI wafer is obtained in which the deterioration of characteristics of the device due to the light leakage current is suppressed.

The present invention also provides an SOI wafer having an SOI layer having a thickness of 0.5 μm or less on a transparent insulating substrate, wherein the SOI layer has a front surface of an N region outside the OSF region and a carrier mobility of 250 cm 2 in an N type. An SOI wafer is provided which is at least / Vsec and at least 150 cm 2 / Vsec in a P type (claim 8).

As described above, an SOI wafer having an SOI layer having a thickness of 0.5 μm or less on a transparent insulating substrate, wherein the SOI layer has a front surface of an N region outside the OSF region and a carrier mobility of 250 cm 2 / V · sec in N type. If the SOI wafer is 150 cm 2 / V sec or more in the P-type, the SOI having a SOI layer on the transparent insulating substrate having a high carrier mobility, which is thin and suitable for the optical device and particularly excellent in the N region. It becomes a wafer. In the case where a MOSFET or the like is fabricated in the SOI layer, the SOI wafer is obtained in which the deterioration of characteristics of the device due to the light leakage current is suppressed.

In this case, it is preferable that the SOI layer does not include a defect region detected by the Cu deposition method (claim 9).

In this manner, if the SOI layer does not include the defect region detected by the Cu deposition method, the light leakage current is further suppressed.

According to the method for manufacturing the SOI wafer of the present invention, before bonding the N region single crystal silicon wafer and the transparent insulating substrate, in this state, since the OH group is increased and activated on the surface by treating the surface to be bonded with plasma and / or ozone. When the N region single crystal silicon wafer and the transparent insulating substrate are brought into close contact with each other at room temperature, the surface to be closely bonded is firmly joined by hydrogen bonding. Therefore, even if it does not perform the high temperature heat processing which raises a bonding force after that, it will become a sufficiently strong joint. In addition, since the bonding surface is firmly bonded in this manner, the ion implantation layer can then be impacted to mechanically peel off the N region single crystal silicon wafer, thereby forming a thin SOI layer on the transparent insulating substrate. Therefore, the film can be thinned even if the heat treatment for peeling is not performed. In this manner, the SOI wafer can be manufactured without thermal deformation, peeling, cracking or the like caused by the difference in the thermal expansion coefficient between the transparent insulating substrate and the single crystal silicon.

In addition, since the hydrogen ion implantation and stripping method is used for the N region single crystal silicon wafer, an SOI wafer having an N region SOI layer having a thin, excellent film thickness uniformity and excellent crystallinity with little growth-in defects is provided. It can manufacture. In addition, since the SOI layer is composed of N regions, when a semiconductor device is fabricated in the SOI layer, deterioration of characteristics of the device due to light leakage current can be suppressed.

In addition, the SOI wafer of the present invention does not generate thermal deformation, peeling, cracking, etc. at the time of manufacture, and is useful for manufacturing various devices, is thin and has excellent film thickness uniformity, and particularly excellent crystallinity as the N region. It can be set as the SOI wafer which has an SOI layer on the transparent insulating substrate with high carrier mobility. In the case where a MOSFET or the like is produced in the SOI layer, the SOI wafer can be obtained in which the deterioration of the characteristics of the device due to the light leakage current is suppressed.

In addition, the SOI wafer of the present invention has a SOI layer of 0.5 µm or less that is sufficiently thin without thermal deformation, peeling, cracking, etc., and carrier mobility is 250 cm 2 / V · sec or more in N type, and 15O in P type. It is a SOI wafer suitable for the production of TFT-LCD having a high performance of 2 cm / V · sec or more and capable of displaying high speed and high definition, and the SOI layer is in the N region, so that the light leakage current is obtained when the MOSFET is manufactured. The SOI wafer can be suppressed.

1 is a process chart showing an example of a method of manufacturing an SOI wafer according to the present invention;

2 is a schematic diagram showing a defective area of single crystal silicon grown by the CZ method.

As described above, in the SOI wafer manufacturing method for forming the SOI layer on the transparent insulating substrate, to solve the occurrence of thermal deformation, peeling, cracking, etc. due to the difference in the thermal expansion coefficient of the transparent insulating substrate and the SOI layer, As a method for producing an SOI wafer using a hydrogen ion implantation peeling method, a technique is disclosed in which a bonding heat treatment step and a thinning step are alternately performed step by step to mitigate the effects of thermal stress generated during heat treatment.

However, in order to improve the productivity of SOI wafers, there is a need for a technology that solves the above problems in a short time and a shorter time.

As a result, the inventors of the present application can increase the bonding strength even if the surface to be bonded is subjected to plasma and / or ozone treatment in advance, and can also be mechanically peeled without the heat treatment at the time of peeling, and thus 0.5 탆. It came to be able to be made into the SOI layer of the following thickness.

In addition, conventionally, when a MOSFET is fabricated in the SOI layer of such an SOI wafer, since the substrate is transparent, light leakage current is generated by light entering the channel region of the MOSFET from the back surface of the substrate, resulting in deterioration of device characteristics. There was a case.

In contrast, the inventors of the present application have found that such a light leakage current can be suppressed by having the entire SOI layer consist of the N region outside the OSF region. Although the principle of suppressing the light leakage current by using the SOI layer composed of the N region is not clear, the light leakage current due to the Grown-in defect of the SOI layer, especially COP having a size of 30 to 130 nm is usually It seems to be related to the occurrence of.

As in Patent Document 2, when a light shielding film is provided between the substrate and the SOI layer, light incident directly on the channel region of the MOSFET can be shielded. However, it is conceivable that light leakage current may be generated even when stray light which exists at both ends of the MOSFET and enters the source and drain regions having a large area is scattered by the COP and enters the channel region. In the case of the SOI layer in the N region, since COP is hardly present in the source and drain regions fabricated therein, scattering of visible light with a wavelength of 400 nm or more due to COP does not occur, and accordingly, such scattering causes the channel region of the MOSFET. It is thought that the light which enters into is reduced.

EMBODIMENT OF THE INVENTION Hereinafter, although embodiment of this invention is described concretely, this invention is not limited to these.

1 is a process chart showing an example of a method for manufacturing an SOI wafer according to the present invention.

First, by the CZ method, single crystal silicon whose front surface becomes the N region outside the OSF region is grown, and this is sliced to produce a wafer (step A).

For the growth of single crystal silicon having the entire surface in the N region, for example, in the defect distribution diagram of FIG. 2, when the growth rate (raising rate) of the single crystal silicon during pulling up by the CZ method is decreased from high speed to low speed When the growth rate is further reduced while the growth rate is further reduced at or below the boundary where the OSF region generated in the ring form disappears, the crystal may be grown by controlling the growth rate at or above the growth rate of the boundary forming the I region.

The single crystal silicon in the front N region thus grown is sliced by a cutting device such as a conventional slicer or wire saw having an inner edge, and then subjected to an N region silicon single crystal wafer by a common process such as chamfering, lapping, etching, and polishing. To produce.

The single crystal silicon wafer is not particularly limited as long as it is in the N region. For example, the diameter is 100 to 300 mm, the conductivity type is P type or N type, and the resistivity is about 10 Ω · cm.

Further, preferably, the single crystal silicon to be grown at this time does not include a defect region detected by the Cu deposition method. For this purpose, the growth rate to be controlled may be less than or equal to the growth rate at the boundary where the Cu deposition defect region remaining after the OSF region disappears.

Next, a transparent insulating substrate is prepared (step B).

Although this transparent insulating substrate is not specifically limited, either, a quartz substrate, a sapphire (alumina) substrate, or a glass substrate is used, and since these are transparent insulating substrates with good optical characteristics, an SOI wafer suitable for optical device fabrication can be manufactured. Can be.

Next, at least one of hydrogen ions or rare gas ions is implanted from the surface of the produced N-region single crystal silicon wafer to form an ion implantation layer in the wafer (step C).

For example, the implantation energy for forming an ion implantation layer at a temperature corresponding to a predetermined SOI layer thickness, for example, 0.5 μm or less, from the surface of the N region single crystal silicon wafer is 250 to 450 ° C., At least one of a dose of hydrogen ions or rare gas ions is implanted. As conditions at this time, for example, the injection energy may be 20 to 10 10 keV, and the injection dose may be 1 × 10 ^{16 to} 1 × 10 ¹⁷ / cm 2. In this case, in order to facilitate peeling in the ion implantation layer, the ion implantation dose is preferably made larger than 8 × 10 ¹⁶ / cm 2. Further, if an arbitrary insulating film such as a thin silicon oxide film is formed in advance on the surface of the single crystal silicon wafer, and ion implantation is performed through this, the effect of suppressing channeling of the implanted ions can be obtained.

Next, the ion implantation surface and / or the surface of the transparent insulating substrate of this N region single crystal silicon wafer are treated with plasma and / or ozone (step D).

In the case of a plasma treatment, an N region single crystal silicon wafer and / or a transparent insulating substrate which has been cleaned by RCA cleaning or the like is placed in a vacuum chamber, and plasma gas is introduced therein, followed by 5 to 10 seconds in a high frequency plasma of about 100 W. The surface is exposed to a plasma treatment. As the gas for plasma, when processing an N region single crystal silicon wafer, when the surface is oxidized, plasma of oxygen gas, when not oxidized, hydrogen gas, argon gas, or a mixed gas thereof, or a mixture of hydrogen gas and helium gas Gas can be used. When processing a transparent insulating substrate, you may use any gas.

In the case of treatment with ozone, after placing an N region single crystal silicon wafer and / or a transparent insulating substrate which has been cleaned such as RCA cleaning in a chamber into which air is introduced, and introducing a gas for plasma such as nitrogen gas and argon gas, The surface is ozone treated by generating a high frequency plasma and converting oxygen in the atmosphere into ozone. Either one of the plasma treatment and the ozone treatment may be performed, or both may be performed.

By treatment with such plasma and / or ozone, the organic matter on the surface of the N region single crystal silicon wafer and / or the transparent insulating substrate is oxidized and removed, and the OH groups on the surface increase and are activated. As the surface to be processed, it becomes a bonding surface, and if it is an N area | region single crystal silicon wafer, it becomes an ion implantation surface. Although it is more preferable to process both an N area | region single crystal silicon wafer and a transparent insulating substrate, you may process only one.

Next, using the surface treated with plasma and / or ozone as a bonding surface, the ion implantation surface of the N region single crystal silicon wafer and the surface of the transparent insulating substrate are bonded to each other at room temperature to be bonded (Step E).

In step D, since at least one of the ion implantation surface of the N-region single crystal silicon wafer or the surface of the transparent insulating substrate is plasma-treated and / or ozone-treated, only they are brought into close contact with each other at a general temperature of about room temperature under reduced pressure or atmospheric pressure, for example. This enables strong bonding with strength that can withstand mechanical peeling in subsequent processes. Therefore, high temperature bond heat treatment of 1200 ° C or higher is not necessary, and thermal deformation, cracking, peeling, or the like due to a difference in thermal expansion coefficient, which is a problem due to heating, is preferable.

After that, the bonded wafer may then be heat treated at a low temperature of 100 to 300 ° C. to increase the bonding force (step F).

For example, when the transparent insulating substrate is quartz, the coefficient of thermal expansion is smaller than that of silicon (Si: 2.33 × 10 ⁻⁶ , quartz: O.6 × 10 ⁻⁶ ), and 300 ° C. when bonded and heated with a silicon wafer having a similar thickness. Beyond this, the silicon wafer is broken. However, such a relatively low temperature heat treatment is preferable because there is no fear of thermal deformation, cracking or peeling due to a difference in thermal expansion coefficient. In the case of using a heat treatment furnace of a batch treatment method, sufficient heat treatment time can be obtained if the heat treatment time is about 0.5 to 24 hours.

Next, the ion implantation layer is subjected to an impact to mechanically peel off the N region single crystal silicon wafer, thereby forming an SOI layer on the transparent insulating substrate (step G).

In the hydrogen ion implantation peeling method, the bonded wafer is heat treated at about 500 ° C. under an inert gas atmosphere, and thermal peeling is performed due to the rearrangement effect of the crystal and the bubble aggregation effect of the injected hydrogen, but in the present invention, the ion implantation layer Since mechanical peeling is performed by applying an impact to it, there is no fear that thermal deformation, cracking, peeling, or the like occurs due to heating.

In order to apply an impact to the ion implantation layer, it is preferable to spray continuously or intermittently, for example, from the side of the wafer to which a jet of a fluid such as gas or liquid is bonded. However, the method is not particularly limited as long as mechanical peeling occurs due to the impact.

In this way, although the SOI wafer in which the SOI layer of N area | region was formed on the transparent insulating board | substrate by the peeling process can be obtained, it is preferable to perform mirror polishing on the surface of the SOI layer of the SOI wafer obtained in this way (process H).

By this mirror polishing, surface roughness called haze generated in the peeling process can be removed, or crystal defects near the surface of the SOI layer caused by ion implantation can be removed. As this mirror polishing, polishing with very low polishing value of 5 to 400 nm, for example, touch polish, can be used.

The SOI wafers produced by the processes A to H do not cause thermal deformation, peeling, cracking, etc. at the time of manufacture, and are useful for manufacturing various devices, are thin and have excellent film thickness uniformity, and are particularly excellent in crystallinity. Thus, an SOI wafer having an SOI layer on a transparent insulating substrate having high carrier mobility can be obtained. Since the SOI layer is formed on the transparent insulating substrate, such an SOI wafer is particularly suitable for the production of optical devices such as TFT-LCDs. In addition, since the SOI layer does not include the entire surface N region, preferably the Cu deposition defect region, generation of a light leakage current can be suppressed even when a MOSFET is manufactured.

In addition, such an SOI wafer can be made to have an SOI layer having a thickness of 0.5 µm or less without thermal deformation, peeling, cracking, or the like on the transparent insulating substrate. The SOI layer has a front surface of an N region outside the OSF region and a carrier mobility of 250 cm 2 / V sec or more in the N type and 150 cm 2 / V sec or more in the P type. Therefore, in the case of polycrystalline silicon, the highest mobility of electrons was about 100 cm 2 / V sec in P type and about 200 cm 2 / V sec in N type. It is an SOI wafer suitable for manufacturing TFT-LCDs having excellent performance. In addition, since the SOI layer is an N region and preferably does not include a Cu deposition defect region, it is an SOI wafer capable of suppressing the light leakage current when a MOSFET is fabricated.

(Example)

As a wafer for forming an SOI layer, a single crystal silicon wafer having a diameter of 200 mm, which is made of a silicon single crystal rod having an entire N area and mirror-polished on one surface thereof, is prepared, and the silicon oxide film layer is formed on the surface by thermal oxidation. Nm was formed. The surface roughness Ra of the oxide film layer on the mirror-surface side which was bonded was 0.2 nm. The measurement was performed in a measurement area of 10 µm × 10 µm using an atomic force microscope.

On the other hand, a synthetic quartz wafer having a diameter of 200 mm whose one surface was mirror polished was prepared for the transparent insulating substrate. The surface roughness Ra of the mirror surface side which performs the bonding was 0.19 nm. The measuring apparatus and the measuring method were made the same conditions as the oxide film layer of a single crystal silicon wafer.

Hydrogen ions were selected as ions to be injected into the single crystal silicon wafer through the 100 nm silicon oxide film layer, and the ions were implanted under conditions of an implantation energy of 35 keV and an implantation dose of 9 × 10 ¹⁶ / cm 2. The implantation depth in the single crystal silicon layer was 0.3 nm.

Next, the ion-implanted single crystal silicon wafer was placed in a plasma processing apparatus, and air was introduced as a gas for plasma. A high frequency power of 13.56 MHz was applied between parallel flat electrodes having a diameter of 300 mm under a reduced pressure of 2 Torr. It applied on the conditions of W, and performed the high frequency plasma process for 5 to 10 second.

On the other hand, with respect to the synthetic quartz wafer, the wafer is placed in a chamber into which air is introduced, argon gas is introduced as a plasma gas between the narrow electrodes, and then plasma is generated by applying a high frequency between the electrodes, and the plasma and By interposing the atmosphere between the substrates, oxygen in the atmosphere was ozonated, and the bonding surface was treated by the ozone. Processing time was made into 5 to 10 second.

After the wafers subjected to the surface treatment as described above were brought into close contact with each other at room temperature, bonding was started by strongly pressing one end portion of both wafers in the thickness direction. When this was left to stand at room temperature for 48 hours, when the bonding surface was visually confirmed, a wide bonding was confirmed on the entire surface of the substrate on the bonding surface. One wafer was fixed so as to confirm the bonding strength, and a stress was applied to the wafer surface of the other wafer in the parallel direction so as to be shifted laterally, but not shifted.

Next, in order to exfoliate by impacting an ion implantation layer, the blade of the paper cutting scissors was struck several times at the diagonal position with respect to the side surface of a bonded wafer. Thereby, peeling occurred in the ion implantation layer, so that the SOI wafer and the remaining single crystal silicon wafer could be obtained.

When the surface (peeled surface) of the SOI layer is visually confirmed, the surface roughness is rougher than the surface roughness (Ra = 0.2 nm) of the bonded surface, so that polishing is performed at a polishing value of 100 nm, and the surface roughness Ra is 0.2 nm. The following smooth surfaces were obtained. Moreover, according to the measurement of the in-plane film thickness uniformity of this SOI layer, it was confirmed that film thickness nonuniformity is ± 10 nm or less in wafer surface, and has favorable film thickness uniformity. In addition, about the crystallinity of an SOI layer, SECCO defect evaluation was performed using the liquid which diluted the SECCO etching liquid according to the regular method. As a result, the defect density was able to obtain a satisfactory value of 2 × 10 ³ to 6 × 10 ³ / cm 2.

In addition, this invention is not limited to the said embodiment. The above embodiment is merely an example, and any one having substantially the same configuration as the technical idea described in the claims of the present invention and showing the same operation and effect is included in the technical idea of the present invention.

For example, since the SOI layer of the SOI wafer after the steps A to G has already been sufficiently thinned, a high-temperature heat treatment (more than 500 ° C. to less than the melting point of silicon) may be performed to further increase the bond strength according to the purpose.

Claims (9)

A method of manufacturing an SOI wafer by bonding a single crystal silicon wafer and a transparent insulating substrate to form a SOI layer on the transparent insulating substrate by thinning the single crystal silicon wafer. A step of growing a single crystal silicon whose entire surface becomes an N region outside the OSF region by the Czochralski method, slicing this to form a wafer, and Implanting at least one of hydrogen ions or rare gas ions from the surface of the produced N-region single crystal silicon wafer to form an ion implantation layer in the wafer; Treating any one or both of the ion implantation surface of the N region single crystal silicon wafer and the surface of the transparent insulating substrate with at least one of plasma and ozone; Bonding the surface of the N region single crystal silicon wafer and the surface of the transparent insulating substrate to be in close contact with each other at room temperature; Impacting the ion implantation layer to mechanically peel a single crystal silicon wafer to form an SOI layer on the transparent insulating substrate The manufacturing method of SOI wafer characterized by performing the above. The method of manufacturing an SOI wafer according to claim 1, wherein the grown single crystal silicon does not include a defect region detected by a Cu deposition method. The method according to claim 1 or 2, wherein after the bonding step is performed, the bonded wafer is subjected to a heat treatment at 100 to 300 DEG C to increase the bonding force, and then the SOI layer is formed. SOI wafer manufacturing method. The method for manufacturing an SOI wafer according to any one of claims 1 to 3, wherein mirror polishing is performed on the surface of the SOI layer of the SOI wafer obtained by the step of forming the SOI layer. The said transparent insulating substrate is any one of a quartz substrate, a sapphire (alumina) substrate, and a glass substrate, The manufacturing method of the SOI wafer in any one of Claims 1-4 characterized by the above-mentioned. The method of manufacturing an SOI wafer according to any one of claims 1 to 5, wherein an ion implantation dose when forming the ion implantation layer is made larger than 8 x 10 ¹⁶ / cm 2. The SOI wafer manufactured by the manufacturing method of the SOI wafer as described in any one of Claims 1-6. An SOI wafer having an SOI layer having a thickness of 0.5 μm or less on a transparent insulating substrate, The SOI layer is characterized in that the entire surface is an N region outside the OSF region, carrier mobility is 250 cm 2 / V sec or more in the N type, and 150 cm 2 / V sec or more in the P type. . The SOI wafer according to claim 8, wherein the SOI layer does not include a defect region detected by a Cu deposition method.

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