KR20080084276A - Semiconductor package and method of manufacturing thereof - Google Patents

Abstract

A semiconductor package and a method for manufacturing the same are provided to test semiconductor chips of various sizes using one test socket by forming an area control molding unit and a thickness control molding unit. A semiconductor chip(110) is provided with an external connection terminal. An area control molding unit(120) is arranged along a lateral surface of the semiconductor chip so as to mount the semiconductor chip on a test socket having a plane area greater than that of the semiconductor device. The area control molding unit includes an epoxy resin. A thickness control molding unit(123) covering an upper surface of the semiconductor chip is prepared in order to reduce a height of the test socket and a thickness deviation of the semiconductor chip. The thickness control molding unit has at least one opening that exposes the upper surface of the semiconductor chip.

Description

Semiconductor package and manufacturing method therefor {SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF}

1 is a cross-sectional view showing a semiconductor package and a test socket according to a first embodiment of the present invention.

2 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention.

3 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention.

4 is a sectional view showing a semiconductor package according to another embodiment of the present invention.

5 is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to an embodiment of the present invention.

6 is a cross-sectional view showing a state in which the upper mold and the lower mold shown in FIG.

7 and 8 are cross-sectional views showing a method for manufacturing a semiconductor package according to another embodiment of the present invention.

The present invention relates to a semiconductor package and a method of manufacturing the same.

The semiconductor device is a semiconductor chip manufactruing process for manufacturing a semiconductor chip on a silicon wafer made of high-purity silicon, a die sorting process for electrically inspecting the semiconductor chip, and selecting and packaging good semiconductor chips. It is manufactured through a semiconductor packaging process (semiconductor packaging process) and a test process (test process) to finally test the semiconductor package.

Among these processes, the test process is performed using a test socket. The test socket mounts the manufactured semiconductor package and applies a test signal to the semiconductor package to test whether the semiconductor package is operating normally.

In recent years, with the development of a semiconductor package manufacturing process, the size of a semiconductor package has become very diverse.

However, as the size of the semiconductor package varies, the size of the test socket for finally testing the semiconductor package must also be developed corresponding to the size of the semiconductor package, and in particular, a semiconductor package developed in a smaller size is larger than the semiconductor package. Difficult to test by mounting on a socket.

As a result, when the size of the semiconductor package is different from each other, a test socket must be newly manufactured to correspond to each of the different semiconductor packages, thereby increasing the production cost of the semiconductor package.

The present invention provides a semiconductor package that can be mounted in a test socket manufactured by adjusting the volume of the semiconductor package.

In addition, the present invention provides a method of manufacturing the semiconductor package.

A semiconductor package according to the present invention includes a semiconductor chip having an external connection terminal; And an area adjusting molding part disposed along a side of the semiconductor chip to mount the semiconductor chip to a test socket having a planar area larger than that of the semiconductor chip.

Here, the area control molding part comprises an epoxy resin.

The apparatus may further include a thickness adjusting molding part covering an upper surface of the semiconductor chip to reduce height of the test socket and thickness variation of the semiconductor chip.

The thickness control molding part has at least one opening exposing the top surface of the semiconductor chip.

In addition, the method of manufacturing a semiconductor package according to the present invention comprises the steps of: accommodating the external connection terminals of the semiconductor package inside the first cavity formed in the lower mold; Coupling an upper mold having a second cavity larger than a planar area of the semiconductor package with the lower mold; And forming an area adjusting molding part on a side surface of the semiconductor package by injecting a molding resin between the side surface of the semiconductor package and the second cavity.

Here, the upper surface of the second cavity and the semiconductor package is in close contact.

A gap is formed between the second cavity and the top surface of the semiconductor package, and the second cavity includes at least one protrusion for pressing the top surface of the semiconductor package.

Mounting the semiconductor package having the molding for adjusting the area in a test socket; And testing the semiconductor package in the test socket.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a semiconductor package and a test socket according to a first embodiment of the present invention.

The semiconductor package 100 according to the present invention includes a semiconductor chip 10 and an area control molding part 20.

In the present embodiment, the semiconductor package 100 may be a wafer level semiconductor package which is only 100% to 110% of the planar area of the semiconductor chip 10.

The semiconductor chip 10 includes a data storage unit (not shown) for storing a large amount of data, a circuit unit (not shown) for processing stored data, and a bonding pad and a bonding pad for inputting and / or outputting data or signals. It includes an external connection terminal 30 composed of a bump formed in the.

The semiconductor package 100 including the semiconductor chip 10 having an external connection terminal 30 is mounted in a test socket indicated by reference numeral 40 in FIG. 1, and the semiconductor package 100 mounted in the test socket 40. Is tested by a test signal provided through a signal input / output terminal disposed in the test socket 40.

Meanwhile, semiconductor packages having different sizes may be mounted and tested in the test socket 40. For example, since the semiconductor package having a size larger than that of the test socket 40 cannot be mounted inside the test socket 40, the test of the semiconductor package 100 is also impossible. In addition, in the case of a semiconductor package having a smaller size than the test socket 40, the semiconductor package may be mounted inside the test socket 40, but the semiconductor package may move inside the test socket 40, thereby causing frequent test failures.

In this embodiment, in order to be able to test a semiconductor package having a size smaller than that of the test socket 40 by mounting it in the test socket 40 larger than the size of the semiconductor package (100) in the side surface of the semiconductor package 100 20) is arranged.

The area adjusting molding part 20 is disposed on the side surface of the semiconductor chip 10 of the semiconductor package 100. The area control molding part 20 has a size suitable for preventing the semiconductor package 100 from flowing in the test socket 40 when the semiconductor package 100 is mounted on the test socket 40.

In the present exemplary embodiment, the area adjusting molding part 20 may be disposed along the side surface of the semiconductor chip 10 of the semiconductor package 100. Alternatively, the plurality of area control molding part 20 may be formed at regular intervals. Alternatively, the area adjusting molding part 20 may be formed in a plurality of irregular intervals.

Meanwhile, in the present embodiment, the thickness of the area adjusting molding part 20 may be substantially the same as the thickness of the semiconductor chip 10. Alternatively, the thickness of the area control molding part 20 may be smaller than the thickness of the semiconductor chip 10. In the present embodiment, the area adjusting molding part 20 may include an epoxy resin.

2 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

Referring to FIG. 2, the semiconductor package 200 includes a semiconductor chip 110, an area control molding part 120, and a thickness control molding part 123.

In the present embodiment, the semiconductor package 200 may be a wafer level semiconductor package that is only 100% to 110% of the planar area of the semiconductor chip 110.

The semiconductor chip 110 may include a data storage unit (not shown) for storing a large amount of data, a circuit unit (not shown) for processing stored data, and an external connection terminal 130 including a bonding pad and a bump formed on the bonding pad. ).

The semiconductor package 200 including the semiconductor chip 110 having an external connection terminal 130 is mounted in a test socket (not shown), and the semiconductor package 200 mounted in the test socket is a signal input / output disposed in the test socket. It is tested by the test signal provided through the terminal.

Meanwhile, semiconductor packages having different sizes may be mounted on the test sockets and thus may not be tested. For example, testing of a semiconductor package is also impossible because a semiconductor package having a planar and thicker thickness than the test socket cannot be mounted inside the test socket. In addition, in the case of a semiconductor package having a planar thickness and a thinner thickness than that of the test socket, the semiconductor package can be mounted inside the test socket, but the semiconductor package moves up, down, left, and right inside the test socket, which causes frequent test failures.

In this embodiment, the semiconductor package 200 is moved to the left and right sides of the semiconductor package 200 in order to mount and test the semiconductor package having a planar thickness and a thinner thickness than the test socket in a test socket larger than the planar surface of the semiconductor package. An area control molding part 120 is disposed to prevent the gap, and a thickness control molding part 123 is disposed on an upper surface of the semiconductor package 200 to prevent vertical movement of the semiconductor package 200.

The area adjusting molding part 120 is disposed on the side surface of the semiconductor chip 110 of the semiconductor package 200. The area control molding part 120 has a size suitable for preventing the semiconductor package 200 from flowing left and right inside the test socket when the semiconductor package 200 is mounted in the test socket.

In the present embodiment, the area adjusting molding part 120 may be disposed along the side surface of the semiconductor chip 110 of the semiconductor package 200. Alternatively, a plurality of the area adjusting molding part 120 may be formed at regular intervals. Alternatively, the area adjusting molding part 120 may be formed in a plurality of irregular intervals.

Meanwhile, in the present embodiment, the thickness of the area adjusting molding part 120 may be substantially the same as the thickness of the semiconductor chip 110. Alternatively, the thickness of the area adjusting molding part 120 may be smaller than the thickness of the semiconductor chip 110.

In addition, the thickness adjusting molding part 123 formed on the upper surface of the semiconductor package 200 prevents the semiconductor package 200 from moving upward and downward in the test socket because the thickness of the semiconductor package 200 is lower than the height of the test socket. The semiconductor package 200 is stably tested.

In the present embodiment, the thickness control molding part 123 includes at least one opening 124 exposing the top surface of the semiconductor package 200, and the thickness control molding part 123 and the area control molding part 123 are For example, it may include an epoxy resin.

3 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

Referring to FIG. 3, the semiconductor package 300 includes a substrate 320, a semiconductor chip 310, a conductive wire 330, a molding part 335, and a molding part 350 for thickness control.

In the present embodiment, the substrate 320 may be a printed circuit board, bond fingers 325 are disposed on the upper surface of the substrate 320, and conductive balls such as solder balls are mounted on the rear surface of the substrate 320. A ball land 327 is disposed. Ball land 327 and bond finger 325 are electrically connected.

The semiconductor chip 310 is disposed on the top surface of the substrate 320. In this embodiment, the semiconductor chip 310 has a plurality of bonding pads 315 corresponding to external connection terminals, and the bonding pads 315 are bonded to the top surface of the substrate 320 by the conductive wires 330. It is electrically connected with the finger 325.

The semiconductor chip 310 and the substrate 320 are bonded to each other by, for example, an adhesive member 337.

The molding part 335 molds the semiconductor chip 310 and the conductive wire 330. In the present embodiment, the molding part 335 may be an epoxy resin.

The semiconductor package 300 including the substrate 320, the semiconductor chip 310, the conductive wire 330, and the molding part 335 is mounted in a test socket, which is indicated by reference numeral 340 in FIG. 3, and the test socket 340. The semiconductor package 300 mounted on the C) is tested by a test signal provided through a signal input / output terminal disposed in the test socket 340.

Meanwhile, semiconductor packages having different sizes may be mounted on the test socket 340 to be tested. For example, since the semiconductor package having a larger size than the test socket 340 cannot be mounted inside the test socket 340, the semiconductor package 300 may not be tested. In addition, in the case of a semiconductor package having a smaller size than the test socket 340, it is possible to mount the inside of the test socket 340, but the semiconductor package moves inside the test socket 340, which causes frequent test failures.

In this embodiment, in order to be able to test a semiconductor package having a size smaller than that of the test socket 340 by mounting the test socket 340 larger than the size of the semiconductor package (100) in the side surface of the semiconductor package 100 350 is disposed.

The area adjustment molding part 350 may be disposed on side surfaces of the substrate 320 and the molding part 335 of the semiconductor package 300. The area control molding part 350 has a size suitable for preventing the semiconductor package 300 from flowing in the test socket 340 when the semiconductor package 300 is mounted in the test socket 340.

In the present exemplary embodiment, the area adjusting molding part 350 may be disposed along side surfaces of the substrate 320 and the molding part 335 of the semiconductor package 300. Unlike this, the plurality of area adjusting molding parts 350 may be formed at predetermined intervals on the side surfaces of the substrate 320 and the molding part 335. Alternatively, the plurality of area adjusting molding parts 20 may be formed at irregular intervals on the side surfaces of the substrate 320 and the molding part 335.

Meanwhile, in the present embodiment, the thickness of the area adjusting molding part 350 may be substantially the same as the thickness of the semiconductor chip 310. Alternatively, the thickness of the area adjusting molding part 350 may be smaller than the thickness of the semiconductor chip 310. In the present embodiment, the area control molding part 350 may include an epoxy resin.

4 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

Referring to FIG. 4, the semiconductor package 300 includes a substrate 320, a semiconductor chip 310, a conductive wire 330, a molding part 335, a thickness control molding part 350, and a height control molding part 352. It includes.

In the present embodiment, the substrate 320 may be a printed circuit board, bond fingers 325 are disposed on the upper surface of the substrate 320, and conductive balls such as solder balls are mounted on the rear surface of the substrate 320. A ball land 327 is disposed. Ball land 327 and bond finger 325 are electrically connected.

The semiconductor chip 310 is disposed on the top surface of the substrate 320. In this embodiment, the semiconductor chip 310 has a plurality of bonding pads 315 corresponding to external connection terminals, and the bonding pads 315 are bonded to the top surface of the substrate 320 by the conductive wires 330. It is electrically connected with the finger 325.

The semiconductor chip 310 and the substrate 320 are bonded to each other by, for example, an adhesive member 337.

The molding part 335 molds the semiconductor chip 310 and the conductive wire 330. In the present embodiment, the molding part 335 may be an epoxy resin.

The semiconductor package 300 including the substrate 320, the semiconductor chip 310, the conductive wire 330, and the molding unit 335 is mounted in a test socket (not shown), and the semiconductor package 300 mounted in the test socket. ) Is tested by the test signal provided through the signal input and output terminals placed in the test socket.

Meanwhile, semiconductor packages having different sizes may be mounted on the test sockets and thus may not be tested. For example, since the semiconductor package having a size larger than that of the test socket cannot be mounted inside the test socket, the test of the semiconductor package 300 is also impossible. In addition, the semiconductor package having a smaller size than the test socket can be mounted inside the test socket, but the semiconductor package moves up, down, left, and right inside the test socket, which causes frequent test failures.

In this embodiment, in order to be able to test a semiconductor package having a size smaller than the test socket in a test socket larger than the size of the semiconductor package without lateral movement, the molding portion 350 for adjusting the area is formed on the side of the semiconductor package 100. Is placed.

The area adjustment molding part 350 may be disposed on side surfaces of the substrate 320 and the molding part 335 of the semiconductor package 300. The area control molding part 350 has a size suitable for preventing the semiconductor package 300 from flowing in the test socket when the semiconductor package 300 is mounted in the test socket.

In the present exemplary embodiment, the area adjusting molding part 350 may be disposed along side surfaces of the substrate 320 and the molding part 335 of the semiconductor package 300. Unlike this, a plurality of molding portions 350 may be formed at predetermined intervals on the side surfaces of the substrate 320 and the molding portion 335. Alternatively, the plurality of area control molding parts 350 may be formed at irregular intervals on the side surfaces of the substrate 320 and the molding part 335.

Meanwhile, in the present embodiment, the thickness of the area adjusting molding part 350 may be substantially the same as the thickness of the semiconductor chip 310. Alternatively, the thickness of the area adjusting molding part 350 may be smaller than the thickness of the semiconductor chip 310. In the present embodiment, the area control molding part 350 may include an epoxy resin.

Meanwhile, the height adjusting molding part 352 is disposed on the upper surface of the molding part 335 of the semiconductor package 300. The height adjustment molding part 352 may stably test the semiconductor package 300 by preventing the semiconductor package 300 from moving up and down inside the test socket while the semiconductor package 300 is mounted in the test socket. Make sure In the present embodiment, the height adjusting molding part 356 may include an epoxy resin.

5 is a cross-sectional view illustrating a process of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 5, first, a data storage unit (not shown) for storing a large amount of data, a circuit unit (not shown) for processing stored data, and a bonding pad and bonding for inputting and / or outputting data or signals A semiconductor package 100 including an external connection terminal 30 composed of a bump formed on a pad is manufactured.

Subsequently, before the test is performed by coupling the semiconductor package 100 to the test socket, an area adjusting molding part is formed on the side of the semiconductor package 100 so that the semiconductor package 100 can be accurately mounted on the test socket.

In order to form the area adjusting molding part, the semiconductor package 100 is first disposed on the lower mold 410. The lower mold 410 includes a recess 415 for receiving the external connection terminal 30 of the semiconductor package 100. The depth of the recess is sufficient such that the external connection terminal 30 does not contact the bottom surface of the lower mold 410 on which the recess 415 is formed, and the width of the recess 415 is defined by the semiconductor package 100. Sufficient enough is enough.

6 is a cross-sectional view illustrating a state in which the upper mold and the lower mold illustrated in FIG. 5 are combined.

Referring to FIG. 6, when the upper mold 420 is formed in the lower mold 410, a cavity is selectively formed on the side surface of the semiconductor package 100, and the upper surface of the semiconductor package 100 may be formed of the buffer member 425. It is in close contact with the upper mold 420 having.

In the state in which the lower mold 410 and the upper mold 420 are coupled, a molding material such as an epoxy resin is injected into the cavity to form an area control molding part 20 on the side surface of the semiconductor package 100.

7 and 8 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with another embodiment of the present invention.

7 and 8, a data storage unit (not shown) for storing a large amount of data, a circuit unit (not shown) for processing stored data, and a bonding pad for inputting and / or outputting data or signals; A semiconductor package 100 including an external connection terminal 30 formed of a bump formed on a bonding pad is manufactured.

Subsequently, before the test is performed by coupling the semiconductor package 100 to the test socket, an area adjusting molding part is formed on the side of the semiconductor package 100 so that the semiconductor package 100 can be accurately mounted on the test socket, and the semiconductor package ( The molding part for thickness adjustment is formed on the upper surface of 100).

 In order to form the area adjusting molding part and the thickness adjusting molding part, the semiconductor package 100 is first disposed in the lower mold 410. The lower mold 410 includes a recess 415 for receiving the external connection terminal 30 of the semiconductor package 100. The depth of the recess is sufficient such that the external connection terminal 30 does not contact the bottom surface of the lower mold 410 on which the recess 415 is formed, and the width of the recess 415 is defined by the semiconductor package 100. Sufficient enough is enough.

When the upper mold 420 is coupled to the lower mold 410, a first cavity is selectively formed on the side surface of the semiconductor package 100, and a second cavity is formed on the upper surface of the semiconductor package 100. . In this case, a plurality of fixing protrusions 427 may be formed on the inner surface of the upper mold 420 to press and fix a portion of the upper surface of the semiconductor package 100. In the state in which the lower mold 410 and the upper mold 420 are coupled to each other, a molding material such as an epoxy resin is injected into the first cavity and the second cavity so that an area adjusting molding part 20 is formed on the side surface of the semiconductor package 100. The thickness adjusting molding part 20 is formed on the upper surface of the semiconductor package 100.

As described in detail above, in the case of a semiconductor package smaller than a test socket for testing a semiconductor package, a molding part for adjusting an area and / or a thickness may be separately formed on the side and / or the top surface of the semiconductor package, thereby different from each other. It has the advantage of being able to test a semiconductor chip having a size.

Although the detailed description of the present invention has been described with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art will have the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (11)

A semiconductor chip having an external connection terminal; And An area adjusting molding part disposed along a side of the semiconductor chip to mount the semiconductor chip to a test socket having a planar area larger than that of the semiconductor chip; Semiconductor package comprising a. The method of claim 1, The area control molding part is a semiconductor package, characterized in that it comprises an epoxy resin. The method of claim 1, And a thickness adjusting molding part covering an upper surface of the semiconductor chip in order to reduce height of the test socket and thickness variation of the semiconductor chip. The method of claim 3, wherein And the thickness adjusting molding part has at least one opening exposing the top surface of the semiconductor chip. A semiconductor package comprising a substrate having an external connection terminal, a semiconductor chip disposed on the substrate and connected to the external connection terminal, and a molding part covering the semiconductor chip. And an area adjusting molding part disposed at a side of the molding part to mount the semiconductor package to a test socket having a plane area larger than that of the substrate. The method of claim 5, wherein The molding part and the area control molding part is a semiconductor package, characterized in that it comprises an epoxy resin. The method of claim 5, wherein A semiconductor package, characterized in that the molding portion for adjusting the thickness to reduce the height deviation of the test socket and the semiconductor package on the upper surface of the molding portion. Accommodating external connection terminals of the semiconductor package in a first cavity formed in the lower mold; Coupling an upper mold having a second cavity larger than a planar area of the semiconductor package with the lower mold; And Injecting a molding resin between the side surface of the semiconductor package and the second cavity to form an area control molding part on the side surface of the semiconductor package; Method of manufacturing a semiconductor package comprising a. The method of claim 8, The second cavity and the upper surface of the semiconductor package is in close contact with the manufacturing method of the semiconductor package. The method of claim 8, A gap is formed between the second cavity and an upper surface of the semiconductor package, wherein the second cavity includes at least one protrusion for pressing the upper surface of the semiconductor package. The method of claim 8, Mounting the semiconductor package having the molding for adjusting the area in a test socket; And testing the semiconductor package in the test socket.

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