KR20080084167A - Method of manufacturing a transistor in semiconductor device - Google Patents

Method of manufacturing a transistor in semiconductor device Download PDF

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Publication number
KR20080084167A
KR20080084167A KR1020070025487A KR20070025487A KR20080084167A KR 20080084167 A KR20080084167 A KR 20080084167A KR 1020070025487 A KR1020070025487 A KR 1020070025487A KR 20070025487 A KR20070025487 A KR 20070025487A KR 20080084167 A KR20080084167 A KR 20080084167A
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KR
South Korea
Prior art keywords
layer
film
forming
conductive
insulating film
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Application number
KR1020070025487A
Other languages
Korean (ko)
Inventor
이혜령
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070025487A priority Critical patent/KR20080084167A/en
Publication of KR20080084167A publication Critical patent/KR20080084167A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a transistor of a semiconductor device is provided to improve the driving capability of a transistor by guaranteeing more drain current. A first conductive layer(202) is formed on a semiconductor substrate(200). An ion implantation process can be performed to form a well junction(204) in the first conductive layer. An ion implantation process for controlling a threshold voltage can be performed to form a threshold voltage control layer(206) in the well junction. The first conductive layer and the semiconductor substrate are partially etched to form a trench. An isolation layer is formed in the trench to have a step with the first conductive layer. An insulation layer is formed on the first conductive layer and the isolation layer. A second conductive layer(212) is formed on the insulation layer. The second conductive layer and the insulation layer are etched to form a gate(216).

Description

Method of manufacturing a transistor in semiconductor device

1 is a layout view of a device illustrated to explain a semiconductor device according to an embodiment of the present invention.

2A to 2F are sectional views showing a state taken along the line A-A of FIG.

3A to 3F are cross-sectional views illustrating a state in which line B-B of FIG. 1 is cut away.

<Description of the symbols for the main parts of the drawings>

200 semiconductor substrate 202 first conductive film

204 well junction 206 threshold voltage regulating layer

208: device isolation film 210: second insulating film

212: second conductive film 214: tungsten silicide film

216: gate 218: source and drain junction

The present invention relates to a method for manufacturing a transistor of a semiconductor device, and more particularly, to a method for manufacturing a transistor of a semiconductor device for increasing the channel width.

As devices become more integrated, gate lengths and widths are reduced due to shrinking devices. Higher integration of the device can increase the device's drain current and reduce parasitic capacitance, improving the device's operating speed.

However, a device having a short channel length has characteristics of a device having a long channel length, but a short channel effect occurs due to its structural characteristics.

In addition, as the gate length is shortened due to the reduction of the device, the threshold voltage (Vt) decreases, the breakdown voltage (BV) decreases, the saturation velocity occurs, the punch through occurs, the hot Problems such as reducing the Hot Carrier occur. Therefore, there is a limit to reducing the gate length by miniaturization of the device.

In addition, the gate width must be reduced by reducing the device, and reducing the gate width causes problems such as a narrow width effect, an inverse narrow width effect, and a hump.

According to the present invention, a conductive film is formed on an upper surface of a semiconductor substrate, the conductive film is used as an active material, and an insulating film is formed to surround the exposed conductive film surface, and the insulating film is used as a gate insulating film to effectively increase the channel length to improve transistor driving ability. Can be.

In the method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention, a first conductive film is formed on a semiconductor substrate. A trench is formed by etching the first conductive film and a portion of the semiconductor substrate. An isolation layer is formed in the trench so as to have a step with the first conductive layer. An insulating film is formed over the first conductive film and the device isolation film. A second conductive film is formed over the insulating film. The second conductive film and the insulating film are etched to form a gate.

In the above, after forming the first conductive film, an ion implantation process is performed to form a well junction in the first conductive film, and a threshold voltage adjusting layer is formed in the well junction by performing an ion implantation process for adjusting the threshold voltage. The insulating film is used as the gate insulating film of the semiconductor element.

In the insulating film forming process, a photoresist pattern is formed on the device isolation layer to expose the upper portion of the first conductive layer and both ends of the device isolation layer, and then an insulating film is formed on the upper portion of the first conductive layer and a portion of both ends of the device isolation layer exposed by the photoresist pattern. Then, the photoresist pattern is removed.

In the insulating film forming process, an insulating film is formed on the first conductive film and the device isolation film, and then a photoresist pattern is formed on the semiconductor substrate including both ends of the first conductive film and the device isolation film so that the center portion of the device isolation film is exposed. After etching the etching mask insulating film, the photoresist pattern is removed.

The insulating film is formed of an oxide or nitride film or a laminated film in which an oxide and a nitride film are laminated. The insulating film is formed to a thickness of 20 kPa to 400 kPa.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view of a device illustrated to explain a semiconductor device according to an embodiment of the present invention.

The active 100 and the field region 102 are defined by an isolation layer formed in a predetermined region of the semiconductor substrate. A gate 104 having a structure in which an insulating film, a first conductive film, and a second conductive film are stacked in a direction crossing the active region 100 and the field region 102 is formed.

2A to 2E are cross-sectional views illustrating a state AA taken along the line AA of FIG. 1, and FIGS. 3A to 3E are cross-sectional views illustrating a state taken along the line BB of FIG. 1, in which a floating gate and a control gate are stacked in a cell region. A method of forming a transistor in a low voltage NMOS region of a peripheral circuit region while a gate is formed is described.

2A and 3A, a first conductive layer 202 is formed on the semiconductor substrate 200. At this time, the first conductive film 202 is formed of a polysilicon film. By forming the first conductive layer 202 on the semiconductor substrate 200 without the gate insulating layer forming process, the first conductive layer 202 serves as an active region.

2B and 3B, the well junction 204 is formed in the first conductive layer 202 by performing an ion implantation process, and then an ion implantation process for adjusting the voltage threshold (Vt) is performed to perform well junction ( A threshold voltage regulation layer 206 is formed in 204. At this time, in the ion implantation process for adjusting the threshold voltage Vt, the dopants B 11 and F 19 are used.

2C and 3C, the first conductive layer 202 and a portion of the semiconductor substrate 200 are etched by an etching process to form a trench for device isolation, and then the semiconductor substrate 200 including trenches to fill the trenches. A first insulating film is formed on the upper portion. In this case, the first insulating layer is formed by stacking a PSZ (polysilazane) material and a high density plasma (HDP) oxide film in order to improve the embedding characteristics at a high aspect ratio.

Then, a chemical mechanical polishing (CMP) process is performed such that the first insulating film remains only in the trench to form the device isolation layer 208. After forming a mask (not shown) on the semiconductor substrate 200 including the first insulating layer and the isolation layer 208, an etching process is performed to adjust the effective field height (EFH), which is the height of the isolation layer 208. . As a result, a part of the sidewall of the first conductive film 204 is exposed.

2D and 3D, a second insulating layer 210 is formed on the exposed surface of the first conductive layer 202. At this time, there are two methods of forming the second insulating film 210.

First, a photoresist pattern (not shown) is formed on the device isolation layer 208 so that the upper portion of the first conductive layer 202 and a portion of both ends of the device isolation layer 208 are exposed, and then a second insulating layer is formed on the surface of the well junction 204. Form 210. In this case, the second insulating film 210 may be formed of Oxide-Nitride-Oxide (ONO), but the second insulating film 210 does not have to be thick because it serves as a gate insulating film. Therefore, the second insulating film 210 is preferably formed to a thickness of 20 kPa to 400 kPa using an oxide or nitride film or a laminated film in which oxides and nitride films are laminated. Remove the photoresist pattern.

Second, after forming the second insulating film 210 on the first conductive film 202 and the device isolation film 208, the first conductive film 202 and the device isolation film 208 so that the central portion of the device isolation film 208 is exposed. A photoresist pattern (not shown) is formed on the semiconductor substrate 100 including both ends. In this case, the second insulating film 210 may be formed of Oxide-Nitride-Oxide (ONO), but the second insulating film 210 does not have to be thick because it serves as a gate insulating film. Therefore, the second insulating film 210 is preferably formed to a thickness of 20 kPa to 400 kPa using an oxide or nitride film or a laminated film in which oxides and nitride films are laminated. After etching the second insulating layer 210 using the photoresist pattern as an etching mask, the photoresist pattern is removed.

Here, the second insulating layer 210 is formed to surround the surface of the well junction 204, and since both the upper sidewall and the sidewall of the well junction 204 are used as channel regions, the channel width W may be increased compared to the conventional one. .

2E and 3E, the second conductive layer 212 and the tungsten silicide layer WSix 214 are sequentially formed on the second insulating layer 210. At this time, the second conductive film 212 is formed of a polysilicon film. In the conventional transistor, since the first conductive film and the second conductive film formed on the upper and lower portions of the dielectric film do not need to be separated from each other, the first conductive film and the second conductive film formed on the upper and lower portions of the dielectric film are connected through the dielectric film contact. . However, in the present invention, the second insulating film 210 formed on the first conductive film 202 serves as a gate insulating film, and the second conductive film 212 serves as a floating gate, thereby forming a dielectric film contact. No step needed.

2F and 3F, the tungsten silicide layer (WSix) 214, the second conductive layer 212, and the second insulating layer 210 are etched to form the gate 216, and then an ion implantation process is performed. The source and drain junctions 218 are formed in the first conductive film 202 on both sides.

As described above, the first insulating film 202 is formed on the semiconductor substrate 200 to actively use the first conductive film 202, and surround the exposed surface of the first conductive film 202. By forming the 210 and using the second insulating film 210 as the gate insulating film, the channel width W can be effectively increased. The driving ability of the transistor can be improved by increasing the channel width W to secure more drain current.

In addition, by forming the second insulating film 210 to surround the exposed surface of the first conductive film 202 to effectively increase the channel width W, a narrow width effect occurs at a narrow width. Problems such as the inverse narrow width effect and the hump can be solved.

In addition, as the channel length is increased compared to the conventional transistor, it is possible to secure a margin for reducing the active width.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the effects of the present invention are as follows.

First, the first conductive film is formed on the semiconductor substrate to use the first conductive film as an active material, the second insulating film is formed to surround the exposed first conductive film surface, and the second insulating film is used as the gate insulating film to effectively use the channel width. Can be increased.

Second, the driving ability of the transistor can be improved by increasing the channel width to secure more drain current.

Third, by forming a second insulating film to cover the exposed surface of the first conductive film to effectively increase the channel width, the narrow width effect and inverse narrow width that occur at the narrow width Problems such as effects, humps, etc. can be solved.

Fourth, the margin of the active width can be reduced by increasing the channel length compared to the conventional transistor.

Claims (7)

Forming a first conductive film on the semiconductor substrate; Etching a portion of the first conductive layer and the semiconductor substrate to form a trench; Forming an isolation layer in the trench so as to have a step with the first conductive layer; Forming an insulating layer on the first conductive layer and the device isolation layer; Forming a second conductive film on the insulating film; And And forming a gate by etching the second conductive layer and the insulating layer. The method of claim 1, After forming the first conductive film Performing an ion implantation process to form a well junction in the first conductive film; And And forming a threshold voltage regulating layer in the well junction by performing an ion implantation process for adjusting the threshold voltage. The method of claim 1, And the insulating film is used as a gate insulating film of a semiconductor device. The method of claim 1, The insulating film forming process Forming a photoresist pattern on the device isolation layer to expose the first conductive layer and portions of both ends of the device isolation layer; Forming an insulating layer on an upper portion of the first conductive layer exposed by the photoresist pattern and a partial region of both ends of the device isolation layer; And And removing the photoresist pattern. The method of claim 1, The insulating film forming process Forming the insulating layer on the first conductive layer and the device isolation layer; Forming a photoresist pattern on the semiconductor substrate including both of the first conductive layer and the device isolation layer to expose a central portion of the device isolation layer; Etching the insulating layer using the photoresist pattern as an etching mask; And And removing the photoresist pattern. The method of claim 1, And the insulating film is formed of an oxide or a nitride film or a laminated film in which an oxide and a nitride film are laminated. The method of claim 1, The insulating film is a transistor manufacturing method of a semiconductor device to form a thickness of 20 ~ 400Å.
KR1020070025487A 2007-03-15 2007-03-15 Method of manufacturing a transistor in semiconductor device KR20080084167A (en)

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KR1020070025487A KR20080084167A (en) 2007-03-15 2007-03-15 Method of manufacturing a transistor in semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103688A (en) * 2013-04-10 2014-10-15 三星电子株式会社 FIN-FET transistor with punchthrough barrier and leakage protection regions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103688A (en) * 2013-04-10 2014-10-15 三星电子株式会社 FIN-FET transistor with punchthrough barrier and leakage protection regions

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