KR20080081082A - Reliability of vias and diagnosis by e-beam probing - Google Patents

Abstract

Electronic devices, such as IC devices, are tested by determining a failure net within the electronic device that is causing a device failure. After identifying the failure net, the failure net is locally stressed. The stress is applied so that only the net being tested is subjected to the stress, and the remaining nets and components of the device are not stressed. A change in a signal produced by the failure net is observed while the failure bet is being subjected to the stress. The testing in this manner assists in identifying the failure net as a failure source of the device.

Description

RELIABILITY OF VIAS AND DIAGNOSIS BY E-BEAM PROBING}

The present invention relates to testing of electronic devices. In particular, the present invention relates to monitoring the net to determine if the net in the device is a source of failure.

Due to the increased complexity and packaging of chips used in electronic devices, the geometric size of the devices is rapidly decreasing. Currently, the geometric size in electronic devices is moving from 0.18 μm to 0.13 μm as small. The trend towards smaller geometrical dimensions of the device is expected to continue in the future. As the geometry of the device increases, the problems associated with the testing device and the debugging device continue to be more and more difficult to solve.

To eliminate some of the difficulties of testing these small geometric sizes, designers make extensive use of simulation and design inspection software to eliminate design problems before fabricating the device. While simulation and inspection software identify some pre-fabrication problems, many designs cannot produce fully operational parts through the entire specification without first considering length, cost, and debug aspects. In addition, even if all of the design problems are identified and corrected prior to manufacture, defects can enter the device during the manufacturing process.

During the testing and debugging process, probing devices for the device's internal nets become increasingly useful. Probing of the device's internal nets helps to identify and isolate parts inside the device that are not performing properly. One technique used to access internal nets is to include pads on some "important" internal nets during device design, thereby accessing these nets during testing and debugging. However, the majority of internal nets do not have pads and therefore cannot directly access these nets.

Packaging density and chip complexity limit the device designer's placement of pads on internal nets due to space constraints within the device. In particular, this is true for very large scale integrated circuits (VLSIs) such as gate arrays, field programmable gate arrays (FPGAs), and application specific integrated circuits (ASICs) such as mixed signal integrated circuits. Lack of direct access to all of the device's internal nets complicates test and debug processing.

Certain features of the device layout further increase the complexity of testing and debugging. For example, at the bottom of a trench or via, it is very difficult to detect a bond, such as a manufacturing defect. Typically, defect detection at the bottom of trenches or vias requires failure analysis of the device using means such as electron microscopes. In addition, intermittent defects such as stress associated with intermittent defects are particularly difficult to find due to their non-repetitive nature.

Several techniques are involved in testing and debugging electronic devices. Some of these techniques include functional testing, burn-in testing, and defect detection.

Typically, functional testing is used to verify proper operation of the electronic device. For example, the IC can be functionally tested after completion of the IC manufacturing process. Test leads, or probes, are connected to the input / output (I / O) pins of the IC. Test probes are applied to the input pins of the IC and the output pins of the IC are monitored to determine if the expected signals are produced. Typically, the functional test is performed under normal environmental conditions, so that the device under test is not exposed to any type of external stress, for example environmental stress such as high temperature.

Another technique used to test and debug electronic devices is burn-in testing. Typically, a burn-in test of a device involves the operation of raising the ambient temperature of the powered device. The burn-in test stresses the entire device, including all nets in the device. Because of the environment under which the device is tested, it is not practical to not encapsulate the device to expose the internal nets of the device due to environmental factors such as condensation of the device. In addition, even if the device's internal nets are not encapsulated to access the device's internal nets, the entire device and all nets are not stressed the same, which makes it difficult to identify individual net defects through burn-in tests.

The third technique, fault detection technology, probes the device's internal nets as well as monitors the device's I / O pins. Typically, probing the internal nets of the device requires accessing the internal nets without encapsulating the device. If the device is not encapsulated, environmental stressing of the unencapsulated device can be impractical.

One technique used to probe inner nets uses mechanical probes. Mechanical probes are aligned to physically contact the internal net of the device. One disadvantage of using mechanical probes is that they can load the net of the electrical circuit to be tested. For example, mechanical probes increase the capacitance of the circuit, which can distort the measurement performance of the circuit in that the circuit can be tested without the additional load of mechanical probes.

The technology developed to remove the load on the device circuit under test is an e-beam probe. Recently developed e-beam probe tools and techniques have greatly helped to overcome some of the problems involved in probing internal nodes of electronic devices for debugging and other purposes.

E-beam probing uses the principle of voltage contrast of a scanning electron microscope (SEM). Conventional SEM images are generated by raster scanning a beam of finely concentrated primary electrons with respect to the device under test when signals are applied to the device. Secondary electrons are generated when the primary beam is reflected from the device under test. The secondary electrons reflected from the device are measured and an image of the nets of the device under test is generated using a scintillator, a photo-multiplier tube (PMT) and related electronics. The energy of the secondary electrons generated by the device under test is due to the change in electrical potential on the surface of the conductors, ie the nets, in the device. Secondary electrons impinging on the surface of the scintillator produce a plurality of photons proportional to the energy of the secondary electrons, which photons are emitted from the scintillator and collide with the surface of the PMT. The PMT outputs a voltage proportional to the plurality of photons impinging on its surface. The voltage from the PMT is amplified by the associated electronics and used to generate an image corresponding to the electrical potential on the surface of the conductors and nets in the device. In this way, e-beam technology displays node voltages.

For example, positive voltages may appear as dark areas in the image in response to a low secondary electron count. Zero, that is, negative voltages may appear as bright areas in the image in response to a higher secondary electron count.

e-beam probing offers several advantages over other probing techniques, such as mechanical probing. Typically, e-beam probes are passive in that they do not interact or load with the monitored electrical circuits. In contrast, as described above, mechanical probes put a load on the circuit under test, making the measurement inaccurate.

What is needed is an effective way to monitor the operation of internal nets of an electronic device without identifying specific nets that may affect the operation of the device or may be a bad source.

A method of identifying a defective net in an IC where the output of the IC indicates an IC failure comprises determining a potential defective net by observing a signal generated by the defective net, wherein the IC does not affect other IC nets. Stressing a potential bad net, and observing a change in the signal generated by the potential bad net in response to the stress to identify the potential bad net as a bad net of the IC.

Stretching a net in a device, i.e. an IC, includes: aligning an external stress source with the net, applying stress to the net without affecting other device nets, and while the net is stressed. Monitoring the net while stress is applied to determine if the net is bad.

Locally stretching the net in the device, i.e., the IC, may include aligning the e-beam probe with the suspected net in the device. Once the e-beam probe is aligned with the suspected net, the current in the e-beam is increased to locally stress the device near the suspected net.

An effective method is provided for monitoring the operation of internal nets of an electronic device without identifying specific nets that may affect the operation of the device or may be a bad source.

Other features and advantages of the invention can be understood from the detailed description of the preferred embodiment, which shows, by way of example, the principles of the invention.

In conventional integrated circuit (IC) electronic devices, such as very large scale integration (VLSI) chips, there are many interconnects and vias inside the device. The mechanical probe does not provide direct access to the majority of the internal connections and vias of the IC. It is not practical to identify a fault in a particular net without monitoring the nets of the IC while testing the device by the test signal. The initial step in the failure analysis of the device is to determine the location of the failure. As mentioned above, internal nets must be probed. Mechanical probes can impose a load on the electrical circuit to be monitored, making inaccurate or non-repetitive measurements. Thus, there is a need for a contactless and repeatable measurement technique for monitoring the internal nets of a device.

One kind of contactless and repeatable measurement unit for monitoring the internal nets of the device is an electronic-beam probe. Typically, the e-beam probe is installed in a positioning device that incorrectly aligns the e-beam with the desired net in the device. If the positioning device controller accesses the device layout database, the positioning device may automatically place pre-identified nets in the device. Normally, good alignment of the e-beam is achieved by focusing coils, or objective lenses, as described below.

In addition, when monitoring the internal net, it is desirable to apply local stress to the device, for example only one net of the device under test. By straining only the desired net without affecting other nets, the failure mode of the device can be identified and identified. For example, in the case where individual nets have defects that depend on temperature, by stretching individual nets, it is possible to reliably determine whether the stretched nets are a source of failure.

1 is a diagram of a portion of a test device 102 and a test device exhibiting characteristics in accordance with the present invention. A portion of the device 102 under test is shown, showing a plurality of internal nets and vias. As described below, one of the nets was identified as a potential bad net 104 and the other ie the remaining nets 106 were considered to be operating satisfactorily. Applying test stimuli to the I / O pins of the device 102 under test changes the signals on the nets 104, 106 accordingly.

In one embodiment, the signals on the potentially bad net 104 are monitored using a contactless measuring device 110, for example an e-beam probe. In addition, the stress source 112 is aligned with the defective net 114. The stress source is configured to apply a stress source such as, for example, temperature, current, or voltage.

In another embodiment, the stress source uses mechanical probes configured to minimize any load on the electrical circuit to apply stress. In another embodiment, the stress source uses contactless probes such as e-beam or laser light to apply stress.

In another embodiment, the stress source 112 and the contactless measurement device 110 are the same units as a single e-beam probe, for example configured to apply stress as well as to monitor for potential bad nets. For example, the current density of the primary beam from the e-beam probe can be increased from a normal value of about 1 nAmp used to monitor the net to a value of about 50 nAmps used to apply stress. In contrast to using e-beam probes conventionally, when increasing the current density in an e-beam probe, the probe is no longer a passive monitoring device. Instead, the e-beam probe actively interacts with the net by monitoring the secondary signal reflected from the net while simultaneously stressing the net locally. In all these embodiments, the net is run by a test input and monitored while stressing a potential single bad net.

In accordance with the present invention, various back-trace techniques can be used to identify potential rogue nets. The back-trace technique is, for example, a systematic test of nets starting at the location of a device having a failure found during a functional test at the output of the device, ie the identified failure. For example, after detecting a failure at an output node of a portion of the electrical circuit, the input nets of the portion of the electrical circuit are tested. After all input nets of a portion of the electrical circuit have been tested as "good", the defect identified in that portion of the electrical circuit is isolated. If one or more input nets are identified as bad in part of the electrical circuit, the electrical circuit that is the source of the bad input net is retested. Continue testing until the defective part of the electrical circuit is separated.

2 is a schematic diagram of an exemplary circuit of an IC device 200 showing a back-trace technique applied to identify a net. In order to represent an unstable digital circuit in an IC, for example, a VLSI device with mixed signals is described. In FIG. 2, the digital value measured on the net 204 and output by the register 202 indicates a circuit failure. Monitor the input signals and nets 206, 208, 210, 212, and 214 of register 202 to determine if a failure is in register 202 or net 204. In this example, net 214 has a failure, but nets 206, 208, 210, and 212 are satisfactorily tested. Since the net 206 is satisfactorily tested, the circuit device 220 provided to the net 206 and the nets provided to the circuit device 220 are not additionally tested. The nets provided to the circuit device 222 are tested to determine whether the net provided to the circuit device 22 is defective or whether the circuit device 222 generates a failure.

Inputs of circuit arrangement 222 are nets 230, 232, 234, and 236. In this example, nets 230, 232, and 234 are successfully tested and net 236 is bad. Since the nets 230, 232, and 234 have been successfully tested, no additional testing is done for the circuits provided to these nets. Since the net 236 is defective, the nets provided to the circuit device 240 are tested to determine whether the nets provided to the circuit device 240 have a defect or whether the circuit device 240 causes the defect.

Inputs of circuit arrangement 240 include nets 250, 252, and 254. In this example, the nets 250, 252, and 254 are successfully tested. Thus, the back-trace test isolates failures in either the circuit arrangement 240 or the net 236. In order to determine whether the circuit device 240 is bad or the net 236 is bad, the net 236 without stressing the circuit device 240 or any other circuit devices in the IC device 200, i.e., the nets. Perform additional tests that locally stress). By stretching the net 236, the failure for the individual net 236 can be isolated.

As mentioned above, the reliability of the via structures of VLSI devices is a major concern in the manufacture of semiconductor devices. In particular, high levels of failure can occur in tungsten via structures in aluminum alloy interconnect systems. As mentioned above, failure analysis of via defects continues to be requested. Next, features of the present invention will be described with respect to failure analysis performed on an unstable digital circuit that generates intermittent failure in a mixed signal VLSI device. The failure analysis for this device shows that the via structure contains a void and an anomalous thin layer under the Ti / TiN adhesion layer at the interface of the tungsten plug and the underlying AlCu alloy.

Unstable digital circuitry is part of a mixed signal device that includes digital and analog circuitry. The device is mounted on the field after passing wafer probing and final testing. In that field, the device exhibited intermittent failures. The device was returned from the field and conventional failure analysis was performed. Many manual probing techniques were used with no success in analyzing failure modes. As mentioned above, a problem with mechanical probing is that the mechanical probe puts a load on the electrical device under test. Loading the circuit under test produces inadequate and unreliable test results. In order to remove the load produced by the mechanical probes, a non-contact technique using an e-beam probe according to the invention has been implemented to perform a failure analysis of the device.

3 is a block diagram of a test station 300 used in accordance with the present invention. The test station includes an e-beam probe unit 302 such as schlumberger IDS10000plus. The test station not only includes a workstation 303 used by the test operator to control test equipment, but also visually displays the test results to the operator.

The e-beam probe unit 302 includes a load module 304 that holds the device under test and is electrically connected to the I / O pins of the device. After the device under test is installed in the load module 304, the load module 304 is secured to the sample chamber lid 306. Before installing the device under test to the load module 304, remove the upper portion of the encapsulation portion from the device. This exposes the internal structure of the device, including internal nets. When the rod module 304 is secured to the specimen chamber 306, the device under test is arranged to face downward, with respect to the exposed internal structure that faces the specimen chamber 308.

At the bottom of the sample chamber 308 are two ion pumps 310, 312. Ion pumps 310 and 312 are used to vacuum the inside of the sample chamber. At the end of the specimen chamber 308 opposite the device under test, an e-beam column 320 is present. As described below, the e-beam column generates an electron beam that is focused on the device under test to monitor the voltage of the internal nets of the device. The e-beam column 320 and ion pumps 310, 320 are installed in the XY stage 322. XY stage 322 incorrectly aligns the electron beam generated by the e-beam to the internal net of the device under test.

4 is a block diagram illustrating additional details of the e-beam column 320. The e-beam column 320 includes a filament 402. The filament 402 generates electrons used to generate the e-beam. Electrons emitted by the filament 402 are accelerated toward the device 102 under test by the electrostatic lens 404. After the electrons pass through the electrostatic lens 404, the electrons are concentrated in the beam by the condenser lens 408. The electron beam passing through the condenser lens 408 travels through the vacuum in the specimen chamber towards the device 102 under test.

When the electron beam approaches the device 102 under test, the electron beam passes through the objective lens 410. The objective lens 410 focuses the electron beam onto the primary electron beam that is directed to the desired internal net of the device 102 under test. The primary electron beam interacts with the inner net of the device 102 under test, and the secondary electrons are emitted back to the specimen chamber.

The detector 420 is disposed between the condenser lens 408 and the objective lens 410. The detector 420 has a scintillator 422. The scintillator 422 emits photons in proportion to the energy of the secondary electrons when the secondary electrons impinge on their surface. Photons emitted by the scintillator 422 are sent to a photomultiplier tube (PMT) 424. The PMT 424 is configured to generate a voltage in proportion to the number of photons that strike the surface. Thus, the PMT 424 output voltage is proportional to the energy of the secondary electrons emitted by the internal net of the device under test. Thus, the PMT 424 output voltage is sent to an amplifier 426 that amplifies and conditions the signal. The amplifier 426 signal output is routed to the workstation 300 that processes it and displayed to the operator.

As described above, the displayed image is an image showing the change in intensity of the secondary beam due to the electrical potential of the surface of the conductors, ie the nets, in the device. For example, positive voltages may appear as dark areas in the image, corresponding to a low secondary electron count. Zero, that is, negative voltages may appear as bright areas in the image, corresponding to high secondary electron counts.

The test setup described above is used to test a defective mixed signal device. By using back-trace techniques using e-beam probes, there is less device failure in the individual 8-bit right shift registers used for digital data input. An additional test shows that the data signals from the 8-bit register failed to match the pre-assigned IC codes. The failure of the signals from the 8 bit register is believed to cause the malfunction of the device.

To help identify the failure mechanism of the device, all register related nets were measured using an e-beam probe. By the e-beam probe test, it can be seen that two phase clock generators in the digital circuit produce irregular waveforms. 5 is a graph showing output waveforms of a conventional two phase clock generator and a clock generator under test. Traces 510, 512 represent sufficient clock generator output signals from known good apparatus. Traces 520 and 522 represent the output signals of the clock generator under test. Trace 522 is irregular and closer to a triangle than to the expected square wave shape.

Additional e-beam probing of all internal nets of the clock generator concentrates the defect on the output inverter (buffer) of the defective clock generator.

After identifying the defective output inverter as a possible failure, the nets of the output inverter were locally strained. Techniques used to locally strain the nets used in this example include techniques for increasing the current in the e-beam and techniques for increasing the electron flux of the e-beam. During the testing of the mixed signal device, the test station 300 was operated to increase the current of the e-beam from approximately 1 nAmp to monitor the net and from about 50 nAmps to strain the net. Also, the larger e-beams through the objective lens 410 of the e-beam column 320 are used to concentrate the e-beams in a small area of the net, thus increasing the electron flux.

Traces 530, 532 represent clock generator output signals during local thermal stress. As indicated by the traces 530, 532, it can be seen that when thermally stressed, it no longer oscillates and the clock generator output is severely distorted.

The simulation was performed using the high via resistance of the output net of the faulty inverter. The simulation produces a signal similar to triangular trace 522 as measured with an e-beam probe. Further simulation increases via resistance to very high values, and an inverter output similar to traces 530, 532 stops switching. Since the traces 530, 532 are made when the net is under thermal stress, it has been found that the thermal stress increases the net resistance to a very high value.

6 is an illustration of the portion of the device around the bad net. The net includes two vias 601, 602. It can be seen that vias are the cause of the high resistance.

Thereafter, bonding pads were placed across the vias 601, 602 that were suspected of failure using focused ion beam (FIB) technology. It was found that the resistance of both ends of the beer was very high. Additional failure analysis was performed using a scanning electron microscope (SEM) and one of the suspected vias 601, 602 was identified as a defective via. 7 is an SEM photograph of a via of suspected bad. 7 shows a void 702 of about 0.2 μm in the Al-alloy under the tungsten layer.

Further failure analysis was performed on vias suspected of failure using a tunneling electron microscope (TEM). 8 is a TEM photograph of a via suspected of a failure near the tungsten-metal interface. 8 shows a very thin biphasic layer 802 of about 150 angstroms under the Ti / TiN adhesion layer underneath the tungsten plug. During the manufacturing process, it was found that the bilayer was aluminum oxide produced by DI (de-ionized) solution consumption during the via cleaning process after via etching.

Poor tungsten-metal interface results in via delamination and improves localized thermal stress. In addition, a poor tungsten-metal interface can accelerate the formation of voids in the AlCu alloy under the tungsten plug during high temperature treatments or local electrical thermal stressing. Forming voids in the Al-alloy under the tungsten layer is explained by the discontinuity of the Al flux at the tungsten-AlCu interface. For example, Al flux deviating from the thermal region may not be compensated from the tungsten plug during electron transfer.

The voids and abnormal thin layers of the tungsten-AlCu interface can be greatly reduced in tungsten-AlCu interconnect systems. This reduction may cause either permanent device failure or intermittent malfunction, depending on the amount of electrical thermal stress and the amount of reduction in the interconnects affected during the application environment or any test. Especially for current semiconductor processing technologies, tungsten-AlCu interconnect system has one important reliability problem in VLSI devices.

In the device under test described in the above example, new via cleaning treatments were implemented by the manufacturer in order to reduce DI solution consumption and to minimize thermal stress inducing voids in tungsten-AlCu interconnect systems. Improved reliability of via interconnects changed during processing. To date, no similar intermittent device failures have been observed. Thus, the technique can successfully identify faulty sources in a mixed signal device and initiate appropriate corrective action based on the results of separate circuit stress and net monitoring.

The foregoing description details certain embodiments of the invention. However, although detailed description above, it can be seen that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics. Since the above-described embodiments are merely illustrative in all respects and not restrictive, the scope of the present invention is indicated by the appended claims rather than the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

1 is a diagram of a device under test and a portion of a test device showing characteristics of a system constructed in accordance with the present invention.

2 is a schematic diagram of a sample circuit showing a back-trace.

3 is a block diagram of a test station used in accordance with the present invention.

4 is a block diagram illustrating additional details of an e-beam column.

5 is a graph showing the output waveforms of a conventional two phase clock generator and a clock generator under test.

6 is an illustration of a portion of a device around a bad net.

7 is a scanning electron microscope (SEM) picture of vias suspected of defective.

FIG. 8 is a TEM (tunneling electron microscope) photograph of a via suspected to be defective near the tungsten-metal interface.

Claims (6)

A method for identifying a defective net whose output indicates an IC failure in an IC device, Determining a potential bad net by observing a signal generated by the net indicating the bad, further comprising performing a back-trace of the net in the IC device. Determining; Stressing the potential bad net without affecting other IC device nets; And Observing a change in the generated signal that identifies the potential bad net as a bad net of the IC device by observing a change in the signal generated by the potential bad net in response to the stressing. But Straining the potential bad net, Aligning an external stress source with the potential bad net; And Applying stress to the potential bad net, And the observing step is performed by the external stress source. The method of claim 1, And the external stress source is an e-beam probe. The method of claim 2, And applying the stress further comprises increasing the current of the first electron beam of the e-beam probe to 50 nA. The method of claim 2, The step of applying the stress further comprises increasing the size of the first electron beam of the e-beam probe to increase the electron flux. The method of claim 1, And the IC device is a mixed signal integrated circuit. The method of claim 1, And performing back-trace of the net in the IC device further comprises using an e-beam probe.

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