KR20080079053A - A semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to increase a potential difference between global I/O line pair signals by maintaining a discharge state of a global I/O line signal and pulling up a global I/O line bar signal. A memory cell(11) outputs data to a bit line pair. A bit line sense amplifier(13) amplifies a voltage difference between the bit line pairs and outputs the amplified result to a first I/O line pair. A second sense amplifier(15) receives the data from the first I/O line pair, amplifies the voltage difference in response to a first sense amplifier enable signal, and outputs the result to a second I/O line pair. An I/O line precharging unit(16) precharges a second I/O line pair to a precharge voltage level in response to an I/O line precharge signal. An I/O line pull-up circuit(100) receives output signal pairs from the I/O line precharging unit, and pulls up a level of a higher output signal from the output signal pairs of the I/O line precharging unit in response to a second sense amplifier enable signal.

Description

Semiconductor memory device {A SEMICONDUCTOR MEMORY DEVICE}

1 is a schematic block diagram of a data output path of a conventional semiconductor memory device.

2 is a schematic block diagram of a data output path of the semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram of a local sense amplifier in the data output path of the semiconductor memory device of the present invention shown in FIG.

4 is a simulation timing diagram illustrating an output waveform of a bit line sense amplifier in the semiconductor memory device data output path of the present invention.

5 is a simulation timing diagram illustrating output waveforms of a local input / output sense amplifier in the semiconductor memory device data output path of the present invention in comparison with the prior art.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a local input / output sense amplifier for stably operating by minimizing the layout area of a semiconductor memory device core while preventing the operation speed of the semiconductor memory device from decreasing. It is about.

The semiconductor memory device includes a plurality of memory cells to store data or read stored data in the memory cells. In the semiconductor memory device, in order to read data stored in a memory cell, a sense amplifier is used to receive a small signal, determine a voltage or current level, and transfer the same to an output pin.

The data of the memory cell is input to the bit line sense amplifier through the bit line, and the voltage level is sensed and amplified. Generally, when a word line is enabled by the RASB command, all memory cells connected to the memory cell are connected to the bit line sense amplifier. Data is transferred to the corresponding bit line. Data of the memory cells connected to the enabled word line is charged share to the bit lines to increase or decrease the voltage level of the bit lines little by little.

The bit line of each memory cell adjacent to these bit lines is called a "bit line bar", which maintains the voltage level precharged to the initial bit line voltage.

The bit line and the bit line bar are connected to the bit line sense amplifier with a predetermined voltage difference, and the voltage difference becomes wider according to the operation of the bit line sense amplifier. The output lines of the bit line sense amplifiers, that is, the bit lines, are selected by a column selection circuit activated by a CASB active command and are connected to the data input / output lines. The output of the bit line sense amplifier transferred to the data input / output line is amplified again by the input / output sense amplifier, for example, the current sense amplifier, and then output to the pad through the output driving circuit.

1 is a schematic block diagram of a data output path of a conventional semiconductor memory device, which includes a memory cell 11, a bit line sense amplifier 13, a local input / output sense amplifier 15, and a global input / output line precharge unit 16. And an input / output sense amplifier 18 and an output buffer 19.

An operation of a data output path of a conventional semiconductor memory device will be described with reference to FIG. 1.

When the word line is enabled by applying the row address first, the bit line sense amplifier 13 amplifies a voltage corresponding to the charge stored in the memory cell 11.

Subsequently, when a column address is applied together with a read command, the designated column select line CSL is enabled and the bit line sense amplifier 13 amplifies the data carried on the bit line BL pair so that local input / output line pairs LIO and LIOB are amplified. )

 When the local I / O sense amplifier 15 receives data amplified in the local I / O line pairs LIO and LIOB, amplifies and outputs the data to the global I / O line pairs GIO and GIOB, the global I / O line precharge unit 16 receives the I / O sense amplifier. Before the enable signal IOSA_EN is applied, both outputs of the local input / output sense amplifier 15 are charged to the power supply voltage VCC level in advance, and when the global input / output line precharge signal GIO_pre is applied to the low level, the local input / output is performed. Both outputs of the sense amplifier 15 are discharged.

The input / output sense amplifier 18 receives the output of the local input / output sense amplifier 15 through the global input / output line pairs GIO and GIOB, amplifies the current level, and outputs the output buffer 19 to the power supply voltage VCC level. And the output signal of the input / output sense amplifier 18 having the ground voltage VSS level is delayed by a predetermined time and outputs the buffered read data to the data input / output pin DQ.

In this case, the local input / output sense amplifier 15 may be configured to include a relatively small loading local input / output line pair (LIO, LIOB) and a large global input / output line pair in the case of a semiconductor memory device having a long global input / output line pair (GIO, GIOB) or a low operating voltage. It is additionally provided between the pairs GIO and GIOB to overcome the problems of the load mismatch and to prevent the operation speed from decreasing, thereby serving to stably operate the semiconductor memory device.

In the semiconductor memory device using the local input / output sense amplifier 15, each of the sense amplifiers is introduced after the global input / output line pairs GIO and GIOB or the local input / output line pairs LIO and LIOB have been sufficiently developed. After the read or write operation is completed, each input / output line pair must be precharged for the next read operation.

However, the local input / output sense amplifier 15 primarily detects the data on the local input / output line pairs LIO and LIOB and develops the data as much as possible to load the data into the global input / output line pairs GIO and GIOB having a large capacitance. Most of the input / output line data sensing methods used in the related art have been in the form of NMOS differential amplifiers.

This method consists of NMOS transistors to minimize the layout area of the semiconductor memory device core and pulls down all the local input / output line pairs (LIO and LIOB).

However, this approach is slower, less gainy, and less expensive than the full up-pull down method using CMOS transistors. Since data on (GIO, GIOB) is applied to the input / output sense amplifier 18, there is a problem that the gain of the input / output sense amplifier 18 is also lowered.

SUMMARY OF THE INVENTION An object of the present invention is to minimize the layout area of a semiconductor memory device core and simultaneously pull down the voltage level in a local input / output sense amplifier of a semiconductor memory device to detect and amplify the voltage level of a single input / output line. The present invention provides a semiconductor memory device which pulls up to maximize the data voltage difference.

The semiconductor memory device of the present invention for achieving the above object is a memory cell for outputting data to the bit line pair, a bit line sense amplifier for amplifying the voltage difference between the bit line pair and outputs the first input and output line pair, the first input and output line A first sense amplifier that amplifies the voltage difference in response to the first sense amplifier enable signal by receiving the pair of data and outputs the second sensed signal to the second input / output line pair, and precharges the second input / output line pair in response to the input / output line precharge signal. The level of the output signal having the highest voltage level among the output signal pairs of the input / output line precharge part in response to the second sense amplifier enable signal by receiving the output signal pairs of the input / output line precharge part and the input / output line precharge part which are precharged to the voltage level. And an input / output line pull-up circuit which pulls up.

The semiconductor memory device of the present invention for achieving the above object is a column selection circuit for receiving a first input and output line pair signal and transmitting it to the first sense amplifier in response to the column selection line signal, the input and output line pull through the second input and output line pair The output signal of the second sense amplifier and the second sense amplifier, which receives the output signal pair of the up circuit and amplifies and outputs the current level in response to the second sense amplifier enable signal, is delayed by a predetermined time to read the buffered read data. And an output buffer for outputting.

In order to achieve the above object, an input / output line precharge part of a semiconductor memory device of the present invention includes: first and second sides connected to one line of a second input / output line pair and the other side connected to the other line of the second input / output line pair; A series of second PMOS transistors, each having a third PMOS transistor connected to a second input / output line pair, wherein a power supply voltage is applied to the contacts of the first and second PMOS transistors, and the first to third PMOS transistors An input / output line precharge signal having an inverted level is applied to the gate terminal.

The input / output line pull-up circuit of the semiconductor memory device of the present invention for achieving the above object is a fourth PMOS transistor to which a power supply voltage is applied to one side, one side is connected to the other side of the fourth PMOS transistor, and the other side is a second input / output line pair And fifth and sixth PMOS transistors connected to the second terminal, and a second sense amplifier enable signal of which level is inverted is applied to a gate terminal of the fourth PMOS transistor, and gate terminals of the fifth and sixth PMOS transistors are cross-coupled. It is characterized in that connected to the other side of the sixth and fifth PMOS transistors, respectively.

The first sense amplifier of the semiconductor memory device of the present invention for achieving the above object is a voltage sense amplifier, the second sense amplifier is characterized in that the current sense amplifier.

Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic block diagram of a data output path of a semiconductor memory device of the present invention, which includes a memory cell 11, a bit line sense amplifier 13, a column select circuit 14, a local input / output sense amplifier 15, and a global An input / output line precharge unit 16, an input / output line pull-up circuit 100, an input / output sense amplifier 18, and an output buffer 19 are provided.

The memory cell 11 includes an NMOS transistor having one side connected to a grounded capacitor C, one side connected to a bit line BL, the other side connected to the other side of the capacitor C, and a word line WL applied to a gate terminal. N), and the column select circuit 14 has two NMOSs having one side connected to each of the output signal pairs LIO and LIOB of the bit line sense amplifier 13 and receiving the column select line CSL at the gate terminal. It consists of transistors N1 and N2.

The global input / output line precharge unit 16 is connected in series with two PMOS transistors P1 and P2 in parallel with one PMOS transistor P3 so that both sides are connected to the global input / output line pairs GIO and GIOB, respectively. . The power supply voltage VCC is applied to the contacts of the two PMOS transistors P1 and P2, and the inverted global I / O line precharge signal GIO_pre is passed through the inverter INV1 to the gate terminals of the PMOS transistors P1 to P3. Is applied.

The input / output line pull-up circuit 100 has two PMOS transistors P5 connected to one side of a parallel connection between a PMOS transistor P4 to which a power supply voltage VCC is applied and two PMOS transistors P5 and P6. , P6) The other side is connected to the global input / output line pairs GIO and GIOB. The gate terminals of the two PMOS transistors P5 and P6 are cross-coupled and connected to the other side of the counterpart PMOS transistor, respectively, and the inverted input / output sense amplifier enable signal through the inverter INV2 is connected to the gate terminal of the PMOS transistor P4. IOSA_EN) is applied.

The function of each block of the data output path of the semiconductor memory device of the present invention will be described with reference to FIG. 2.

The memory cell 11 receives the word line WL enabled by the input of the row address, and outputs the data that is written and stored to the bit line pairs BL and BLB, and the bit line sense amplifier 13 bit The charge stored in the capacitor C of the memory cell 11 is applied through the line pair BL and BLB to amplify the corresponding voltage.

The column select circuit 14 receives a column address along with a read command from the outside and receives a column select line CSL enabled at a high level to turn on the NMOS transistors N1 and N2 to sense the bit line pairs. The data of the signals BL and BLB are transferred to the local input / output line pairs LIO and LIOB.

The local input / output sense amplifier 15 is further configured to alleviate the problem of load mismatch between the relatively small loading local input / output line pairs (LIO, LIOB) and the large loading global input / output line pairs (GIO, GIOB). As a voltage sense amplifier that may be provided, the semiconductor memory device may be stably operated by preventing the operation speed of the semiconductor memory device having a long global input / output line pair GIO or GIOB or having a low operating voltage.

The global input / output line precharge unit 16 supplies both outputs of the local input / output sense amplifier 15 to the power supply voltage VCC level before the input / output sense enable signal IOSA_EN is applied to the control terminal of the input / output sense amplifier 18. After charging in advance, the global input / output line precharge signal GIO_pre is applied at a low level to discharge both outputs of the local input / output sense amplifier 15.

The input / output line pull-up circuit 100 receives one output signal from the global input / output line precharge unit 16 and discharges one of the output signal pairs of the global input / output line precharge unit discharged in response to the inverted input / output sense amplifier enable signal IOSA_EN. Pull up the signal level and output.

The input / output sense amplifier 18 is a current sense amplifier, receives an output of the input / output line pull-up circuit 100 through the global input / output line pairs GIO and GIOB, and amplifies and outputs the current level.

The output buffer 19 receives the output signals of the power supply voltage VCC level and the ground voltage VSS level from the input / output sense amplifier 18 to delay the predetermined time and output the buffered read data to the data input / output pin DQ. .

FIG. 3 is a circuit diagram of a local sense amplifier in the data output path of the semiconductor memory device of FIG. 2 and includes seven NMOS transistors NM4 to NM10 and an inverter INV.

 The NMOS transistor NM4 has a drain terminal connected to the global input / output line GIO-1, a gate terminal to which the inverted local input / output sense enable signal LIO_SA_EN is applied, and a source terminal connected to the local input / output line LIO. The NMOS transistor NM5 is connected to the drain terminal connected to the global input / output line GIOB-1 and the gate terminal connected to the gate terminal of the NMOS transistor NM4 and to which the inverted local input / output sense amplifier enable signal LIO_SA_EN is applied. It has a source terminal connected to the input / output line LIOB.

 The NMOS transistor NM9 has a drain terminal connected to the global input / output line GIO-1, and a gate terminal to which the local input / output sense amplifier enable signal LIO_SA_EN is applied, and the NMOS transistor NM6 is a source of the NMOS transistor NM9. Has a drain terminal connected to the terminal and a gate terminal connected to the local input / output line LIO, and the NMOS transistor NM10 is connected to the drain terminal connected to the global input / output line GIOB-1 and the gate terminal of the NMOS transistor NM9 and is connected locally. The input / output sense amplifier enable signal LIO_SA_EN has a gate terminal applied thereto, and the NMOS transistor NM7 has a drain terminal connected to the source terminal of the NMOS transistor NM10 and a gate terminal connected to the local input / output line LIOB.

The NMOS transistor NM8 includes a drain terminal connected in common to the source terminal of the NMOS transistor NM6 and the source terminal of the NMOS transistor NM7, a source terminal to which the ground voltage VSS is applied, and a local input / output sense amplifier enable signal LIO_SA_EN. Inverter INV receives the local input / output sense amplifier enable signal LIO_SA_EN, inverts the level, and applies it to the gate terminal of the NMOS transistor NM5.

Hereinafter, an operation of the local sense amplifier in the data output path of the semiconductor memory device of FIG. 3 will be described.

In the case of the data read operation, since the local input / output sense amplifier enable signal LIO_SA_EN and the inverted local input / output sense amplifier enable signal LIO_SA_EN of the local sense amplifier 15 are both enabled, the local sense amplifier 15 normally operates. In operation, data on the local input / output line pairs LIO and LIOB is transferred to the global input / output line pairs GIO-1 and GIOB-1.

In the case of the data write operation, since the inverted local input / output sense amplifier enable signal LIO_SA_EN of the local sense amplifier 15 is enabled and the local input / output sense amplifier enable signal LIO_SA_EN is disabled, the NMOS transistor NM8 ), The NMOS transistor NM9 and the NMOS transistor NM10 are turned off.

FIG. 4 is a simulation timing diagram illustrating an output waveform of a bit line sense amplifier in a data output path of a semiconductor memory device according to an embodiment of the present invention, in which bit line pair signals BL and BLB, column select lines CSL, and local input / output sense amplifiers are enabled. Signal LIO_SA_EN and local input / output line pair signals LIO and LIOB.

Referring to FIG. 4, a simulation result of an operation of a bit line sense amplifier in a data output path of a semiconductor memory device according to the present invention will be described below.

When a row decoder (not shown) analyzes a row address input from an external source and selects one word line and the word line enable signal WL is applied at a high level, the charge of the memory cell 11 connected to the selected word line is applied. Is carried on the corresponding bit line BL.

Assuming that low-level data is stored in the memory cell 11, the voltage of the bit line BL is lowered by a predetermined level at the time point T1, and the voltage of the bit line bar BLB is a precharged power supply voltage. Since the half value (Vcc / 2) of the level is maintained, the bit line pair signals BL and BLB start development and a voltage difference occurs.

When the bit line sense amplifier 13 is enabled at the time point T2, the voltage of the bit line BL gradually decreases, but since the voltage of the bit line bar BLB does not change, the bit line pair signals BL and BLB are voltages. The difference is amplified.

When the potential difference between the bit line pair signals BL and BLB increases to some extent at the time point T3, the bit line BL signal is discharged to the ground voltage VSS level and the bit line bar BLB signal is supplied to the power supply voltage VCC. Charge to level to complete the sensing operation.

When the column address is applied from the outside together with the read command from the time point T4 when the sensing operation is stabilized to some extent, the designated column select line CSL is enabled to a high level so that the NMOS transistors N1 and N2 in the column select circuit 14 are applied. By turning on), the data of the sensed bit line pair signals BL and BLB are transferred to the local input / output line pairs LIO and LIOB so that the local input / output line pairs LIO and LIOB start development and the voltages of both signals. A difference occurs.

That is, if the memory cell 11 reads low-level data, the local input / output line (LIO) signal has a potential slightly lowered at the precharge level, and the potential of the local input / output line bar (LIOB) signal remains at the precharge level. The voltage difference is generated by holding.

After that, when the local input / output sense amplifier enable signal LIO_SA_EN transitions to the high level at time T4, the local input / output sense amplifier 15 operates to amplify the voltage difference between the local input / output line pairs LIO and LIOB, thereby globalizing. Starts development of an input / output line pair.

FIG. 5 is a simulation timing diagram illustrating output waveforms of a local input / output sense amplifier in the semiconductor memory device data output path of the present invention in comparison with the prior art, and includes a global input / output line precharge signal GIO_pre and a local input / output sense amplifier enable signal ( LIO_SA_EN, the input / output sense amplifier enable signal IOSA_EN, the conventional result waveforms GIO and GIOB-1 of the global input / output line pair signal, and the result waveforms GIO-1 and GIOB-1 of the present invention.

A simulation result of the operation of the local input / output sense amplifier in the data output path of the semiconductor memory device of the present invention will be described with reference to FIG. 5.

When the local input / output sense amplifier enable signal LIO_SA_EN transitions to the high level at time T3, the global input / output line pair signals GIO-1 and GIOB-1 begin to fall together at the precharged voltage level to input / output sense amplifiers. At the time point T5 when the enable signal IOSA_EN transitions to the high level, the development starts and the potential difference between the two signals begins to widen.

In this case, the data output path of the conventional semiconductor memory device is the time when the global input / output line precharge signal GIO_pre transitions to the high level from the time T4 when the local input / output sense amplifier enable signal LIO_SA_EN transitions to the high level ( T6) pulls down both signals of GIO and GIOB signals that are precharged to high level and discharged, senses them, amplifies them, and outputs them after development. It takes a long time to drop and the voltage gain is small.

On the other hand, the global output I / O of the semiconductor memory device according to the present invention is precharged to the high level and discharged at the time T4 at which the local input / output sense amplifier enable signal LIO_SA_EN is transitioned to the high level. Both signals of the line pair GIO and GIOB are sensed and amplified and then output as the global input / output line pair signals GIO-1 and GIOB-1. However, from the time point T5 when the input / output sense amplifier enable signal IOSA_EN transitions to the high level, only the global input / output line signal GIO-1 is discharged and the global input / output line bar signal GIOB-1 is pulled up. After sensing, amplifying, and outputting the signals as global input / output line pair signals (GIO-1 and GIOB-1), the potential difference between the global input / output line pair signals (GIO-1 and GIOB-1) is developed so that the data is sufficiently decoded. It takes less time to bevelped and a larger voltage gain.

Referring to FIGS. 2 to 5, the read operation of the data output path of the semiconductor memory device of the present invention will be described below.

When the word line WL is enabled by applying the row address first, the NMOS transistor in the memory cell 11 is turned on, and the voltage charged in the capacitor C in the memory cell 11 is converted into the bit line pair BL, BLB. )

Assuming that low-level data is stored in the memory cell 11, the voltage of the bit line BL is lowered by a predetermined level at the time point T1, and the voltage of the bit line bar BLB is precharged in the previous step. Since the half level (Vcc / 2) of the voltage level is maintained, the bit line pair signals BL and BLB start development and a first voltage difference occurs.

When the bit line sense amplifier 13 is enabled at the time point T2, the bit line sense amplifier 13 receives and amplifies and develops a second voltage difference by receiving data loaded on the bit line pairs BL and BLB. Output

When the potential difference between the bit line pair signals BL and BLB increases to some extent at the time point T3, the bit line BL signal is discharged to the ground voltage VSS level and the bit line bar BLB signal is supplied to the power supply voltage VCC. Charge to level to complete the sensing operation.

During this process, the voltage of the word line continues to be at a high level, so the selected memory cell 11 is continuously connected to the bit line BL so that the data stored in the memory cell 11 data voltage is automatically lowered to a low level. Rewrite.

At this time, when a column address is applied together with a read command from the outside, the designated column select line CSL is enabled at a high level, and as the NMOS transistors in the column select circuit 14 are turned on, the column select circuit 14 is a bit line. Output signals on the local input / output line pairs LIO and LIOB of the sense amplifier 13 are received and transferred to the input terminal of the local input / output sense amplifier 15.

Thereafter, when the local input / output sense amplifier enable signal LIO_SA_EN transitions to the high level at the time T4, the local input / output sense amplifier 15 receives data carried on the local input / output line pairs LIO and LIOB to receive both signals. The voltage difference is amplified and output to the global input / output line pairs GIO and GIOB.

Meanwhile, the global input / output line precharge unit 16 is applied with the global input / output line precharge signal GIO_pre to a high level before the local input / output sense amplifier enable signal LIO_SA_EN is applied to a high level, thereby providing the PMOS transistors P1 to P1 through I. Since P3 is turned on, both output terminals of the local input / output sense amplifier 15 are charged to the power supply voltage VCC level in advance.

After that, when the local input / output sense amplifier enable signal LIO_SA_EN transitions to the high level at the time T3, the input / output line precharge signal GIO_pre transitions to the low level so that the PMOS transistors P1 to P3 are turned off. The voltage charged in the global input / output line pair signals GIO-1 and GIOB-1 starts to be discharged.

In addition, at the time T5 at which the input / output sense amplifier enable signal IOSA_EN transitions to a high level, the global input / output line pair signals GIO-1 and GIOB-1 begin development and the potential difference between the two signals opens. To start.

Meanwhile, the input / output line pull-up circuit 100 may start to descend together from the time point T4 at which the local input / output sense amplifier enable signal LIO_SA_EN transitions to the high level at the precharged voltage level (GIO-1). , The input / output sense amplifier enable signal IOSA_EN is applied at a low level when the input / output sense amplifier 15 is not operated due to the GIOB-1 being applied and thus the voltage on the input / output line is not pulled up.

After that, the PMOS transistor P4 is turned on at the time T5 at which the input / output sense amplifier 15 starts to operate and the input / output sense amplifier enable signal IOSA_EN transitions to a high level, thereby turning on the global input / output line bar signal GIOB. ) Is pulled up by a predetermined voltage level and output.

As described above, the input / output line pull-up circuit 100 maintains the discharge state of the global input / output line signal GIO-1 and senses only the global input / output line bar signal GIOB-1 by pulling up the global input / output line pair signal GIO-. 1, GIOB-1) is developed, the potential difference is much larger, it takes less time for the data to fully develop, and the voltage gain is also increased.

Accordingly, the resultant waveforms GIO-1 and GIOB-1 of the present invention for the global input / output line pair signal are amplified by a voltage width larger than that of the conventional resultant waveforms GIO and GIOB as shown in FIG. The time taken to fully develop is shortened and the voltage gain is increased, resulting in an increase in the gain of the input / output sense amplifier 18.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

According to the present invention, the layout area of the semiconductor memory device core is minimized, and the voltage difference between the input and output line pair signals is increased, thereby reducing the time required for sufficient data to be developed and increasing the gain of the input / output sense amplifier.

Claims (5)

Memory cells for outputting data to bit line pairs; A bit line sense amplifier configured to amplify the voltage difference between the bit line pair and output the amplified voltage to the first input / output line pair; A first sense amplifier receiving the data of the first input / output line pair and amplifying a voltage difference in response to a first sense amplifier enable signal and outputting the voltage difference to the second input / output line pair; An input / output line precharge unit configured to precharge the second input / output line pair to a precharge voltage level in response to an input / output line precharge signal; An input / output line pull-up circuit for receiving an output signal pair of the input / output line precharge unit and pulling up a level of an output signal having a high voltage level among the output signal pairs of the input / output line precharge unit in response to a second sense amplifier enable signal; A semiconductor memory device, characterized in that provided. The method of claim 1, The semiconductor memory device A column selection circuit receiving the first input / output line pair signal and transferring the first input / output line pair signal to the first sense amplifier in response to a column selection line signal; A second sense amplifier receiving an output signal pair of the input / output line pull-up circuit through the second input / output line pair and amplifying and outputting a current level in response to the second sense amplifier enable signal; And an output buffer configured to receive the output signal of the second sense amplifier and output a buffered read data with a predetermined time delay. The method of claim 1, The input / output line precharge unit A series connection of first and second PMOS transistors having one side connected to one line of the second input / output line pair and the other side connected to the other line of the second input / output line pair; Two sides having a third PMOS transistor connected to the second input / output line pair, respectively; And the power supply voltage is applied to the contacts of the first and second PMOS transistors, and the input / output line precharge signal whose level is inverted is applied to the gate terminals of the first to third PMOS transistors. The method of claim 2, The input and output line pull-up circuit A fourth PMOS transistor to which one side of the power supply voltage is applied; Fifth and sixth PMOS transistors having one side connected to the other side of the fourth PMOS transistor and the other side connected to each of the second input / output line pairs, The second sense amplifier enable signal whose level is inverted is applied to the gate terminal of the fourth PMOS transistor, and gate terminals of the fifth and sixth PMOS transistors are cross-coupled to the other side of the sixth and fifth PMOS transistors, respectively. A semiconductor memory device, characterized in that connected. The method of claim 4, wherein And the first sense amplifier is a voltage sense amplifier, and the second sense amplifier is a current sense amplifier.

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