KR20080076408A - Device to protect semiconductor device from electro static discharge - Google Patents

Device to protect semiconductor device from electro static discharge Download PDF

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Publication number
KR20080076408A
KR20080076408A KR1020070016261A KR20070016261A KR20080076408A KR 20080076408 A KR20080076408 A KR 20080076408A KR 1020070016261 A KR1020070016261 A KR 1020070016261A KR 20070016261 A KR20070016261 A KR 20070016261A KR 20080076408 A KR20080076408 A KR 20080076408A
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KR
South Korea
Prior art keywords
voltage
trigger circuit
trigger
nmos transistor
static electricity
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Application number
KR1020070016261A
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Korean (ko)
Inventor
임동주
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070016261A priority Critical patent/KR20080076408A/en
Publication of KR20080076408A publication Critical patent/KR20080076408A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Abstract

The present invention discloses a device having a low trigger voltage for protecting an internal circuit from electrostatic discharge. The present invention relates to a device for protecting an internal circuit from static electricity from outside. An electrostatic discharge protection device connected between second voltage terminals, comprising: a main trigger circuit for generating a triggered voltage drop corresponding to static electricity; An auxiliary trigger circuit, which is turned on by the main trigger voltage and outputs a voltage generated by static electricity; And a discharge unit which is turned on by the trigger voltage and the voltage output from the auxiliary trigger circuit to provide a path through which static electricity is discharged.

Description

Device To Protect Semiconductor Device From Electro Static Discharge

1 is a cross-sectional view of a GGNMOS which is a conventional electrostatic discharge protection element.

2 is a circuit diagram illustrating an electrostatic discharge protection device according to a conventional example.

3 is a circuit diagram showing an electrostatic discharge protection device according to another conventional example.

4 is a circuit diagram showing an electrostatic discharge protection device according to an embodiment of the present invention.

5 is a waveform diagram showing an embodiment of the main electrostatic discharge circuit portion of FIG.

6 is a circuit diagram illustrating an electrostatic discharge protection device according to another embodiment of the present invention.

7 is a waveform diagram showing a conventional electrostatic discharge according to the embodiment of the present invention.

The present invention relates to an electrostatic discharge protection device that protects an internal circuit from damage by electrostatic discharge (ESD).

In general, when a semiconductor integrated circuit contacts a charged human body or a machine, the static electricity charged in the human body or the machine is discharged into the semiconductor through an input / output pad through an external pin of the integrated circuit.

The static electricity discharged in this way is a transient current wave that causes great damage to the semiconductor internal circuit, and has a large energy.

Alternatively, the static electricity that has been charged inside the semiconductor is discharged to the internal element by the contact of the peripheral circuit, which may cause great damage to the internal circuit.

Therefore, in order to solve the above, most semiconductor integrated circuits include an electrostatic discharge protection device between the input / output pad and the semiconductor internal circuit.

Such an electrostatic discharge protection device is typically a GGNMOS (Gate Grounded NMOS), Figure 1 shows a cross-sectional view of the GGNMOS having a P- type substrate.

The operation principle of GGNMOS is as follows.

First, when static electricity flows through the input / output pad 8, a high voltage is applied to the drain 10 correspondingly.

When a high voltage is applied to the drain 10, holes generated between the drain 10 and the substrate 18 move to the substrate, thereby increasing the potential of the substrate 18.

When the potential increase of the substrate 18 increases above the operating voltage of the diode composed of the source 14 and the substrate 18, the parasitic bipolar T1 operates to discharge static electricity to the ground.

Recent process technologies, however, are increasingly demanding high-speed, low-voltage operation, leading to smaller device sizes, reduced gate oxide thickness, and new process technologies such as silicide processes. This is the case.

While this process technology is necessary to implement devices suitable for high speed operation, it has a negative effect on electrostatic protection devices.

One of the negative effects is the reduction of the gate breakdown voltage due to the reduction of the gate insulating oxide thickness.

When the gate breakdown voltage is reduced, as a static protection device, a conventional GGNMOS having a high trigger voltage becomes difficult to apply, so a GGNMOS having a low trigger voltage has to be developed.

In the related art, a method of lowering the trigger voltage has been applied to a gate triggering technique that applies a turn-on voltage to a gate or a voltage to a substrate using a differential circuit including a resistor and a capacitor during discharge, and an electrostatic discharge protection device of a substrate triggering technique. .

2 and 3 show this electrostatic discharge protection device according to the prior art.

2 is an electrostatic discharge protection device using a gate triggering technique that includes a trigger circuit 102, an inverter 104, and a discharge portion 106 having an electrostatic discharge protection element.

In detail, the trigger circuit 102 includes a resistor R2 and a capacitor C1 connected in series between the power supply voltage terminal VCC and the ground voltage terminal VSS.

The inverter 104 is a driving unit in the form of CMOS transistors PM1 and NM1 and applies a voltage to the gate of the NMOS transistor NM2 of the discharge unit 106 through an output node.

3 shows an electrostatic protection device using a substrate triggering technique.

Specifically, the differential circuit 110 includes a capacitor C2 and a resistor R3 connected in series, and has a characteristic of applying a trigger voltage to the substrate of the NMOS transistor NM3 through an output node during electrostatic discharge.

However, as mentioned above, since an electrostatic protection device having an even lower trigger voltage is required according to the development of the process technology of the semiconductor device and the low voltage and speed, the conventional electrostatic protection having the configuration as shown in FIGS. 2 and 3 is required. The device is inadequate for such low voltage, high speed semiconductor memory devices.

Accordingly, it is an object of the present invention to provide an electrostatic protection device having a low trigger voltage suitable for semiconductor memory devices that operate at low voltages and at high speeds.

Another object of the present invention is to effectively protect a semiconductor internal circuit from electrostatic discharge by using an electrostatic protection device having a low trigger voltage.

Electrostatic discharge protection device according to the present invention for achieving the above object in the electrostatic discharge protection device connected between the first and second voltage terminals for protecting the internal circuit from the static electricity flowing from the outside, the voltage corresponding to the static electricity A main trigger circuit for generating a dropped trigger voltage; An auxiliary trigger circuit turned on by the main trigger voltage to output a voltage generated by the static electricity; And a discharge unit which is turned on by the trigger voltage and the voltage output from the auxiliary trigger circuit to provide a path through which the static electricity is discharged.

Here, the main trigger circuit may include a capacitor and a resistor connected in series between the first and second voltage terminals.

On the other hand, the auxiliary trigger circuit is characterized in that it comprises a first NMOS transistor and a resistor connected in series.

Among the first NMOS transistors, a gate and a source are commonly connected to one end of the resistor, and the trigger voltage is provided to the substrate.

The auxiliary trigger circuit may include a series connected NPN bipolar transistor and a resistor.

The discharge unit includes a voltage drop unit for dropping an output voltage of the auxiliary trigger unit; And

And a discharge device turned on by the voltage dropped by the voltage drop unit to provide an electrostatic discharge path.

Among these, the voltage drop unit may include a diode that transfers the output of the auxiliary trigger circuit; And a resistor for dropping the voltage transmitted from the diode.

In addition, the discharge device is composed of a second NMOS transistor, characterized in that the trigger voltage of the main trigger circuit is provided as a substrate voltage, and the output of the voltage drop portion is transmitted to the gate.

The auxiliary trigger circuit includes a MOS transistor type diode that receives the trigger voltage of the main trigger circuit as a substrate voltage, and the area of the MOS transistor type diode is smaller than that of the second NMOS transistor. .

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a circuit diagram illustrating an electrostatic protection device according to an embodiment of the present invention.

Specifically, the electrostatic discharge protection device of the present invention includes a main trigger circuit 202, an auxiliary trigger circuit 204, and a discharge unit 206.

The main trigger circuit 202 includes a capacitor C20 and a resistor R20 connected in series between the external voltage terminal Vcc and the ground voltage terminal Vss, and a common node between the capacitor C20 and the resistor R20. N20 has a configuration in which it is an output terminal.

The common node N20 is connected to the NMOS transistor NM20 of the auxiliary trigger circuit and the NMOS transistor NM22 of the discharge unit 206.

Meanwhile, the auxiliary trigger circuit 204 includes an NMOS transistor NM20 connected in series between the power supply voltage terminal Vcc and the ground voltage terminal Vss and a resistor R22 connected in series thereto.

Here, the gate and the source of the NMOS transistor NM20 are connected to the common node N22.

In addition, the common node N22 is connected to the anode terminal of the diode D20 of the main static electricity protection circuit.

The discharge unit 206 includes a diode D20, an NMOS transistor NM22, and a resistor R24.

Here, the NMOS transistor NM22 is connected between the external voltage terminal VCC and the ground voltage terminal VSS, and the substrate of the NMOS transistor NM22 is connected to the common node N20.

On the other hand, the substrates of the NMOS transistor NM20 and the NMOS transistor NM22 are commonly configured to receive a trigger voltage which is an output of the main trigger circuit 204.

The cathode of the diode D20 is connected to the gate of the NMOS transistor NM22 which operates as the main electrostatic discharge protection element, and the resistance between the ground voltage VSS and the gate of the NMOS transistor NM22 through the common node N24. R24).

The NMOS transistor NM20 of the auxiliary trigger circuit 204 is preferably configured to have a smaller area than that of the NMOS transistor N22 of the discharge unit 206.

Hereinafter, an embodiment showing a specific operation of the present invention will be described.

First, when static electricity flows into the external voltage terminal VCC, a voltage drop is generated by the resistor R20 connected in series with the capacitor C20 of the main trigger circuit 202.

At this time, the capacitor (C20) and the resistor (R20) for generating a voltage drop is the correction of the capacitor (C20) and the resistor (R20) to generate a voltage drop (a) of about 1 to 2 volts when static electricity is introduced It is preferred that the number be adjusted.

The voltage drop (a) may be represented by Equation 1 below, where C represents a capacitor capacity, R represents a resistance value, and dVi / dt represents an amount of change of voltage introduced by static electricity over time.

a = CR (dVi / dt) (Vi: voltage introduced by static electricity, t: time)

The voltage generated by the voltage drop is applied to the substrates of the NMOS transistor NM22 of the discharge unit 206 and the NMOS transistor NM20 of the auxiliary trigger circuit 204.

At this time, the voltage generated by the voltage drop is applied as a positive voltage to the substrates of the NMOS transistors NM20 and NM22 to reduce the trigger voltage.

According to the voltage drop in the main trigger circuit 202, the NMOS transistor NM20 of the auxiliary trigger circuit 204 is turned on, and as a result, static electricity induced through the power supply voltage terminal VCC is applied to the source terminal of the NMOS transistor NM20. The anode voltage of the diode D20 connected to the voltage is increased.

Thereafter, the voltage output from the diode D20 is input to the gate of the NMOS transistor NM22 that operates as the main electrostatic protection device to turn on the NMOS transistor NM22, and the turned-on NMOS transistor NM22 is connected to the ground voltage terminal. VSS) to discharge static electricity.

Here, the resistor R24 provided in the discharge unit 206 serves to prevent a malfunction in the normal operating state.

5 is a waveform diagram illustrating a voltage over time of the discharge unit 206 according to an embodiment of the present invention.

Referring to FIG. 5, waveform a represents the voltage change of the source of the NMOS transistor NM20 over time.

As can be seen from the waveform a, the source of the NMOS transistor NM20 increases in voltage until the turn-on level of the diode D20, and when the diode D20 is turned on, the voltage decreases and becomes constant.

Waveform b shows the voltage change across the diode D20 over time.

Before the diode D20 is turned on, the diode D20 is operated as a capacitor and is turned on in a period where the voltage difference between the anode and the cathode is reduced.

On the other hand, immediately after the diode is turned on, when the charged charges of the diode move in the opposite direction of the diode, the waveform b (voltage across the diode) decreases and then increases again after a certain time.

In addition, the waveform c shows a change in voltage applied to the gate of the NMOS transistor NM22, which is the main electrostatic discharge protection device, over time.

The initial diode operates and shows a rising curve in which the voltage rises until the NMOS transistor NM22 is turned on. After that, when the NMOS transistor NM22 is turned on, the voltage decreases.

The waveform b representing the voltage of the diode (Diode Voltage) is the difference between the waveform c (Vg Main) representing the voltage of the main electrostatic discharge protection device and the waveform a (Vs trigger circuit) representing the source voltage of the NMOS transistor NM20. same.

On the other hand, the section A shown in FIG. 5 is a section in which the gate voltage of the NMOS transistor NM22 is temporarily increased to 1 Volt or more while the voltage across the diode decreases.

In addition, section B represents a section in which the diode is turned on and the discharge unit 206 is turned on to discharge static electricity.

As described above, the present invention applies the trigger voltage to the gate and the substrate region when the static electricity flows through the power through the above-described trigger circuit configuration, and unlike the conventional electrostatic discharge protection device, the substrate triggering and gate triggering effects can be simultaneously obtained. Can be.

In addition, as the operation by the trigger voltage is simultaneously performed on the substrate and the gate, the trigger voltage is further reduced, and an effective and fast discharge operation can be performed.

6 is a circuit diagram showing an electrostatic discharge protection device according to another embodiment of the present invention.

Referring to FIG. 6, an electrostatic discharge protection device according to another embodiment of the present invention may be configured using a bipolar transistor.

Specifically, the electrostatic discharge protection device of the present invention includes a main trigger circuit 302, an auxiliary trigger circuit 304, and a discharge unit 306.

 The main trigger circuit 302 includes a capacitor C30 and a resistor R30 connected in series between the external voltage terminal Vcc and the ground voltage terminal Vss, and a common node between the capacitor C30 and the resistor R30. N30 has a configuration in which it is an output terminal.

Here, the common node N30 is connected to the substrate of the bipolar transistor T30 of the auxiliary trigger circuit and the NMOS transistor NM30 of the discharge unit 306.

Meanwhile, the auxiliary trigger circuit 304 includes an NPN bipolar transistor T30 and a resistor R32 connected in series between the power supply voltage terminal Vcc and the ground voltage terminal Vss.

Here, the gate and the source of the NPN bipolar transistor T30 are connected to the common node N32.

In addition, the common node N32 is connected to the anode terminal of the diode D30 of the discharge portion.

The discharge unit 306 includes a diode D30, an NMOS transistor NM30, and a resistor R34.

Here, the NMOS transistor NM30 is connected between the external voltage terminal VCC and the ground voltage terminal VSS, and the substrate of the NMOS transistor NM30 is connected to the common node N30.

On the other hand, the substrates of the NPN bipolar transistor T30 and the NMOS transistor NM30 are configured in common and are provided with a trigger voltage which is an output of the main trigger circuit 304.

The cathode of the diode D30 is connected to the gate of the NMOS transistor NM30, and is connected to the resistor R34 between the ground voltage terminal VSS and the gate of the NMOS transistor NM30 through the common node N34.

On the other hand, the NPN bipolar transistor T30 of the auxiliary trigger circuit 304 is preferably composed of a smaller area than the NMOS transistor N30.

7 is a graph illustrating a process of discharging static electricity of the embodiment of the present invention and the prior art.

While the trigger voltage d of the conventional substrate triggering circuit is about 5 volts, the electrostatic discharge protection device using the substrate and gate triggering effect of the present invention has a trigger voltage e of about 4 volts.

This represents a trigger voltage that is reduced by about 20% compared with the prior art.

Accordingly, the electrostatic discharge protection device of the present invention uses the static electricity introduced through the main trigger circuit and the auxiliary trigger circuit to provide a trigger voltage fed back to the gate and the substrate to the discharge portion, thereby providing an electrostatic discharge protection device having a low trigger voltage. Can be provided.

In addition, the trigger circuit for feeding back the trigger voltage to the gate and the substrate is configured with a small area, thereby providing an electrostatic discharge protection device having improved layout efficiency.

Claims (9)

In the electrostatic discharge protection device connected between the first and second voltage terminals for protecting the internal circuit from the static electricity flowing from the outside, A main trigger circuit for generating a triggered voltage drop corresponding to the static electricity; An auxiliary trigger circuit turned on by the main trigger voltage to output a voltage generated by the static electricity; And And a discharge unit which is turned on by the trigger voltage and the voltage output from the auxiliary trigger circuit to provide a path for discharging the static electricity. The method of claim 1, And the main trigger circuit has a capacitor and a resistor connected in series between the first and second voltage terminals. The method of claim 1, And the auxiliary trigger circuit comprises a first NMOS transistor and a resistor connected in series. The method of claim 3, wherein The first NMOS transistor has a gate and a source is commonly connected to one end of the resistor, the electrostatic discharge protection device, characterized in that provided with the trigger voltage to the substrate. The method of claim 1, And wherein the auxiliary trigger circuit comprises a series connected NPN bipolar transistor and a resistor. The method of claim 1, The discharge unit A voltage drop unit for dropping an output voltage of the auxiliary trigger unit; And And a discharge device turned on by the voltage dropped by the voltage drop unit to provide an electrostatic discharge path. The method of claim 6, The voltage drop is A diode delivering an output of the auxiliary trigger circuit; And And a resistor for dropping the voltage transmitted from the diode. The method of claim 6, The discharge device is composed of a second NMOS transistor, the electrostatic discharge protection device characterized in that receiving the trigger voltage of the main trigger circuit as a substrate voltage, and receives the output of the voltage drop portion to the gate. The method of claim 8, The auxiliary trigger circuit includes a MOS transistor type diode that receives the trigger voltage of the main trigger circuit as a substrate voltage, and an area of the MOS transistor type diode is smaller than that of the second NMOS transistor. .
KR1020070016261A 2007-02-15 2007-02-15 Device to protect semiconductor device from electro static discharge KR20080076408A (en)

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KR1020070016261A KR20080076408A (en) 2007-02-15 2007-02-15 Device to protect semiconductor device from electro static discharge

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KR1020070016261A KR20080076408A (en) 2007-02-15 2007-02-15 Device to protect semiconductor device from electro static discharge

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KR20080076408A true KR20080076408A (en) 2008-08-20

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