KR100818086B1 - ElectroStatic Discharge Protection Circuit - Google Patents

ElectroStatic Discharge Protection Circuit Download PDF

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Publication number
KR100818086B1
KR100818086B1 KR1020060031557A KR20060031557A KR100818086B1 KR 100818086 B1 KR100818086 B1 KR 100818086B1 KR 1020060031557 A KR1020060031557 A KR 1020060031557A KR 20060031557 A KR20060031557 A KR 20060031557A KR 100818086 B1 KR100818086 B1 KR 100818086B1
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Prior art keywords
voltage
discharge protection
electrostatic discharge
protection circuit
gate
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KR1020060031557A
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Korean (ko)
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KR20070100026A (en
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문정언
임동주
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주식회사 하이닉스반도체
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    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04HBUILDINGS OR LIKE STRUCTURES FOR PARTICULAR PURPOSES; SWIMMING OR SPLASH BATHS OR POOLS; MASTS; FENCING; TENTS OR CANOPIES, IN GENERAL
    • E04H15/00Tents or canopies, in general
    • E04H15/32Parts, components, construction details, accessories, interior equipment, specially adapted for tents, e.g. guy-line equipment, skirts, thresholds
    • E04H15/54Covers of tents or canopies
    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04BGENERAL BUILDING CONSTRUCTIONS; WALLS, e.g. PARTITIONS; ROOFS; FLOORS; CEILINGS; INSULATION OR OTHER PROTECTION OF BUILDINGS
    • E04B1/00Constructions in general; Structures which are not restricted either to walls, e.g. partitions, or floors or ceilings or roofs
    • E04B1/62Insulation or other protection; Elements or use of specified material therefor
    • E04B1/74Heat, sound or noise insulation, absorption, or reflection . Other building methods affording favourable thermal or acoustical conditions, e.g. accumulating of heat within walls
    • E04B1/76Heat, sound or noise insulation, absorption, or reflection . Other building methods affording favourable thermal or acoustical conditions, e.g. accumulating of heat within walls specifically with respect to heat only
    • E04B1/78Heat insulating elements

Abstract

The present invention discloses an electrostatic discharge protection circuit operating at a low trigger voltage by applying a voltage generated in the trigger circuit to the gate and the substrate of the electrostatic discharge protection device.
Disclosed is a driving unit generating a driving voltage using a voltage drop generated by an electrostatic current due to static electricity, a trigger driven by a driving voltage, and generating a gate trigger voltage and a substrate trigger voltage through voltage distribution using an electrostatic current. And a static electricity discharge protection unit configured to discharge the static electricity by applying the voltage reducing unit and the gate trigger voltage and the substrate trigger voltage.

Description

Electrostatic Discharge Protection Circuit

1 is a cross-sectional view of a conventional electrostatic discharge protection device,

2 is a view showing an electrostatic discharge protection circuit for lowering a conventional trigger voltage;

3 illustrates another electrostatic discharge protection circuit for lowering a conventional trigger voltage.

4 is a diagram showing an electrostatic discharge protection circuit according to a first embodiment of the present invention;

FIG. 5 is a diagram illustrating a simulation result of a trigger voltage of the electrostatic discharge protection circuit of FIG. 4 and the electrostatic discharge protection circuit of FIG. 2;

6 is a diagram showing an electrostatic discharge protection circuit according to a second embodiment of the present invention;

7 is a diagram illustrating an electrostatic discharge protection circuit according to a third embodiment of the present invention.

The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge protection circuit operating at a low trigger voltage by applying a voltage generated in the trigger circuit to the gate and the substrate of the electrostatic discharge protection device.

In general, an electrostatic discharge (ESD) protection circuit is a circuit formed between a semiconductor internal circuit and a pad to which an external input / output pin is connected in order to prevent product destruction or product degradation due to static electricity when designing a semiconductor device. .

When a semiconductor circuit is in contact with a charged human body or machine, the static electricity charged by the human body or machine is discharged into the semiconductor circuit through the input / output pads through the external pins of the semiconductor circuit, and a transient current with a large energy flows into the semiconductor internal circuit. It can seriously damage the circuit.

In addition, as the static electricity charged inside the semiconductor circuit is discharged to the outside through the machine by the contact of the machine, a transient current may flow to the semiconductor internal circuit to damage the semiconductor circuit.

Accordingly, most semiconductor circuits provide an electrostatic discharge protection circuit using an electrostatic discharge protection element between the input / output pad and the semiconductor internal circuit to protect the semiconductor internal circuit from damage of the semiconductor circuit due to static electricity.

1 is a cross-sectional view of a conventional electrostatic discharge protection device. Referring to FIG. 1, the conventional electrostatic discharge protection device is a gate grounded NMOS (GGNMOS), where the drain region 12 is connected to the pad PAD, and the gate region 14, the source region 16, and the pickup region 18 are provided. ) Has a structure connected to ground.

When a high voltage is applied to the drain region 12 due to the generation of static electricity, the potential of the substrate P-SUBSTRATE increases as a hole generated between the drain region 12 and the pickup region 18 moves to the substrate P-SUBSTRATE. When the voltage of the substrate P-SUBSTRATE is increased above the operating voltage of the source 16 and the diode formed of the substrate, the parasitic bipolar transistor operates to discharge static electricity.

On the other hand, as the semiconductor technology advances, the thickness of the gate insulating film of the NMOS transistor constituting the semiconductor internal circuit becomes thin. However, when the thickness of the insulating film of the gate becomes thin, the voltage at which the gate insulating film is destroyed is reduced.

In terms of the electrostatic discharge protection device, reducing the gate dielectric breakdown voltage makes it difficult to use GGNMOS with high trigger voltage. Therefore, efforts are being made to lower the trigger voltage.

2 is a diagram illustrating an electrostatic discharge protection circuit for lowering a conventional trigger voltage. Referring to FIG. 2, the conventional electrostatic discharge protection circuit for lowering the trigger voltage applies a turn-on voltage or more to the gate of the NMOS transistor N1, which is an electrostatic discharge protection element during electrostatic discharge, by using a differential circuit. Lower the trigger voltage.

When static electricity flows into the power supply voltage supply pad, current flows to the capacitor C of the trigger circuit 20. At this time, a voltage drop occurs as a current such as a current flowing through the capacitor C flows through the resistor R of the trigger circuit 20, which causes a voltage difference between the gate and the source of the PMOS transistor P1 of the inverter 22. do.

When the voltage difference between the gate and the source of the PMOS transistor P1 increases to turn on the PMOS transistor P1, the PMOS transistor P1 is turned on so that the inverter 22 generates a positive voltage. It outputs to the gate of transistor N1. Therefore, the NMOS transistor N1 is turned on to discharge the static electricity introduced into the power supply voltage supply pad to the ground voltage supply pad.

3 is a diagram illustrating another electrostatic discharge protection circuit for lowering a conventional trigger voltage. Referring to FIG. 3, a conventional electrostatic discharge protection circuit for lowering a trigger voltage is applied with a high voltage to the drain of the NMOS transistor N4 when static electricity flows, and by using a current generated therein, an NMOS transistor which is an electrostatic discharge protection device ( By applying a voltage to the substrate of N3), the trigger voltage of the NMOS transistor N3 is lowered.

However, in order to implement an electrostatic discharge protection circuit suitable for semiconductor technology and low voltage high speed operation characteristics, which are continuously developed, an electrostatic discharge protection circuit driven at a lower trigger voltage than a conventional electrostatic discharge protection circuit is required.

SUMMARY OF THE INVENTION The present invention has been made by the above necessity, and an object thereof is to apply a voltage generated in a trigger circuit to a gate and a substrate of an electrostatic discharge protection device so that the electrostatic discharge protection circuit can operate at a low trigger voltage.

In order to achieve the above object, a driving unit for generating a driving voltage by using a voltage drop generated by the electrostatic current due to static electricity, the gate trigger voltage and the substrate trigger is driven by the driving voltage and the voltage distribution using the electrostatic current A trigger voltage reducing unit generating a voltage and an electrostatic discharge protection unit configured to discharge the static electricity by receiving the gate trigger voltage and the substrate trigger voltage.

Here, the driving unit is a capacitor connected to the first resistor and the first resistor to generate a voltage by the electrostatic current due to the static electricity flowing into the first pad to generate a driving voltage and to flow the electrostatic current to the second pad It includes. In one embodiment of the present invention, the first pad is a power supply voltage pad, the second pad is a ground voltage pad, and the first resistor is resistor R11 of FIG. 4.

The trigger voltage reducing unit may include switching means for interrupting the electrostatic current by the driving voltage, a second resistor connected to the switching means, and resistance means connected in series with the second resistor, The gate trigger voltage and the substrate trigger voltage may be generated by voltage distribution using the second resistor and the resistance means. In one embodiment of the present invention, the second resistor is preferably the resistor R12 of FIG.

In addition, the switching means is preferably a PMOS transistor or a bipolar transistor.

In addition, the resistor means includes a third resistor, a gate and a drain, which are connected to the second resistor in common, and an NMOS transistor or a collector and a base connected to the second resistor in common to operate as a diode. Can be. In one embodiment of the present invention, the third resistor is preferably resistor R13 of FIG. 4.

The electrostatic discharge protection unit may be an NMOS transistor including a drain connected to the first pad, a gate to which the gate trigger voltage is applied, a substrate to which the substrate trigger voltage is applied, and a source connected to the second pad. Do.

In addition, when a power supply voltage is supplied to the first pad, the power supply voltage is driven by the power supply voltage to discharge the voltage applied to the gate of the NMOS transistor by the leakage current of the switching means to the second pad so that the N-mode transistor is turned on. It further comprises a leakage preventing means for preventing it.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating an electrostatic discharge protection circuit according to a first embodiment of the present invention. As shown in FIG. 4, the electrostatic discharge protection circuit 100 according to the first embodiment of the present invention includes a driving unit 110, a trigger voltage reducing unit 120, and an electrostatic discharge protection unit 130.

The driving unit 110 is a driving voltage for driving the trigger voltage reduction unit 120 by using a voltage drop generated while flowing a current to the ground voltage supply pad when positive static electricity flows into the power supply voltage supply pad. Create

The driver 110 includes a resistor R11 for generating a voltage drop and a capacitor C11 for flowing an alternating current generated by the static electricity introduced to the ground voltage supply pad.

Preferably, the resistor R11 is connected to one end of the power supply voltage supply pad and the other end is connected to one end of the capacitor C11, and the capacitor C11 is connected to the other end of the resistor R11 and the other end is supplied with the ground voltage. It is preferably connected to the pad.

The connection node of the resistor R11 and the capacitor C11 operates as an output terminal for outputting a driving voltage to the trigger voltage reduction unit 120.

The trigger voltage reducing unit 120 receives a driving signal from the driving unit 110, generates a gate trigger voltage VT and a substrate trigger voltage VS, and outputs the gate trigger voltage VT to the electrostatic discharge protection unit 130.

The trigger voltage reducing unit 120 is turned on by a driving signal and transmits an electrostatic current generated by static electricity to a ground voltage supply pad. The resistor generates a gate trigger voltage VT using an electrostatic current. And a resistor R13 for generating the substrate trigger voltage VS using the electrostatic current R12.

The PMOS transistor P11 includes a source connected to the power supply voltage supply pad, a substrate connected to the source, a gate to which the driving voltage of the driver 110 is applied, and a drain connected to one end of the resistor 12.

Preferably, the resistor R12 is connected to the drain of the PMOS transistor P11 and the other end thereof is connected to one end of the resistor R13, and the resistor R13 is connected to the other end of the resistor R12 and the other end thereof. Is preferably connected to the ground voltage supply pad.

The connection node of the resistor R12 and the PMOS transistor P11 serves as an output terminal for outputting the gate trigger voltage VT to the electrostatic discharge protection unit 130, and the connection node of the resistor R12 and the resistor R13 is a substrate. It operates as an output terminal for outputting the trigger voltage VS.

The electrostatic discharge protection unit 130 receives the gate trigger voltage VT and the substrate trigger voltage VS from the trigger voltage reduction unit 120 and turns on to flow an electrostatic current generated by static electricity to a ground voltage supply pad. As a result, the introduced static electricity is discharged.

The electrostatic discharge protection unit 130 includes a drain connected to the power supply voltage supply pad, a gate to which the gate trigger voltage VT of the trigger voltage reduction unit 120 is applied, and a substrate trigger voltage VS of the voltage reduction unit 120. And an NMOS transistor N11 having a substrate to which it is applied.

The gate trigger voltage VT is preferably greater than a threshold voltage of the MOS transistors constituting the semiconductor memory. In addition, the substrate trigger voltage VS serves to reduce the threshold voltage VTH of the NMOS transistor N11, which is the electrostatic discharge protection unit 130.

Hereinafter, the operation of the electrostatic discharge protection circuit according to the first embodiment of the present invention will be described.

First, the operation at the occurrence of static electricity will be described. When a positive potential static signal flows into the supply voltage supply pad relative to ground voltage,

Figure 112006024217062-pat00001
By the change of the capacitor C11 of the driving unit 110 induces the electrostatic current by the static electricity to the ground voltage supply pad. The resistor R11 of the driver 110 generates a driving voltage for driving the trigger voltage reducing unit 120 by using the voltage drop generated by the electrostatic current.

In this case, the driving voltage refers to a voltage for turning on the PMOS transistor P11 of the trigger voltage reducing unit 120, that is, a gate voltage dropped with respect to the source voltage of the PMOS transistor P11.

When the driving voltage of the driving unit 110 is applied to the gate of the PMOS transistor P11, the PMOS transistor P11 is turned on so that the electrostatic current caused by static electricity is connected to the resistor R12 connected in series with the drain of the PMOS transistor P11. It flows through the resistor R13 to the ground voltage supply pad.

Electrostatic current flowing through the PNOS transistor P11 to the ground voltage supply pad causes a voltage to be applied to the resistors R12 and R13. The voltage dropped by the resistor R12, that is, the voltage applied to the resistor R13, is applied to the substrate of the NMOS transistor N11 as the substrate trigger voltage VS. Therefore, the threshold voltage VTH of the NMOS transistor N11 is lower than when the substrate trigger voltage VS is not applied to the substrate of the NMOS transistor N11.

In addition, the voltage applied to the resistor R12 and the resistor R13 is applied to the gate of the NMOS transistor N11 as the gate trigger voltage VT. Accordingly, the ESD triggering voltage of the NMOS transistor N11 is lower than that when the gate trigger voltage VT is not applied to the gate of the NMOS transistor N11.

The ESD operation start voltage depends on the gate voltage of the NMOS transistor N11. The higher the gate voltage of the NMOS transistor N11 is, the lower the NMOS transistor N11 can discharge static electricity more quickly.

The following describes normal operation without static electricity. If no static electricity is generated, DC voltage is applied to the power supply voltage supply pad.

Figure 112006024217062-pat00002
Is changed to zero. Therefore, the capacitor C11 of the driver 110 does not have a voltage change and thus floats, and a power supply voltage is applied to the gate and the source of the PMOS transistor P11 of the trigger voltage reducer 120. Is applied.

Since there is no difference between the source voltage and the gate voltage of the PMOS transistor P11, the PMOS transistor P11 is not driven, and the gate and the substrate of the NMOS transistor N11 connected to the ground voltage supply pad through the resistors R12 and R13 are The ground voltage is to be applied. In other words. In the normal operation, the NMOS transistor N11 constituting the electrostatic discharge protection unit 130 does not operate.

FIG. 5 is a diagram illustrating a simulation result of a trigger voltage of the electrostatic discharge protection circuit of FIG. 4 and the electrostatic discharge protection circuit of FIG. 2. As shown in FIG. 5, the NMOS transistor N1 of the electrostatic discharge protection circuit which triggers only a conventional gate has an ESD operation start voltage of about 5.24V, whereas the NMOS transistor N11 of the electrostatic discharge protection circuit of this embodiment has an ESD operation. The starting voltage is 4.12V. That is, it can be seen that the ESD operation starting voltage of the NMOS transistor N11 of the present embodiment is reduced by about 21% or more as compared with the conventional art.

Therefore, when the electrostatic discharge protection circuit of this embodiment is used, the gate insulating film protection of the MOS transistor constituting the semiconductor memory is prevented since the electrostatic discharge operation is performed by turning on the gate of the NMOS transistor N11, which is an electrostatic discharge protection element, at 4.12V. It is more effective than before.

In addition, since the voltage that can withstand the gate insulating film of the NMOS transistor is not destroyed, the gate insulating film is proportional to the thickness, and thus the thickness of the gate insulating film of the NMOS transistor used in the internal circuit of the semiconductor device can be reduced by using the electrostatic discharge protection circuit of this embodiment. It has an effect.

6 is a diagram illustrating an electrostatic discharge protection circuit according to a second embodiment of the present invention. As shown in FIG. 6, the electrostatic discharge protection circuit according to the second embodiment of the present invention replaces the resistor R13 of the electrostatic discharge protection circuit according to the first embodiment of FIG. 4 with a resistive NMOS transistor N22. Has one configuration. Here, the NMOS transistor N22 preferably has a diode form in which a drain and a gate are connected together.

In addition, the electrostatic discharge protection circuit according to the second embodiment of the present invention may include a trigger voltage reduction unit for preventing the NMOS transistor N21, which is an electrostatic discharge protection element, from being operated by the leakage current of the PMOS transistor P21 during normal operation. In addition, 220 further includes a leakage preventing NMOS transistor N23.

First, the operation of the resistance NMOS transistor N22 in the occurrence of static electricity will be described. When the PMOS transistor P21 of the trigger voltage reducing unit 220 is turned on by the driving voltage of the driver 210, an electrostatic current flows to the ground voltage supply pad through the resistor R22 and the resistance NMOS transistor N22.

That is, when a voltage equal to or greater than the threshold voltage of the resistance NMOS transistor N22 is applied to the gate of the resistance NMOS transistor N22 by the electrostatic current, the resistance NMOS transistor N22 is turned on to operate as a diode. Therefore, the resistor NMOS transistor N22 receives a constant voltage corresponding to the threshold voltage. The voltage applied to the resistance NMOS transistor N22 may be applied to the substrate of the NMOS transistor N21 as the substrate trigger voltage VS.

When the substrate trigger voltage VS is generated by using a resistor NMOS transistor N22 that operates as a diode, the NMOS transistor is applied by applying a constant voltage to the substrate of the NMOS transistor N21, which is an electrostatic discharge protection device, regardless of the amount of electrostatic current. There is an advantage that can stabilize the operation of (N21).

The following describes an NMOS transistor N23 for preventing leakage in normal operation without generating static electricity. In a normal operation without static electricity, a power supply voltage of a DC component is applied to a power supply voltage supply pad, and the driving unit 210 applies a power supply voltage of a 'HIGH' state to the trigger voltage reduction unit 220 as a driving voltage. do.

At this time, the leakage preventing NMOS transistor N23 of the trigger voltage reducing unit 220 is turned on to maintain the gate voltage of the NMOS transistor N21 which is an electrostatic discharge protection element at a ground voltage state.

Therefore, the leakage preventing NMOS transistor N23 prevents the NMOS transistor N21, which is an electrostatic discharge protection element, from being driven by the leakage current of the PMOS transistor P21 included in the trigger voltage reducing unit 220 during normal operation.

Since other components and operations of the electrostatic discharge protection circuit according to the second embodiment are the same as those described in the first embodiment, detailed description thereof will be omitted.

In addition, the MOS transistors P21, N22, and N23 included in the trigger voltage reduction unit 220 of the electrostatic discharge protection circuit according to the second embodiment may be replaced with bipolar transistors that perform the same function. 7 is a diagram illustrating this.

 The operation process of the bipolar transistor can be easily inferred from the operation of the MOS transistors of FIGS. 4 and 6 by those skilled in the art, and a detailed description thereof will be omitted.

As described above, the electrostatic discharge protection circuit of the present invention configures a semiconductor device because the electrostatic discharge protection circuit can operate at a low trigger voltage by applying the voltage generated in the trigger circuit to the gate and the substrate of the electrostatic discharge protection device. The gate insulating film protection of the MOS transistor is more effective than before.

In addition, the electrostatic discharge protection circuit of the present invention can reduce the thickness of the gate insulating film of the NMOS transistor used in the internal circuit of the semiconductor device has an advantageous effect in the development of high-speed, high-integration semiconductor device and ensuring mass production.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (18)

  1. A driving unit generating a driving voltage by using a voltage drop generated by an electrostatic current due to static electricity;
    A trigger voltage reduction unit driven by the driving voltage and generating a gate trigger voltage and a substrate trigger voltage through voltage distribution using the electrostatic current; And
    An electrostatic discharge protection unit configured to discharge the static electricity by receiving the gate trigger voltage and the substrate trigger voltage;
    Electrostatic discharge protection circuit comprising a.
  2. The method of claim 1, wherein the driving unit
    A first resistor generating a driving voltage by generating a voltage drop by an electrostatic current due to static electricity flowing into the first pad;
    A capacitor connected to the first resistor and flowing the electrostatic current to a second pad;
    Electrostatic discharge protection circuit.
  3. The method of claim 2, wherein the trigger voltage reducing unit
    Switching means for interrupting the electrostatic current by the drive voltage;
    A second resistor connected to said switching means, and
    Resistance means connected in series with said second resistor,
    Generating a gate trigger voltage and a substrate trigger voltage through voltage distribution using the second resistor and the resistance means;
    Electrostatic discharge protection circuit.
  4. The method of claim 3, wherein the switching means
    PMOS transistor
    Electrostatic discharge protection circuit.
  5. The method of claim 3, wherein the switching means
    Bipolar transistor
    Electrostatic discharge protection circuit.
  6. The method of claim 3, wherein the resistance means
    Third resistance
    Electrostatic discharge protection circuit.
  7. The method of claim 3, wherein the resistance means
    A gate and a drain are the first NMOS transistors commonly connected to the second resistor and operating as a diode.
    Electrostatic discharge protection circuit.
  8. The method of claim 3, wherein the resistance means
    A collector and a base are bipolar transistors which are connected to the second resistor and operate as diodes in common.
    Electrostatic discharge protection circuit.
  9. The method of claim 3, wherein the electrostatic discharge protection unit
    A second NMOS transistor having a drain connected to the first pad, a gate to which the gate trigger voltage is applied, a substrate to which the substrate trigger voltage is applied, and a source connected to the second pad;
    Electrostatic discharge protection circuit.
  10. The method of claim 9,
    When the power supply voltage is supplied to the first pad, the power supply voltage is driven by the power supply voltage to discharge the voltage applied to the gate of the NMOS transistor by the leakage current of the switching means to the second pad, thereby providing the second NMOS transistor. Further comprising leakage preventing means for preventing the turning on
    Electrostatic discharge protection circuit.
  11. A driving unit generating a driving voltage by using a voltage drop generated by an electrostatic current due to static electricity;
    Switching means for interrupting the electrostatic current by the drive voltage;
    Voltage distribution means for generating a gate trigger voltage and a substrate trigger voltage by dividing a voltage by using the electrostatic current by the switching means; And
    An electrostatic discharge protection unit configured to discharge the static electricity by receiving the gate trigger voltage and the substrate trigger voltage;
    Electrostatic discharge protection circuit comprising a.
  12. The method of claim 11, wherein the driving unit
    A first resistor generating a driving voltage by generating a voltage drop by an electrostatic current due to static electricity flowing into the first pad;
    A capacitor connected to the first resistor and flowing the electrostatic current to a second pad;
    Electrostatic discharge protection circuit.
  13. The method of claim 11, wherein the switching means
    PMOS transistor
    Electrostatic discharge protection circuit.
  14. The method of claim 11, wherein the switching means
    Bipolar transistor
    Electrostatic discharge protection circuit.
  15. The method of claim 11, wherein the voltage distribution means
    First resistance means connected to the switching means, and
    A second resistance means connected in series with said first resistance means,
    Generating a gate trigger voltage and a substrate trigger voltage through voltage distribution using the first and second resistance means.
    Electrostatic discharge protection circuit.
  16. The method of claim 15, wherein the second resistance means
    An NMOS transistor, in which a gate and a drain are commonly connected to the first resistance means and operating as a diode;
    An electrostatic discharge protection circuit, wherein a collector and a base are one of bipolar transistors connected to the first resistance means and operating as a diode.
  17. The method of claim 12, wherein the electrostatic discharge protection unit
    An NMOS transistor having a drain connected to the first pad, a gate to which the gate trigger voltage is applied, a substrate to which the substrate trigger voltage is applied, and a source connected to the second pad.
    Electrostatic discharge protection circuit.
  18. The method of claim 17,
    When the power supply voltage is supplied to the first pad, the power supply voltage is driven by the power supply voltage to discharge the voltage applied to the gate of the NMOS transistor by the leakage current of the switching means to the second pad so that the NMOS transistor is turned on. Further comprising leakage preventing means for preventing
    Electrostatic discharge protection circuit.
KR1020060031557A 2006-04-06 2006-04-06 ElectroStatic Discharge Protection Circuit KR100818086B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093497A (en) 2003-09-12 2005-04-07 Toshiba Corp Semiconductor device having protective circuit
JP2005235947A (en) 2004-02-18 2005-09-02 Fujitsu Ltd Electrostatic discharge protective circuit
US20060022272A1 (en) 2004-07-29 2006-02-02 Shiao-Shien Chen Electrostatic discharge protection device and circuit thereof
KR20060020849A (en) * 2004-09-01 2006-03-07 주식회사 하이닉스반도체 Circuit for protecting electrostatic discharge in semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093497A (en) 2003-09-12 2005-04-07 Toshiba Corp Semiconductor device having protective circuit
JP2005235947A (en) 2004-02-18 2005-09-02 Fujitsu Ltd Electrostatic discharge protective circuit
US20060022272A1 (en) 2004-07-29 2006-02-02 Shiao-Shien Chen Electrostatic discharge protection device and circuit thereof
KR20060020849A (en) * 2004-09-01 2006-03-07 주식회사 하이닉스반도체 Circuit for protecting electrostatic discharge in semiconductor device

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