KR20080076394A - Repair circuit and cantained it semiconductor memory device - Google Patents

Abstract

A repair circuit and a semiconductor memory device having the same are provided to decrease a size of the semiconductor memory device by enabling two adjacent banks to share the same repair circuit. A semiconductor memory device includes a repair circuit(40) and at least two banks(BANK2,BANK3). The repair circuit outputs a repair determination signal and plural repair block select signals in response to a bank active signal and an address signal. The banks commonly receive the repair determination signal and the repair block select signals and activate one of a normal word line and a repair word line in response to the bank active signal. The repair circuit includes a fuse set unit and a repair determining unit.

Description

Repair circuit and semiconductor memory device having same

1 is a block diagram of a semiconductor memory device having a repair circuit according to the prior art.

FIG. 2 is a block diagram of a repair circuit of each bank of FIG. 1. FIG.

3 is a block diagram showing the configuration of the fuse set of FIG.

4 is a block diagram illustrating a semiconductor memory device having a repair circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram of the repair circuit of FIG. 4. FIG.

6 is a block diagram showing the configuration of the fuse set of FIG.

FIG. 7 is a detailed circuit diagram of the fuse enable unit 60 of FIG. 6.

FIG. 8 is a detailed circuit diagram of a comparison circuit forming the fuse unit 62 of FIG. 6.

9 is a detailed circuit diagram of the fuse island 64 of FIG. 6.

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a repair circuit for replacing a defective cell.

In general, in order to prevent a decrease in yield due to a failure of some cells, the semiconductor memory device may have an extra redundancy cell in the semiconductor memory device in advance. The address and the column address are divided to replace the word line WL in the case of the row defect, and to replace the column select signal Yi in the case of the column defect. The circuit which intervenes in such a repair operation is called a repair circuit.

Referring to FIG. 1, a semiconductor memory device having a repair circuit according to the related art includes repair circuits 10 and 12 in bank units. Hereinafter, like reference numerals in the drawings denote like parts.

Specifically, there are several cell blocks <0: N> in each bank BANK <0: 1>. Although not shown in each cell block <0: N>, there is a cell mat including a main word line MWL and a repair word line RMWL, a driver for driving each of them, and a control circuit for controlling driving.

Each of the repair circuits 10 and 12 outputs the repair determination signal NXE and the repair block selection signal HITB <0: N> by the bank active signal ACT, the low address signal XADD <0: N> and the power-up signal PWR_UP.

Each bank BANK <0: 1> receives an internal low address signal BAX <0: M> having active information and decoded row address information and a block selection signal BS <0: N> and receives a specific cell block <0: N>. Is selected and the main word line MWL driver or the repair word line RMWL driver is driven by the repair determination signal NXE and the repair block selection signal HITB <0: N> applied from the corresponding repair circuit 10 or 12.

Referring to FIG. 2, the repair circuit 10 includes a fuse set unit 20 that outputs a repair block selection signal HITB <0: N> to a bank BANK <0>, and a repair determination unit 22 that outputs a repair determination signal NXE. It is configured to include.

Here, the fuse set 20 includes a plurality of fuse sets <0: N>, the number of which physically corresponds to the number of repair word lines RMWL existing in the cell block. For example, when there is one repair word line RMWL in each of the N + 1 cell blocks <0: N>, N + 1 fusesets <0: N> are required. Therefore, in the two bank structure, two (N + 1) fuse sets are required.

Each fuse set <0: N> constituting the fuse set unit 20 receives a bank active signal ACT <0>, a power-up signal PWR_UP, and a low address signal XADD <0: N>, and a repair block selection signal HITB <0: N> is outputted to the corresponding cell block <0: N>, and the repair determination unit 22 receives the repair block selection signal HITB <0: N> to receive the repair determination signal NXE in all of the banks BANK <0>. Commonly applied to cell blocks <0: N>.

Referring to FIG. 3, the fuse set <0> includes a fuse enable unit 30 which outputs a fuse enable signal FUSE_EN, which is fuse set use information, and repair address information and low address signal XADD <0 built in by a fuse cut. A repair block selection signal is obtained by combining: N> for each bit and outputting the comparison signal HIT <0: N> and the comparison signal HIT <0: N> and the bank active signal ACT <0>. And a fuse island portion 34 for outputting HITB <0>.

Next, the operation of the repair circuit 10 for repairing the defective cell in the cell block <1> of the bank BANK <0> to the repair word line RMWL0 arranged in the cell block <0> of the same bank BANK <0> will be described. see.

The fuse set unit 20 outputs the repair block selection signal HITB <0> activated at a low level through the fuse set <0> corresponding to the cell block <0>. Specifically, the fuse enable unit 30 of the fuse set <0> cuts the fuse to activate the fuse enable signal FUSE_EN, and outputs the fuse enable unit 32. The repair address information is compared with the input low address signal XADD <0: N> to activate and output the comparison signals HIT <0: N>, and the fuse island 34 is brought to a low level in synchronization with the active signal ACT <0>. Outputs the repair block selection signal HITB <0> that is activated.

The repair determination unit 22 activates and outputs the repair determination signal NXE when any one of the repair block selection signals HITB <0: N> is activated at a low level. Therefore, the repair determination unit 22 of all the cell blocks <0: N> in the bank BANK <0> is output. The main wordline MWL driver is deactivated and the repair wordline RMWL0 of the cell block <0> is driven by the repair block select signal HITB <0> to activate the repair wordline RMWL0.

As described above, the conventional semiconductor memory device is configured to repair a defective cell using a repair circuit allocated to each bank. As the degree of integration increases, the probability of a defective cell increases. It is a factor that inhibits high integration.

Accordingly, an object of the present invention is to improve the area of a semiconductor memory device by sharing a repair circuit in adjacent banks.

Another object of the present invention is to improve the repair time by providing a repair circuit for repairing failures occurring at the same address in adjacent banks with one fuse set.

A semiconductor memory device including a repair circuit of the present invention for achieving the above object includes a repair circuit for outputting a repair determination signal and a plurality of repair block selection signals in response to a bank active signal and an address signal; And two or more banks receiving the repair determination signal and the plurality of repair block selection signals in common and activating any one of a normal word line and a repair word line in response to the bank active signal. do.

The repair circuit may include a fuse set unit configured to output the plurality of repair block selection signals in response to at least two bank active signals and the address signal; And a repair determination unit which receives the plurality of repair block selection signals and outputs the repair determination signal.

The fuse set includes a fuse set corresponding to the number of repair word lines included in the bank, and the fuse set activates and outputs a fuse enable island signal when at least one bank active signal is activated. A fuse enable unit; a fuse unit configured to output a plurality of comparison signals by comparing the address signal with repair address information in response to the fuse enable island signal; And a fuse island unit for activating and outputting the repair block selection signal when all of the comparison signals are activated in response to the fuse enable island signal.

The fuse enable unit may include: a plurality of fuse units corresponding to each bank one-to-one and outputting a fuse enable signal activated in response to a corresponding bank active signal; And a fuse enable sum unit configured to activate and output the fuse enable island signal when one or more of the fuse enable signals are activated, wherein the fuse unit selects a bank in which the repair word line exists. Circuit; And a NAND gate that activates and outputs the fuse enable signal when the output of the fuse circuit and the corresponding bank active signal are activated.

The fuse unit compares the repair address information with the address signal and outputs any one of the address signal or a signal obtained by logically combining the address signal and the fuse enable island signal as the comparison signal. It is configured to include.

The comparison unit may include: a fuse circuit configured to output a fuse signal corresponding to the repair address information; And an output unit configured to output, as the comparison signal, a signal obtained by logically combining the address signal or the address signal and the fuse enable island signal in response to the fuse signal.

The NAND gate may be configured to NAND-couple the address signal from the fuse enable island signal. A first passgate transferring the address signal when the fuse signal is activated; A second pass gate transferring an output of the NAND gate when the fuse signal is inactivated; And an inverter for inverting the signal output from the first or second passgate and outputting the signal as the comparison signal.

The fuse island unit may include: a plurality of NAND gates that NAND-couples the fuse enable island signal and the comparison signal to a predetermined number; A plurality of PMOS transistors connected in series between a power supply voltage terminal and an output node and receiving outputs of the respective NAND gates as gates; And a plurality of NMOS transistors connected in parallel between the output node and the ground voltage terminal and receiving the output of each NAND gate through a gate.

According to another aspect of the present invention, a repair circuit may be configured to receive a repair address and a bank active signal corresponding to at least two banks to selectively activate a repair word line included in the at least two banks. And outputting a repair determination signal.

The repair circuit may include a fuse set unit configured to activate and output any one of the repair block selection signals in response to the repair address and the bank active signal; And a repair determination unit that outputs the repair determination signal that is activated when at least one of the plurality of repair block selection signals is activated.

Here, the fuse set unit includes a fuse set corresponding to the number of repair word lines included in the bank.

The fuse set may include a fuse enable unit for activating and outputting a fuse enable island signal when at least one bank active signal is activated; A fuse unit configured to compare the repair address with built-in repair information and output a plurality of comparison signals in response to the fuse enable island signal; And a fuse island unit configured to activate and output the repair block selection signal when all of the plurality of comparison signals are activated in response to the fuse enable island signal.

The fuse enable unit may include: a plurality of fuse units corresponding to each bank one-to-one and outputting a fuse enable signal activated in response to a corresponding bank active signal; And a fuse enable island unit that activates and outputs the fuse enable island signal when at least one of the fuse enable signals is activated.

The fuse unit may include: a fuse circuit for selecting a bank in which the repair word line exists; And a NAND gate that activates and outputs the fuse enable signal when the output of the fuse circuit and the corresponding bank active signal are activated.

The fuse unit may include a plurality of comparison units configured to output one of the repair address or a signal obtained by logically combining the repair address and the fuse enable island signal as the comparison signal.

The comparison unit may include: a fuse circuit configured to output a fuse signal corresponding to the built-in repair address information; And an output unit configured to output, as the comparison signal, a signal obtained by logically combining the repair address or the repair address signal and the fuse enable island signal in response to the fuse signal.

The NAND gate may be configured to NAND-couple the repair address to the fuse enable island signal. A first passgate transferring the repair address when the fuse signal is activated; A second pass gate transferring an output of the NAND gate when the fuse signal is deactivated; And an inverter for inverting the signal output from the first or second passgate and outputting the signal as the comparison signal.

The fuse island unit includes a plurality of NAND gates configured to NAND-couple the fuse enable island signal and the comparison signal to a predetermined number; A plurality of PMOS transistors connected in series between a power supply voltage terminal and an output node and receiving outputs of the respective NAND gates as gates; And a plurality of NMOS transistors connected in parallel between the output node and the ground voltage terminal and receiving the output of each NAND gate through a gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention relates to a semiconductor memory device which reduces an area by sharing a repair circuit in adjacent banks, and presents a preferred embodiment as shown in FIG.

Referring to FIG. 4, in a semiconductor memory device having a repair circuit according to an embodiment of the present invention, a repair circuit 40 exists between adjacent banks BANK <2: 3>.

Specifically, there are several cell blocks <0: N> in each bank BANK <2: 3>. Although not shown in each cell block <0: N>, there is a cell mat including a main word line MWL and a repair word line RMWL, a driver for driving each of them, and a control circuit for controlling driving.

The repair circuit 40 repairs the judgment signal NXE and the repair block selection signal HITB <0: by the bank active signals ACT <2: 3>, the row address signals XADD <0: N> and the power-up signal PWR_UP corresponding to each bank. Outputs N>

Each bank BANK <2: 3> receives an internal low address signal BAX <0: M> and a block selection signal BS <0: N> having active information and decoded row address information, and receives a specific cell block <0: N>. Is selected, and either the main word line MWL driver or the repair word line RMWL driver is driven by the repair determination signal NXE and the repair block selection signal HITB <0: N>.

Referring to FIG. 5, the repair circuit 40 includes a fuse set unit 50 which outputs a repair block selection signal HITB <0: N> to a bank BANK <2: 3>, and a repair determination unit which outputs a repair determination signal NXE ( 52).

The fuse set unit 50 receives the bank active signal ACT <2: 3>, the power-up signal PWR_UP, and the low address signal XADD <0: N>, and receives the repair block selection signal HITB <0: N> from the bank <2: 3>. Is applied to the cell blocks < 0: N > corresponding thereto. For example, the repair block selection signal HITB <0> is commonly applied to the cell blocks <0> of both banks BANK <2: 3>. The repair determination unit 52 receives the repair block selection signal HITB <0: N> and outputs the repair determination signal NXE to all cell blocks <0: N> in the banks <2: 3> in common.

Here, the fuse set 50 includes a plurality of fuse sets <0: N>, the number of which physically corresponds to the number of repair word lines RMWL existing in the cell blocks in one bank <2 or 3>. For example, when there is one repair word line RMWL in each of the N + 1 cell blocks <0: N>, N + 1 fusesets <0: N> are required.

However, since the repair circuit 40 is shared by adjacent banks BANK <2: 3>, the number of fuse sets required in the two-bank structure is N + 1. This is a significantly reduced number compared to the number 2 (N + 1) of the fuse set required in the prior art.

Hereinafter, the fuse set constituting the fuse set unit 50 will be described in more detail with reference to FIGS. 6 to 9.

Referring to FIG. 6, the fuse set <0> may include a fuse enable unit 60 that outputs a fuse enable sum signal FUSE_EN_SUM that is usage information of the fuse set, a built-in repair address information and a low address signal XADD due to a fuse cut. The repair block selection signal HITB <0> is output by combining the fuse unit 62 which compares <0: N> for each bit and outputs the comparison signal HIT <0: N>, and the comparison signal HIT <0: N>. A fuse island portion 64 is included. The other fuse set <1: N> also performs the same configuration and function as in FIG.

Referring to FIG. 7, the fuse enable unit 60 may include a first fuse unit 72 which outputs a fuse enable signal FUSE_EN0 that is activated in synchronization with the bank active signal ACT <2>, and the bank active signal ACT <3>. A fuse that outputs a fuse enable signal FUSE_EN_SUM that is activated when at least one of a fuse enable signal FUSE_EN1 and a fuse enable signal FUSE_EN0 and FUSE_EN1 are activated at a low level in synchronization with the fuse The enable island portion 76 is configured.

The first fuse unit 72 outputs a signal for selecting a repair word line RMWL existing in the bank BANK <2> by the fuse cut, the output signal of the fuse circuit F1 and the bank active signal. The NAND gate NAND1 outputs a fuse enable signal FUSE_EN0 that is activated when all of ACT <2> is activated.

The second fuse unit 74 outputs a signal for selecting a repair word line RMWL existing in the bank BANK <3> by a fuse cut, and an output signal and a bank active signal ACT of the fuse circuit F2 and the fuse circuit F2. The NAND gate NAND2 outputs a fuse enable signal FUSE_EN1 that is activated when all of <3> are activated.

The fuse enable sum unit 74 includes a NAND gate NAND3 that outputs a fuse enable sum signal FUSE_EN_SUM that is activated when any one of the fuse enable signals FUSE_EN1 and FUSE_EN2 is activated.

8 shows one of the comparison units <0: N> constituting the fuse unit 62, and each of the comparison units <0: N> stores the repair address information and the low address signal XADD <0: N>, which are included in the comparison unit. In comparison, a comparison signal HIT <0: N> is output.

Specifically, the comparator <0> includes a fuse circuit F3 for outputting a fuse signal FUSE according to the repair address information, and a low address signal XADD <0> or a low address signal XADD in response to the fuse signal FUSE. And an output unit 80 for outputting any one of a signal obtained by logically combining < 0 > and the fuse enable sum signal FUSE_EN_SUM as a comparison signal HIT <0>.

The output unit 80 includes a pass gate PG1 that transmits the low address signal XADD <0> when the fuse signal FUSE is activated, and a low enable signal XADD <0> and the fuse enable sum signal when the fuse signal FUSE is deactivated. It includes the pass gate PG2 for transmitting the signal combining FUSE_EN_SUM by the NAND gate NAND4, and the inverter INV1 for inverting the output of the pass gate PG1 or PG2 and outputting it as the comparison signal HIT <0>. .

That is, the comparator <0> outputs a comparison signal HIT <0> which is activated at a high level when the low address signal XADD <0> matches the repair address information. Similarly, the comparison unit <0: N> performs the same configuration and function as that of FIG.

Therefore, when the input low address signal XADD <0: N> is a repair address, the fuse unit 62 activates and outputs the comparison signals HIT <0: N> at a high level, and at least one low level when the normal address is a normal address. Outputs the comparison signal HIT <0: N> which is deactivated.

Referring to FIG. 9, the fuse island unit 64 includes NAND gates NAND_1 to NAND_K (where K is a natural number) that NAND couples a fuse enable sum signal FUSE_EN_SUM and a comparison signal HIT <0: N> by a predetermined number. It is connected in parallel between the power supply voltage terminal VDD and the output node ND2 and in parallel between the PMOS transistors P_1 to P_K that receive the output of each NAND gate NAND_1 to NAND_K, the output node ND2 and the ground voltage terminal VSS. NMOS transistors N_1 to N_K that are connected to and receive outputs of the respective NAND gates NAND_1 to NAND_K may be implemented.

Accordingly, the fuse island unit 64 outputs a repair block selection signal HITB <0> that is activated at a low level when both the fuse enable sum signal FUSE_EN_SUM and the comparison signals HIT <0: N> are activated.

Next, the operation of the repair circuit 40 will be described.

First, when the defective cell generated in the cell block <1> in the bank BANK <2> is repaired by the repair word line RMWL0 located in the cell block <0> of the bank BANK <2>, the operation of the repair circuit 40 will be described. .

The fuse set unit 50 outputs the repair block selection signal HITB <0> activated at a low level by using the fuse set <0>.

Specifically, the fuse enable unit 60 of the fuse set <0> selects the bank BANK <2> by cutting the fuse embedded in the first fuse unit 72, and is synchronized with the bank active signal ACT <2>. Fuse enable sum signal FUSE_EN_SUM is activated and output.

The fuse unit 62 embeds the repair address information by cutting each fuse of the comparison unit <0: N> corresponding to the repair address information for the defective cell, and compares it with the input repair low address signal XADD <0: N>. The comparison signal HIT <0: N> is activated and output.

The fuse sum unit 64 activates and repairs the repair block selection signal HITB <0> at a low level when both the comparison signals HIT <0: N> and the fuse enable sum signal FUSE_EN_SUM are activated.

In this way, the repair block selection signal HITB <0> output from the fuse set <0> is output to each cell block <0> and the repair determination unit 52 of the bank BANK <2: 3>.

The repair determination unit 52 activates the repair determination signal NXE by activating the repair block selection signal HITB <0> and outputs all the cell blocks <0: N> in the bank BANK <2: 3> to output the main word line driver. Deactivate

Therefore, when each bank BANK <2: 3> operates independently, the bank signals BAX <0: M> and the block selection signal BS <0> of the bank BANK <2> are activated, so that the cell blocks of the bank BANK <2> are activated. The repair word line RMWL0 disposed at <0> is activated.

On the other hand, when the adjacent banks BANK <2: 3> operate simultaneously, the internal low address signals BAX <0: M> and the block select signal BS <0> of the banks BANK <2: 3> are activated at the same time so that the two banks BANK < If a defect occurs at the same address of 2: 3>, it can be repaired with one fuse set <0>, thereby further improving the repair time and the area of the repair circuit.

Therefore, according to the present invention, the repair circuit is shared and used in adjacent banks, thereby reducing the area of the semiconductor memory device.

In addition, according to the present invention, when a failure occurs at the same address in both adjacent banks, the repair time and area are improved by repairing with one fuse set.

Claims (20)

A repair circuit configured to output a repair determination signal and a plurality of repair block selection signals in response to the bank active signal and the address signal; And Two or more banks receiving the repair determination signal and the plurality of repair block selection signals in common and activating any one of a normal word line and a repair word line in response to the bank active signal; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 1, The repair circuit A fuse set unit configured to output the plurality of repair block selection signals in response to at least two bank active signals and the address signal; And A repair determination unit which receives the plurality of repair block selection signals and outputs the repair determination signal; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 2, And the fuse set includes a fuse set corresponding to the number of repair word lines included in the bank. The method of claim 3, wherein The fuse set is A fuse enable unit for activating and outputting a fuse enable island signal when at least one bank active signal is activated; A fuse unit configured to output a plurality of comparison signals by comparing the address signal with repair address information in response to the fuse enable island signal; And A fuse island unit activating and outputting the repair block selection signal when all of the comparison signals are activated in response to the fuse enable island signal; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 4, wherein The fuse enable portion A plurality of fuse units corresponding to each bank one-to-one and outputting a fuse enable signal activated in response to a corresponding bank active signal; And A fuse enable sum unit for activating and outputting the fuse enable island signal when one or more of the fuse enable signals are activated; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 5, wherein The fuse unit A fuse circuit for selecting a bank in which the repair word line exists; And A NAND gate that activates and outputs the fuse enable signal when the output of the fuse circuit and the corresponding bank active signal are activated; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 4, wherein The fuse unit includes a plurality of comparison units configured to compare the repair address information with the address signal and output one of the address signal or a signal obtained by logically combining the address signal and the fuse enable island signal as the comparison signal. A semiconductor memory device having a repair circuit, characterized in that. The method of claim 7, wherein The comparison unit A fuse circuit configured to output a fuse signal corresponding to the repair address information; And An output unit for outputting a signal obtained by logically combining the address signal or the address signal with the fuse enable island signal in response to the fuse signal; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 8, The output unit A NAND gate configured to NAND-couple the address signal to the fuse enable sum signal; A first passgate transferring the address signal when the fuse signal is activated; A second pass gate transferring an output of the NAND gate when the fuse signal is deactivated; And An inverter for inverting the signal output from the first or second passgate and outputting the signal as the comparison signal; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 4, wherein The fuse island portion A plurality of NAND gates configured to NAND-couple the fuse enable sum signal and the comparison signal to a predetermined number; A plurality of PMOS transistors connected in series between a power supply voltage terminal and an output node and receiving outputs of the respective NAND gates as gates; And A plurality of NMOS transistors connected in parallel between the output node and a ground voltage terminal and receiving outputs of the respective NAND gates through a gate; The semiconductor memory device having a repair circuit, characterized in that comprising a. The repair circuit may be configured to receive a repair address and a bank active signal corresponding to at least two banks, and output a plurality of repair block selection signals and repair determination signals for selectively activating repair word lines included in the at least two banks. . The method of claim 11, The repair circuit A fuse set unit activating and outputting any one of the plurality of repair block selection signals in response to the repair address and the bank active signal; And A repair determination unit configured to output the repair determination signal activated when at least one of the plurality of repair block selection signals is activated; Repair circuit, characterized in that configured to include. The method of claim 12, And the fuse set includes a fuse set corresponding to the number of repair word lines included in the bank. The method of claim 13, The fuse set is A fuse enable unit for activating and outputting a fuse enable island signal when at least one bank active signal is activated; A fuse unit configured to compare the repair address with built-in repair information and output a plurality of comparison signals in response to the fuse enable island signal; And A fuse island unit configured to activate and output the repair block selection signal when all of the plurality of comparison signals are activated in response to the fuse enable island signal; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 14, The fuse enable portion A plurality of fuse units corresponding to each bank one-to-one and outputting a fuse enable signal activated in response to a corresponding bank active signal; And A fuse enable sum unit configured to activate and output the fuse enable island signal when at least one of the fuse enable signals is activated; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 15, The fuse unit A fuse circuit for selecting a bank in which the repair word line exists; And A NAND gate that activates and outputs the fuse enable signal when the output of the fuse circuit and the corresponding bank active signal are activated; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 14, The fuse unit may include a plurality of comparison units configured to output one of the repair address or a signal obtained by logically combining the repair address and the fuse enable island signal as the comparison signal. Device. The method of claim 17, A comparison circuit configured to output a fuse signal in response to the built-in repair address information; And An output unit outputting the repair address or a signal obtained by logically combining the repair address signal and the fuse enable island signal as the comparison signal in response to the fuse signal; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 18, The output unit A NAND gate configured to NAND-couple the repair address to the fuse enable sum signal; A first passgate transferring the repair address when the fuse signal is activated; A second pass gate transferring an output of the NAND gate when the fuse signal is deactivated; And An inverter for inverting the signal output from the first or second passgate and outputting the signal as the comparison signal; The semiconductor memory device having a repair circuit, characterized in that comprising a. The method of claim 14, The fuse island portion A plurality of NAND gates configured to NAND-couple the fuse enable sum signal and the comparison signal to a predetermined number; A plurality of PMOS transistors connected in series between a power supply voltage terminal and an output node and receiving outputs of the respective NAND gates as gates; And A plurality of NMOS transistors connected in parallel between the output node and a ground voltage terminal and receiving outputs of the respective NAND gates through a gate; The semiconductor memory device having a repair circuit, characterized in that comprising a.

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