KR101046276B1 - Semiconductor Integrated Circuit Including Column Redundancy Fuse Block - Google Patents

Abstract

A semiconductor integrated circuit device capable of securing a high effective net die is disclosed. The disclosed semiconductor integrated circuit device includes a semiconductor chip having an edge region and a bank region disposed inside the edge region, and a column redundancy fuse block disposed in the edge region.

Description

Semiconductor Integrated Circuit Including Column Redundancy Fuse Block

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a column redundancy fuse block.

As the size of each element constituting the semiconductor integrated circuit device becomes smaller and the number of elements included in one semiconductor chip becomes larger, the level of defect density also increases. This increase in the defect density is a direct cause of lowering the yield of the semiconductor device, and in severe cases, the wafer on which the semiconductor element is formed must be disposed of.

In order to lower the defect density, a redundancy circuit has conventionally been proposed to replace defective cells with spare cells. In the case of a semiconductor memory device, a redundancy circuit (or a fuse circuit) may be provided for each of row-based wiring (eg, word lines) and column-based wiring (eg, bit lines). And a fuseset array for storing address information. The fuseset array consists of a plurality of fusesets comprising a plurality of fuse wires, and the programming of each fuseset may be done by selective laser blowing of the fuse wires.

In particular, a column redundancy circuit block (Y-Fuse) for repairing column-based wiring is provided in the column control block 20 as shown in FIG. The column control block 20 is disposed in a space between banks arranged adjacent to each other in a column direction, and as shown in FIG. 2, a main decoder (not shown), a pre decoder 21, and a redundancy circuit part are shown. And (23).

The main decoder (not shown) is a circuit portion for designating an address position, and the pre decoder 21 is a circuit portion for receiving a column address signal and generating a column selection signal. The redundancy circuit section 23 may be composed of a fuse circuit section 25 and a fuse set array 27. The fuse circuit unit 25 is configured to provide the predecoder 21 with redundancy selected according to whether the fuse set array 27 is blown with a fuse. Here, reference numeral 10 denotes a chip, and 30 denotes a pad region.

However, current semiconductor memory devices are designed such that no wiring or layer is disposed on the fuse set (not shown) so that the wiring is not affected when the fuse is blown by applying energy (for example, a laser) after the chip is completed. As a result, the data input / output wirings and the like are arranged so as not to pass the upper portion of the fuse set. This places restrictions on the wiring and circuit arrangement.

In addition, the speed at which the pitch between fuses decreases due to the laser beam error tolerance is relatively slow compared to the speed at which the integration and the process technology are developed, so that the area of the fuses, that is, the fuseset array 27 in the semiconductor chip occupies. The share can be increased rather. This is an obstacle to securing an effective net die of the semiconductor memory device.

In particular, in the conventional case, since the fuse circuit unit 25 and the fuse set array 27 must be separately arranged in a space partitioned by the redundancy circuit unit 23, the fuse sets constituting the fuse set array 27 are inevitably multipled. Had to be arranged in rows. As a result, the area of the column control block 20 is increased, which makes it difficult to increase the area of the bank.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device capable of improving placement efficiency.

Another object of the present invention is to provide a semiconductor integrated circuit device capable of securing a high effective net die.

A semiconductor integrated circuit device according to an aspect of the present invention includes a semiconductor chip having an edge region and a bank region disposed inside the edge region, and a column redundancy fuse block disposed in the edge region.

According to another aspect of the present invention, a semiconductor integrated circuit device includes a semiconductor chip including a bank region in which a plurality of banks are arranged in an edge region and an edge region in a row direction and a column direction with a predetermined rule. A column redundancy fuse block including a column address fuse set array arranged in the parallel edge regions and a fuse blowing information block for detecting fuse blowing information in the fuse set array, and the bank region between adjacent banks in the column direction And a column control block configured to receive an output signal of the fuse blowing information block, determine redundancy, and output a column selection signal or a spare column selection signal.

According to still another aspect of the present invention, a semiconductor integrated circuit device includes an edge region including a column redundancy fuse block, a first bank located in a lower column of the edge region, and a first column control block located in a lower column of the first bank. And a second bank located in a lower column of the first column control block, and a second column control block located in a lower column of the second bank.

According to the present invention, a column redundancy fuse block including a fuseset array is provided outside the bank, that is, in the edge region of the semiconductor chip. As a result, the interval between the banks constituting the semiconductor memory device can be reduced, the effective net die ratio can be increased, the wiring arrangement efficiency can be improved, and crosstalk between wirings can be prevented and signal delay can be reduced.

In addition, the column redundancy circuit which receives the row system information substantially arranges the chip edge region, and the column redundancy circuit which receives the column address is provided in the column control block between banks, thereby improving the semiconductor memory memory without increasing address access time. The placement efficiency of the device can be greatly improved.

1 is a plan view showing a general semiconductor chip,
2 is an enlarged block diagram illustrating a redundancy circuit unit of a general semiconductor chip;
3 is a plan view of a semiconductor chip in which column redundancy fuse blocks are disposed outside according to an embodiment of the present invention;
4 is an enlarged block diagram of portion “X” of FIG. 3;
5A is a block diagram illustrating a relationship between a unit fuse set and a mat according to an embodiment of the present invention;
5B is a plan view of a fuseset according to an embodiment of the present invention;
5B is a plan view of a fuse set according to another embodiment of the present invention;
6 is a block diagram illustrating a fuse determination circuit block according to an embodiment of the present invention;
7 is a detailed circuit diagram of a fuse enable circuit according to an embodiment of the present invention;
8 is a detailed circuit diagram of a fuse determination circuit unit according to an embodiment of the present invention;
9 is a block diagram showing a configuration of a column redundancy determining circuit unit according to an embodiment of the present invention;
FIG. 10 is a detailed circuit diagram of a sub comparing unit constituting the column redundancy determining circuit unit of FIG. 9;
11 is a block diagram illustrating a main portion of a semiconductor chip according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 3, the semiconductor chip 100 includes an edge region E and a bank region B positioned inside the edge region E. Referring to FIG.

The edge area E includes a column redundancy fuse block 200 for performing a column redundancy operation.

The bank area B may include a pad area 150 disposed at the center and a plurality of banks spaced apart from each other with a predetermined rule in the row and column directions at both bank areas B around the pad area 150. ).

FIG. 4 is an enlarged view of a portion “X” of FIG. 3. Referring to FIG. 4, the column redundancy fuse block 200 may include a semiconductor chip outside the edge bank Bank4 as described above. The column control block 500 is disposed in an edge region E of 100, and the column control block 500 is disposed in a bank region B between adjacent banks and banks in the column direction.

The column redundancy fuse block 200 may include a fuse set array 210 and a fuse blowing determination block 250. The column control block 500 may include a first column control block 300 and a second column control block 400, and the first column control block 300 and the second column control block 400 may be interposed between banks. Can be placed in different spaces. For example, the second column control block 300 and the second column control block 400 may be alternately arranged in a space between banks generated in the column direction.

Here, a main decoder may be disposed in the first column control block 300, and a column redundancy determination circuit unit 410 and a pre decoder 490 may be disposed in the second column control block 400.

5A is a plan view illustrating one fuseset of the fuseset array 210 of the column redundancy fuse block 200. As shown in FIG. 5A, the unit fuse set 211 may be provided to correspond to two mats MAT adjacent in a row direction among a plurality of mats constituting a bank. The unit fuse set 211 may be configured of a plurality of fuse wires 211a and a pair of guard ring fuses 211b disposed at an outer portion thereof. In this embodiment, since the fuse set 211a and the plurality of fuse wires 211a constituting the fuse set 211 are arranged in the outer periphery of the chip, the margin for the wiring arrangement is reduced. As such, they can be arranged in the form of a single row.

In detail, in the conventional case in which redundancy circuit blocks are located between banks (see FIG. 2), a fuse circuit and a fuseset array including a fuse blowing information unit and a column address comparison unit have to be integrated to correspond to two mats. In order to facilitate the wiring arrangement, the fuse set array had to be arranged in multiple layers. When the fuse set array is formed in a multi-layer, the length of the redundancy circuit block naturally increases, and further, the guard ring fuse 211b disposed for each fuse set 211 to protect the plurality of fuse wires 211a. May also increase, resulting in area waste.

However, when the fuse set array 210 is disposed outside the chip as in the present embodiment, since the arrangement and bypass of the wirings need not be considered, the fuse lines 211a as well as the fuse set 210 may be arranged in a line. Can be. Therefore, the area of the column-based redundancy fuse block 200 can be significantly reduced.

In this case, the fuse wires 211 may be configured to have one blowing area, as shown in FIG. 5B, or may have at least one blowing area, as shown in FIG. 5C.

Referring to FIG. 6, the fuse blowing information block 250 is configured to generate a fuse blowing determination signal yra according to whether a column address fuse is blown. The fuse blowing information block 250 may include a fuse enable circuit unit 260 and a fuse blowing determination circuit unit 280.

The fuse enable circuit unit 260 receives a control signal such as a row active signal ACT and a signal having row information, such as a block selection signal bs <0: 3>, and receives the fuse blowing determination circuit unit. And generate a fuse enable signal yren for driving 280.

More specifically, as shown in FIG. 7, the fuse enable circuit unit 260 includes a driving unit 262, a transfer unit 263, a fuse blowing check unit 264, a latch unit 266, and an output unit 268. It may include.

The driver 262 is configured to provide a power supply voltage VDD to the fuse blowing check unit 264 according to a control signal, for example, a row active signal ACT. The driver 262 may be a PMOS transistor P1.

The transfer unit 263 is configured to discharge the voltage transmitted from the fuse blowing check unit 264 to the ground according to the low active signal ACT that is a control signal. The second driver 263 may be an NMOS transistor N1.

The fuse blowing check unit 264 may include a plurality of column address fuses f1, f2, f3, and f4 and switching elements N2, N3, N4, and N5, and any one of the column address fuses f1 and f2. when blowing, f3, f4), it is configured to output a high signal. One end of the column address fuses f1, f2, f3, and f4 is connected to the driving unit 262, and the switching elements N2, N3, N4, and N5 are connected to the column address fuses f1, f2, f3, and corresponding to the other end of f4), respectively. The switching elements N2, N3, N4, and N5 may be NMOS transistors that are selectively turned on / off in response to the block select signals bs <0: 3>. The switching elements N2, N3, N4, and N5 are opened and closed according to whether the block selection signals bs <0: 3> are enabled. The column address fuses f1, f2, f3, and f4 may have the structure of FIG. 5B or 5C.

The latch portion 266 is configured to latch the output signal of the block selector 264. The latch unit 266 may be configured of first and second inverters IN1 and IN2.

The output unit 268 is configured to enable the fuse enable signal yren when the fuse blowing is confirmed from the fuse blowing check unit 264 and the low active signal ACT is enabled high. do. The output unit 268 may include a third inverter IN3, a NOR gate NOR0, a fourth inverter IN4, and a fifth inverter IN5. The third inverter IN3 inverts the low active signal ACT, and the NOR gate NOR1 receives the output signal of the latch unit 266 and the output signal of the third inverter IN3 to perform a NOR operation. . The fourth and fifth inverters IN4 and IN5 are continuously connected to amplify the output signal of the NOR gate NOR1 to generate a fuse enable signal yren.

The fuse enable circuit unit 260 is operated as follows.

When the low active signal ACT is enabled at a logic low, the driving unit 262 is driven to transfer the driving voltage VDD to the fuse blowing confirmation unit 264. When any one of the column address fuses f1, f2, f3, and f4 is blown, and the corresponding switching elements N1, N2, N3, and N4 are turned on, the fuse blowing check unit 264 may perform the column address fuse f1. Since the power supply voltage VDD is not transmitted through f2, f3, and f4, a high signal is output. If all of the column address fuses f1, f2, f3, and f4 are not blown, the power is supplied by the column address fuses f1, f2, f3, and f4 and corresponding switching elements N2, N3, N4, and N5. The voltage VDD is transmitted to the transfer unit 263 and discharged through the ground.

The latch unit 266 and the output unit 268 latch and buffer the output signal of the fuse blowing check unit 264 to output a fuse enable signal yren.

Referring to FIG. 8, when the fuse enable signal yren is enabled high and one of the column address fuses f1, f2, f3, and f4 is blown, the fuse blowing determination circuit unit 280 goes low. And generate the enabled fuse blowing determination signal yra.

The fuse blowing decision circuit unit 280 includes a first driver 282, a second driver 283, a transfer unit 284, a fuse blowing check unit 285, a latch unit 287, and an output unit 289. Can be.

The first driver 282 is configured to transfer the power supply voltage VDD to the fuse blowing check unit 285 as the row active signal ACT is enabled to a logic low. The first driver 282 may be a PMOS transistor P2.

The second driver 283 is configured to transfer the voltage provided from the fuse blowing check unit 285 to the transfer unit 284 according to the enable of the fuse enable signal yren. The second driver 283 may be an NMOS transistor N6.

The transfer unit 284 is configured to discharge the voltage transferred from the second driver 283 to the ground Vss when the row active signal ACT is logic high. The transfer unit 284 may be an NMOS transistor N7.

The fuse blowing check unit 285 may have the same circuit configuration as the fuse blowing check unit 285 of the fuse enable circuit unit 285. That is, the plurality of column address fuses f1, f2, f3, and f4 and switching elements connected thereto may be configured, for example, NMOS transistors N8, N9, N10, and N11.

The latch unit 287 may include two inverters IN6 and IN7, and the output unit 289 may be an inverter IN8 for inverting and amplifying the output signal of the latch unit 287.

The fuse blowing decision circuit unit 280 as described above is operated as follows.

When the row active signal ACT is enabled to a logic low and the fuse enable signal yren is enabled to be high, the first and second drivers 282 and 283 are driven. In this state, if any one of the column address fuses f1, f2, f3, and f4 of the fuse blowing confirmation unit 285 is blown, the power supply voltage VDD is not transmitted to the transfer unit 284, and thus the fuse blowing check is performed. The unit 285 outputs a high signal. The output signal of the fuse blowing confirmation unit 285 passes through the latch unit 287 and the output unit 289 having an inverted amplification function, and outputs a fuse blowing determination signal yra having a logic low state.

Referring back to FIG. 4, the column redundancy determination circuit 410 of the second column control block 400 compares the fuse blowing determination signal yra and the column address signal bay <2: 7,9>. And a repair select signal (yrhitb <2: 7, 9>) corresponding to each column.

The predecoder 490 receives a repair selection signal yrhitb <2: 7,9> and a column address signal bay <2: 7,9> generated by the column redundancy circuit block 410 to select a column. And generate a signal Yi or a spare column select signal SYi.

As shown in FIG. 9, the column redundancy determining circuit unit 410 may include a column address signal bay <2: 7,9>, a fuse blowing determination signal yra <2: 7,9>, and an inverted fuse enable. Receives a signal yrenb and compares the column address signal bay <2: 7,9> and the fuse blowing determination signal yra <2: 7,9> with a repair selection signal yrhitb <2: 7,9 And a comparator 420 for generating>) The comparator 420 may include as many sub-comparators as the number of input fuse blowing determination signals yra <2: 7,9>. .

Referring to FIG. 10, the sub comparator 430 may include a redundancy generator 432, a comparator 434, and a buffer 436.

The redundancy generator 432 may include a first NOR gate NOR1, a second NOR gate NOR2, a first inverter IN11, a second inverter IN12, and a transfer gate TG.

The first NOR gate NOR1 performs a NOR operation on the inverted fuse enable signal yrenb and the fuse blowing determination signal yra <i>, where i is 2 to 7, and 9, and the second NOR gate NOR2 is The inverted fuse enable signal yrenb and the output signal of the first NOR gate NOR1 are NOR-calculated. The first inverter IN11 inverts the output signal of the second NOR gate NOR2 and transmits the inverted signal to the transfer gate TG. The transfer gate TG is the column address signal inverted by the second inverter IN12 according to the output signal of the second NOR gate NOR2 and the output signal of the first inverter IN11, i / i <i>, i Passes 2 to 7 and 9).

The comparator 434 may include a first PMOS transistor P11, a second PMOS transistor P12, a first NMOS transistor N12, a second NMOS transistor N13, and a third inverter IN3.

The first PMOS transistor P11 is a gate that receives the output signal of the first NOR gate NOR1 inverted by the third inverter IN3, a drain connected to the power supply voltage VDD, and a second PMOS transistor P12. It consists of a source connected to.

The second PMOS transistor P12 includes a gate configured to receive the inverted column address signal / bay <i>, a drain connected to the first PMOS transistor P11, and a source connected to the first NMOS transistor N11. do.

The first NMOS transistor N12 includes a gate configured to receive the inverted column address signal / bay <i>, a drain connected to the second PMOS transistor P12, and a source connected to the second NMOS transistor N13. do.

The second NMOS transistor N13 is connected to a gate receiving the inverted output signal of the first NOR gate NOR1, a drain and a ground voltage terminal Vss connected to the first NMOS transistor N12.

The buffer 436 is selectively turned on according to an output signal of the fourth inverter IN14 and the output signal of the fourth inverter IN14 to invert the inverted fuse enable signal yrenb, and transmits a power voltage VDD. It may be composed of a PMOS transistor P13.

When the inverted fuse enable signal yrenb is enabled (activated) low, the sub comparator 430 may perform a column address signal bay <i> and a corresponding fuse blowing determination signal yra <. If i>) is the same, it generates a logic low level repair select signal yrhitb <i>. On the other hand, when the inverted fuse enable signal yrenb is high or the column address signal bay <i> and the fuse blowing determination signal yra <i> are different from each other, to confirm that a defect has not occurred. Generate a logic high level repair select signal yrhitb <i>.

The generated repair select signal yrhitb <i> is transmitted to the predecoder 490. The predecoder 490 of the present embodiment responds to the repair select signal yrhitb <i> and is normal in the corresponding column. It is determined whether to output the column select signal Yi or the spare column select signal SYi.

In this embodiment, by arranging the column redundancy fuse block 200 including the fuse set array 210 outside the chip, the fuse set array 210 may be relatively disposed without considering the arrangement of the wiring, particularly the data input / output wiring. It can be placed with a wide margin. Accordingly, since there is no fuse set array 210 between the banks, the data input / output wires can be extended in a straight line, thereby improving power mesh characteristics.

Meanwhile, the general column redundancy fuse block includes both a fuse blowing information block and a column redundancy determining circuit unit to receive row-based information (eg, a block selection signal), but the column redundancy fuse block is disposed outside the chip according to the present embodiment. 200 is designed to include only the fuse blowing information block 250 together with the fuse set array 210, and the column redundancy determining circuit unit 410 is designed to be located in the column control block 410 between banks.

The column redundancy determining circuit unit 410 may be installed in the column redundancy fuse block 200 outside the chip. In this case, as shown in FIG. 11, the column redundancy determining circuit unit 410 may be provided with a column address signal bay < 2: 7,9>) and the repair decision signal yrhitb <2: 7,9> generated by the column redundancy decision circuit unit 410 are again decoded via the bank. As many delays b as to be delivered to 490, i.e., a total of a + b delays, may occur. As a result, the address access time tAA may be long.

On the other hand, as shown in the present embodiment, the column redundancy fuse block 200 is disposed outside the chip, and receives the column address signals bay <2: 7,9>, and the column redundancy that directly interacts with the predecoder 490. The decision circuit unit 410 is provided in the column control block 400 adjacent to the predecoder 490 so that the input delay of the column address signals bay <2: 7,9> and the repair decision signal yrhitb <2: 7, 9>) hardly occurs, so that the address access time tAA can be reduced. In the present embodiment, the fuse blowing decision signal yra is provided from the fuse blowing information block 250 to the column redundancy decision circuit unit 410 via a bank, but since the signal is not directly related to the address, It does not affect the access time tAA.

As described above in detail, according to the present invention, a column redundancy fuse block including a fuse set array is installed outside the bank. As a result, the interval between banks constituting the semiconductor memory device can be reduced, the effective net die ratio can be increased, the wiring arrangement efficiency can be improved, and crosstalk between wirings can be prevented and signal delay can be reduced.

In addition, the column redundancy circuit that receives the row-based information substantially is disposed outside the chip, and the column redundancy circuit that receives the column address is provided in the column control block between the banks, thereby increasing the address access time without increasing the address access time. The placement efficiency of the device can be greatly improved.

The present invention is not limited to the above embodiment.

In this embodiment, the logic low or logic high is enabled as an example, but since this can be enabled by logic high or logic low by a circuit change, if the signal of a level capable of driving subsequent circuit parts It will be interpreted as enabled or activated.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

100 semiconductor chip 150 pad region
200: column redundancy fuse block 210: fuse set array
250: fuse blowing information block 300: first column control block
400: second column control block 410: column redundancy determining circuit unit
490: predecoder 500: column control block

Claims (12)

A semiconductor chip including an edge region and a bank region in which a plurality of banks are arranged in a row direction and a column direction with a predetermined rule inwardly;
A column redundancy fuse block including a column address fuse set array arranged in the edge region parallel to the row direction and a fuse blowing information block for detecting fuse blowing information in the fuse set array; And
A column control block disposed in the bank region between adjacent banks in the column direction and configured to receive an output signal of the fuse blowing information block and determine redundancy and output a column selection signal or a spare column selection signal; Include,
The fuse blowing information block,
A fuse enable circuit unit configured to generate a fuse enable signal according to a block selection signal and whether the plurality of column address fuses are blown when the row active signal is enabled; And
And a fuse blowing determination circuit unit configured to receive the fuse enable signal and the block select row information signal and generate the fuse blowing determination signal when the row active signal is enabled. The method of claim 1,
The banks are composed of a plurality of mats,
One fuse set constituting the fuse set array is disposed so as to correspond to the two mats arranged adjacent in the row direction. delete The method of claim 1,
The column control block may include: a column redundancy determination circuit unit configured to receive the fuse blowing determination signal and the column address and generate a redundancy select signal for determining a column address to be repaired;
And a predecoder receiving the redundancy select signal and the column address and providing a column select signal or a spare column signal to the bank. The method of claim 4, wherein
And the column redundancy determining circuit unit and the predecoder are adjacent to each other in a space between banks arranged in parallel in the column direction. The method of claim 4, wherein
And the column redundancy determining circuit unit includes a comparing unit configured to compare the fuse blowing determination signal and the column address signal for each address. The method of claim 4, wherein
The column control block further comprises a main decoder. The method of claim 7, wherein
And the main decoder and the predecoder / column redundancy determining circuit unit are disposed in the bank region between the banks arranged in parallel in the column direction and alternately arranged in different spaces. An edge region comprising column redundancy fuse blocks;
A first bank positioned in a lower column of the edge region;
A first column control block positioned in a lower column of the first bank;
A second bank positioned in a lower column of the first column control block; And
A second column control block positioned in a lower column of the second bank,
The column redundancy fuse block may include a fuse set array including a plurality of fuse sets, and a fuse blowing information block configured to output a fuse blowing determination signal of a corresponding column according to whether a column address fuse is cut. The fuse set includes a plurality of fuse sets. The column address fuse of
The second column control block may receive the fuse blowing determination signal and the column address and generate a redundancy selection circuit unit for generating a redundancy selection signal for determining a column address to be repaired, and the redundancy selection signal and the column address. And a predecoder for providing a column select signal or a spare column signal to the first and second banks. The method of claim 9,
The fuse blowing information block
A fuse enable circuit unit configured to generate a fuse enable signal according to a block selection signal and whether the plurality of column address fuses are blown when the row active signal is enabled; And
And a fuse blowing determination circuit unit configured to receive the fuse enable signal and the block select row information signal and generate the fuse blowing determination signal when the row active signal is enabled. The method of claim 9,
And the first column control block comprises a main decoder for designating address positions of the first bank and the second bank. The method of claim 11,
And the column redundancy determining circuit unit includes a comparing unit configured to compare the fuse blowing determination signal and the column address signal for each address.

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