KR20080074084A - High sensitivity, high resolution detector devices and arrays - Google Patents

Abstract

Avalanche amplification structures (1) including electrodes (2) and (8), an avalanche region (3), a quantifier (4), an integrator (5), a governor (6), and a substrate (7) arranged to detect a weak signal composed of as few as several electrons are presented. Quantifier (4) regulates the avalanche process. Integrator (5) accumulates a signal charge. Governor (6) drains the integrator (5) and controls the quantifier (4). Avalanche amplifying structures (1) include: normal quantifier, reverse bias designs; normal quantifier, normal bias designs; lateral quantifier, normal bias designs; changeable quantifier, normal bias, adjusting electrode designs; normal quantifier, normal bias, adjusting electrode designs; and lateral quantifier, normal bias, annular integrator designs. Avalanche amplification structures (1) are likewise arranged to provide arrays of multi-channel devices. Structures have immediately applicability to devices critical to homeland defense.

Description

HIGH SENSITIVITY, HIGH RESOLUTION DETECTOR DEVICES AND ARRAYS}

The present invention relates to single-channel and multi-channel detectors capable of recording low-level signals comprising only a plurality of electrons. In particular, the present invention relates to an avalanche amplification device in which amplification is realized through a multi-layered, solid-state intelligent amplifier design.

Detecting and recording low-level signals is very difficult for a sensor device. For example, the sensitivity, selectivity, operating range, and arrayed arrangement of such devices require accurate detection of signals consisting of only a few electrons.

One widely used approach for detecting and recording low-level signals includes a charge-sensitive amplifier on a field effect transistor with a threshold sensitivity of dozens of electrons, which is solid by Albert JP Theuwissen. State Imaging with Charge-Coupled Device (published by Kluwer in 1995, ISBN 0-7923-3456-6).

Another approach involves an output video signal amplifier comprised of charge coupled devices, which ensures a sensitivity that is nearly similar to that of a charge-sensitive amplifier on a field effect transistor.

Another approach to sensing weak electrical signals is to use avalanche amplification or multiplication of signal carriers, which is generally the most sensitive and fast amplification method. Avalanche type devices include those described in Physics of Avalanche Photodiode in Semiconductors and Semimetals (published by Academic Press in 1985, Vol. 22) by F. Capasso.

Avalanche amplification is based on impact ionization occurring in a strong electric field, where the accelerated signal carriers ionize the atoms of the working medium of the amplifier, thus multiplication of the signal carriers (e.g., Causing duplication). However, at very high multiplication factors, it is difficult to stabilize the avalanche amplification operating point. In addition, the internal (excessive) noise level and response time increase rapidly as the propagation factor increases. Such conventional avalanche photodiodes use a relatively small (typically less than 10 ³ ) propagation factor M, which prevents the detection and recording of signals consisting of several electrons in a wide band.

Avalanche proliferation has also been applied for recording individually ionized particles using a Geiger-Muller counter, as described in USPN 4,303,861 by Ekstrom. Particles entering this device initiate an avalanche-like proliferation process of signal carriers to the required recording level. More recently, this principle has been used successfully to write single charge carriers in semiconductor avalanche-type photodiodes. However, this Geiger-Müller amplification principle does not distinguish signals within one or multiple input charge carriers (ie, does not provide high resolution for a number of charge carriers).

Shushakov et al. Describe and claim in US Pat. No. 6,885,827 a system and method for detecting an input signal by distributing the input signal to independent signal components that are independently amplified, thus providing a high propagation factor, low noise, and It enables specially fast response speed. The invention includes a number of steps. The signal is assigned to the individual channels of the multi-channel threshold amplifier, where each channel is assigned in such a way that it has only one elementary electrical charge. Each channel of the amplifier converts one electron at the input into a calibrated charge packet at the output. The summation of the output signals of each channel makes it possible to measure the value of only several electronic electrical signals, which are delivered to the input of a discrete amplifier with high accuracy. Calibrated amplification for one electron is provided in each channel of the discrete amplifier.

In addition to the threshold avalanche amplifier, each channel is equipped with an integrator that accumulates amplified charge signal packets. After receiving the required charge packet, the accumulator communicates with the quantifier via a governor, which turns off the channel. A regulator is used to adjust the potential of the quantifier and to drain the charge from the accumulator to return the channel to its initial state.

Thus, there is a need for further advances and improvements that make it possible to detect weak signals.

Accordingly, there is a need for an amplifying avalanche structure that is compatible with the systems and methods provided in USPN 6,885,827 by Shushakov et al., Which can further improve and improve the detection of weak signals.

It is an object of the present invention to provide an amplifying avalanche structure that is compatible with the systems and methods provided in USPN 6,885,827 by Shushakov et al., Which can further enhance and improve the detection of weak signals.

In accordance with the present invention, various embodiments are disclosed for an amplifying avalanche structure operating based on the principles described by Shushakov et al. The present invention includes transparent and non-transparent electrodes, avalanche regions, quantifiers, accumulators, regulators, and substrates, arranged to detect a weak signal consisting of only a few electrons. . Avalanche amplifying structures include a normal quantifier, reverse bias design; Normal quantifier, normal bias design; Lateral quantifier, normal bias design; Variable quantifier, normal bias, regulating electrode design; Normal quantifier, normal bias, adjustable electrode design; And lateral quantifier, normal bias, annular accumulator design. The amplifying structures are similarly arranged to form multi-channel devices.

According to various embodiments of the present invention, an amplifying avalanche structure operating in Geiger mode includes two electrodes, an avalanche region, an accumulator for accumulation of a single charge, and an avalanche process for turning on and off. A quantifier, a regulator for discharging charge from an accumulator composed of a semiconductor structure disposed on a planar substrate, the regulator and accumulator being sequentially disposed behind one of the electrodes, the avalanche region being an avalanche region. Adjacent the edge periphery of the accumulator region such that there is no electrical contact between the and the regulator, the quantifier is provided by an accumulator surface adjacent to the avalanche region. The regulator may be composed of the same semiconductor material as the avalanche region, but has less doped or wider bandgap. The substrate on the lower side of the amplifying avalanche structure may be a heavily doped layer, which has the same type of conductivity as the avalanche region and consists of the same semiconductor material as the avalanche region. The substrate may also be composed of the same conductivity type as the avalanche region material but less doped than the avalanche region material. On the bottom contact side, the substrate may have a highly doped contact layer of the same conductivity type as the avalanche region.

According to other embodiments of the invention, the contact to the avalanche region may be enabled through an electrode disposed on the back or bottom side of the substrate, or through an electrode disposed on the upper side of the substrate. Can be validated.

According to another embodiment of the invention, the entire upper surface of the amplifying avalanche structure may be covered with a dielectric layer except for the region in which the regulator is disposed.

According to another embodiment of the present invention, a dielectric layer is disposed on the top surfaces of the accumulator and avalanche regions, and the electrodes in contact with the regulator layer occupy the entire top surface of the avalanche structure. Or a regulator with an upper electrode is disposed along the surface of the avalanche structure.

According to another embodiment of the present invention, the upper electrode may be disposed along the entire surface of the avalanche structure, and the electrode may be transparent.

According to another embodiment of the present invention, the amplifying avalanche structure includes a signal transmission layer disposed along one side of the avalanche region, wherein the signal transmission layer is doped with the avalanche region and is composed of the same semiconductor material and conductivity type as the avalanche region. Or have a narrower bandgap than the avalanche region. The substrate and all layers may be composed of the same semiconductor material, for example Si, SiC, GaN, GaAs, and GaP.

According to another embodiment of the present invention, the amplifying avalanche structure may have an additional conductive contact region disposed between the accumulator and the regulator such that there is no direct electrical contact with the avalanche region. And the amplifying avalanche structure may have a barrier layer on the accumulator and the top surface of the avalanche region, which do not have electrical contact with the top electrode in contact with the regulator. A dielectric layer may be applied over the entire top surface of the blocking layer, and the top electrode in contact with the regulator may occupy the entire top surface of the avalanche structure. The blocking layer may be made of the same semiconductor material of the same conductivity type as the avalanche region and may be doped by the avalanche region. The barrier layer may be composed of a semiconductor material of opposite conductivity type and may be less doped than the avalanche region. The substrate and all layers may be composed of the same semiconductor material, for example Si, SiC, GaN, GaAs, and GaP.

According to another embodiment of the present invention, an avalanche amplifying structure disposed along a planar substrate and operating in Geiger mode is arranged on two electrodes, a regulator disposed between the substrate and the upper first electrode, a side periphery of the regulator. And an avalanche region disposed on the outer side periphery of the accumulator, wherein the quantifier is performed by an accumulator surface adjacent to the avalanche region. The substrate is made of a material having the same conductance type as the avalanche region, but with a higher resistance. The amplifying structure may comprise a dielectric layer disposed along the upper surfaces of the accumulator and avalanche regions, wherein the upper first electrode in contact with the regulator layer covers the entire upper surface of the avalanche structure. The amplifying structure on the upper surfaces of the accumulator and avalanche region may comprise a blocking layer composed of the same conductance type semiconductor material as the avalanche region but having a higher resistance. By means of the blocking electrode no electrical contact is allowed with the top electrode in contact with the regulator.

According to another embodiment of the present invention, an amplifying avalanche structure operating in Geiger mode includes two electrodes, an avalanche region, an accumulator for accumulation of a single charge, a quantifier for turning on and off an avalanche process, and an accumulator A regulator for discharging charge from the regulator, wherein the regulator and accumulator are sequentially disposed behind one of the electrodes, the avalanche region being the edge of the accumulator such that there is no electrical contact between the avalanche region and the regulator. Adjacent to the periphery, the quantifier includes a third electrode disposed on the dielectric layer provided by the accumulator surface adjacent to the avalanche region and in contact with the avalanche region. The substrate may be composed of the same conductivity type as the avalanche region material but less doped than the avalanche region material. In addition, a conductive contact region may be disposed between the accumulator and the regulator to avoid direct electrical contact with the avalanche region. And between the surfaces of the accumulator and avalanche regions, on one side, and on the other side, the dielectric layer, on the other side, a barrier layer of the same conductivity type semiconductor material as the avalanche region but having a lower doping impurity concentration may be disposed.

According to another embodiment of the present invention, an amplifying avalanche structure operating in Geiger mode comprises an avalanche region, an accumulator for the accumulation of a single charge, a quantifier for turning on and off an avalanche process, and discharging charge from the accumulator. A regulator for controlling the quantifier disposed on the strongly doped substrate between the two electrodes, wherein layers of avalanche regions composed of a material having the same conductivity type but of higher resistance are disposed thereon. The accumulator may be composed of a strongly doped semiconductor material with a conductivity of the type opposite to that of the substrate, the regulator of the high-impedance semiconductor material, and the quantifier provided at the interface between the avalanche region and the accumulator. The accumulator may have a low conductance in a direction parallel to the substrate plane. All layers (except regulators) of the substrate and the amplifying avalanche structure may be composed of the same semiconductor material. The regulator layer may be composed of the same material as the other layers and the material constituting the substrate, or may have a wider bandgap. The amplifying avalanche structure may comprise a single transport layer, which may generate free charge carriers and transfer the charges to the avalanche region. The substrate and all layers may be composed of the same semiconductor material, for example Si, SiC, GaN, GaAs, and GaP.

According to another embodiment of the present invention, an avalanche amplifying structure operating in Geiger mode includes a planar laminate semiconductor structure mounted on a substrate between two electrodes, the layer and accumulator of the avalanche region. The regulator layers are arranged in turn, capable of releasing charge from and controlling the quantifier. The function of the accumulator capable of accumulating signal charge and the quantifier's ability to turn on and off the avalanche process is performed at the interface between the avalanche region and the regulator. The interface between the avalanche region and the regulator may have a low conductance in a direction parallel to the substrate plane.

According to another embodiment of the present invention, an avalanche amplifying structure operating in Geiger mode may comprise a planar thin film semiconductor structure disposed between two electrodes on a strongly doped substrate, as opposed to a substrate. A regulator layer composed of high impedance semiconductor material is disposed successively on the substrate such that a layer of avalanche regions composed of semiconductors having a conductance of the type and a quantifier are provided at the interface between the substrate and the avalanche regions, and the accumulator is disposed between the avalanche regions and the regulator. Is provided in the interface.

According to another embodiment of the present invention, an avalanche amplifying structure operating in Geiger mode may comprise a planar thin film semiconductor structure disposed between two electrodes on a strongly doped substrate, wherein on the substrate: A regulator layer composed of a high-impedance semiconductor material, a conductance layer of the same type as the substrate material, and an accumulator layer composed of a strongly doped material and a type of conductance opposite to the substrate so that the quantifier is provided at the interface between the avalanche region and the accumulator. The layers of the avalanche regions composed of semiconductors having are arranged in succession. All layers and substrate may be composed of the same semiconductor material, or all layers (except regulators) may be composed of the same semiconductor material, and the regulator layer may be composed of a material having a wider band gap than other layers and substrates. It may be. A signal-transport layer can be disposed between the upper electrode and the avalanche region, which can generate free charge carriers and transfer the charges to the avalanche region. All layers except the signal-transport layer may be made of the same semiconductor material, whereas the signal-transport layer is made of a narrower band gap semiconductor material or a high-resistance semiconductor material having the same conductance type as the avalanche region. May be The substrate and all layers may be composed of the same semiconductor material, for example Si, SiC, GaN, GaAs, and GaP.

The disclosure to be described below describes various exemplary individual structures or single structures, which may be used in a standalone manner or integrated into matrices of discrete amplifiers. That is, in principle, each individual structure can be used as a self-contained functional device, which requires Geiger avalanche photodiode or Single photon avalanche diodes (SAPDs). Or an internal discrete amplifier. However, these individual structures are also well suited to integrate, and thus may provide a multi-channel internal discrete amplifier, or a multi-channel Geiger mode amplifier, or a multi-channel SAPD array.

After exemplary embodiments of basic, discrete amplifier structures have been disclosed, including exemplary claims corresponding to this structure and additional structures, multi-channel discrete based on the array of discrete device structures described above Various exemplary embodiments of amplifiers are described.

Those skilled in the art, including those disclosed by the exemplary claims, are described for the purposes of illustration and description of the present invention, and may restrict or limit the present invention. I will fully understand that I do not intend to limit them. Accordingly, the drawings illustrating various preferred embodiments of the present invention, together with the description and exemplary claims, serve to explain the principles of the invention. Furthermore, the exemplary claims are not intended to limit the scope of the invention as contemplated, contemplated, and intended by the inventor, and are provided to provide further understanding and specification of the technical spirit embraced by the invention. It became. In this regard, these exemplary claims are presented in conjunction with and with reference to the exemplary embodiments they embrace, and such juxtaposition and reference to the exemplary claims and figures is intended to limit the claims to the embodiments. It is not intended to be exhaustive or to limit the scope of the invention to the example claims listed herein.

Thus, it will be apparent to those skilled in the art that the embodiments described herein and the alternative embodiments and modifications are merely illustrative of the present invention, and the present invention is not limited thereto. For example, according to the non-limiting exemplary feature of the various embodiments, such devices may be completely homogeneous semiconductor devices based, for example, entirely on silicon. However, one of ordinary skill in the art will appreciate that such devices may be implemented with other materials, including compound semiconductors, and need not be homogeneous, but may include heterogeneous components. To illustrate in more detail, although single crystal silicon is used as the semiconductor material throughout the entire device in the exemplary embodiments described below, one of ordinary skill in the art would appreciate one or more of the discrete devices and / or arrays. It will be appreciated that other single crystal, polycrystalline, elemental, and / or compound semi-conductive materials may be used to implement the component (s), layer (s) or portion (s). Similarly, although the exemplary embodiments described below employ homo-juctions and hetero-junctions, metal-semiconductor junctions may be used to achieve the desired function. For example, the regulator may be implemented through a wider band gap material, while the signal transmission region has a lower band gap material than other layers. In addition, various insulating and conductive (eg, metal) materials may be applied which are different from those explicitly described herein, which are well understood by those skilled in the art.

Accordingly, the illustrative embodiments of the invention disclosed herein, as well as the various modifications and features thereof, provide a number of specificities, and these possible details are to be understood as limiting the scope of the invention. No. And those skilled in the art can have many modifications, applications, variations and equivalent implementations without departing from the scope of the present invention and without diminishing its attendant advantages. Will understand. In addition, it is to be noted that the terms and expressions used herein are used as the terminology of description rather than the term of limitation. The above terms or expressions are not used to exclude any equivalents of the features of the invention disclosed and described herein. Accordingly, the invention is not intended to be limited to the disclosed embodiments and should be defined in accordance with the claims, which will be provided in any application that is not a provisional application, claiming the benefit of this provisional application.

The present invention provides a number of advantages over the prior art. The present invention facilitates a highly sensitive device that is self-contained for recording and counting individual electrons and photons. The present invention is applicable to single channel and multi-channel devices. In particular, the present invention enables the fabrication of detectors with high amplification coefficients, low noise and fast response speeds. Additional aspects, features, and advantages of the present invention will be understood and will become more readily apparent when the present invention is considered in light of the detailed description taken in conjunction with the accompanying drawings.

1A-1C are schematic cross-sectional views of several exemplary embodiments of the present invention including an avalanche amplifying structure having a reverse-bias directional avalanche, including electrodes, avalanche regions, quantifiers, accumulators, The positional relationship of the regulator, the substrate and the optional signal transfer layer is shown.

FIG. 2A shows a series of material layers corresponding to the structure of FIG. 1A.

2B-2C show energy bands corresponding to the material layer structure shown in FIG. 2A during various operating conditions of the amplifier.

FIG. 2D illustrates the functional components of the avalanche amplifying structure shown in FIG. 1A.

3 is a cross-sectional view of an anti-bias avalanche amplifying structure having both a hole accumulator and an electron accumulator, in accordance with an embodiment of the invention.

4 is a diagram illustrating functional components of the avalanche amplifying structure shown in FIG. 3.

5 is a cross-sectional view of an inverse bias avalanche amplifying structure having holes, electron accumulators, and buried channels for holes, in accordance with an embodiment of the present invention.

6A-6B are cross-sectional views of two inverse bias avalanche amplifying structures, in accordance with an embodiment of the invention.

7A-7C are schematic cross-sectional views of several exemplary embodiments of the present invention including an avalanche amplifying structure having a normal direction avalanche, including electrodes, avalanche regions, quantifiers, accumulators, regulators, substrates. And the positional relationship of the optional signal transport layer.

FIG. 8A shows a series of material layers corresponding to the structure of FIG. 7A.

8B-8C show energy bands corresponding to the material layer structure shown in FIG. 8A during various operating conditions of the amplifier.

FIG. 9 illustrates a cross section of a normal direction avalanche amplifying structure having a ring guard region, in accordance with an embodiment of the invention.

10 is a cross-sectional view of a normal direction avalanche amplifying structure with a high field implant, in accordance with an embodiment of the present invention.

FIG. 11 illustrates a cross section of a normal direction avalanche amplifying structure with backside illumination, in accordance with an embodiment of the present invention. FIG.

12 is a cross-sectional view of a normal direction avalanche amplifying structure with a high field implant and hole accumulator, in accordance with an embodiment of the present invention.

FIG. 13 illustrates functional components of the normal direction avalanche amplifying structure shown in FIG. 12.

14 is a cross-sectional view of a normal avalanche amplifying structure having a ring guard and a hole accumulator, in accordance with an embodiment of the present invention.

15A-15O are schematic cross-sectional views of several exemplary embodiments of the present invention including an avalanche amplifying structure operating in Geiger mode and having a lateral avalanche, wherein electrodes, avalanche regions, quantifiers, accumulations Positional relationship between the device, the regulator, the substrate and the optional dielectric layer, the signal transmission layer, the blocking layer, the contact region, and the third electrode.

16 illustrates a cross-section of a lateral avalanche amplifying structure, in accordance with an embodiment of the present invention.

FIG. 17 illustrates functional components of the lateral avalanche amplifying structure shown in FIG. 16.

18 is a cross-sectional view of a lateral avalanche amplifying structure including InGaAsP according to an embodiment of the present invention.

19 is a cross-sectional view of a lateral avalanche amplifying structure having a pair of electrodes aligned along one side of the device, in accordance with an embodiment of the present invention.

20 is a cross-sectional view of a lateral avalanche amplifying structure having three electrodes, according to an embodiment of the present invention.

21 is a cross-sectional view of a lateral avalanche amplifying structure with one large electrode aligned along one side of the device, in accordance with an embodiment of the present invention.

FIG. 22 illustrates a cross section of a lateral avalanche amplifying structure with a blocking layer, in accordance with an embodiment of the present invention. FIG.

FIG. 23 is a cross-sectional view of a lateral avalanche amplifying structure having a buried channel and one large electrode along the upper side of the device, in accordance with an embodiment of the present invention.

24 is a cross-sectional view of a lateral avalanche amplifying structure having a buried channel and three electrodes, in accordance with an embodiment of the present invention.

25 is a cross-sectional view of a lateral avalanche amplifying structure with a hole accumulator and one large electrode along the upper side of the device, in accordance with an embodiment of the present invention.

FIG. 26 is a cross-sectional view of a lateral avalanche amplifying structure having a buried channel, a hole accumulator and three electrodes, in accordance with an embodiment of the present invention.

FIG. 27 is a cross-sectional view of a lateral avalanche amplifying structure having a hole accumulator and a pair of electrodes disposed opposingly around the device, in accordance with an embodiment of the present invention.

28A-28B are schematic cross-sectional views of two exemplary embodiments of the present invention, including an avalanche amplifying structure having a normal direction avalanche, a MIS-based drain, and three electrodes, with electrodes, avalanches, FIGS. The positional relationship between regions, quantifiers, accumulators, regulators, substrates and dielectric layers is shown.

FIG. 29 illustrates a cross-section of a lateral avalanche amplifying structure with a normal avalanche, a MIS-based drain, and three electrodes, in accordance with an embodiment of the present invention.

30A shows a series of material layers corresponding to the structure of FIG. 29.

30B-30C illustrate energy bands corresponding to the material layer structure shown in FIG. 30A during various operating conditions of the amplifier.

FIG. 30D illustrates functional components of the avalanche amplifying structure shown in FIG. 29.

FIG. 31 is a cross-sectional view of a lateral avalanche amplifying structure with a normal avalanche, a MIS-based drain and three electrodes, in accordance with an embodiment of the present invention.

FIG. 32A shows a series of material layers corresponding to the structure of FIG. 31.

32B-32C illustrate energy bands corresponding to the material layer structure shown in FIG. 32A during various operating conditions of the amplifier.

FIG. 32D shows functional components of the avalanche amplifying structure shown in FIG. 31.

33 is a schematic cross-sectional view of an exemplary embodiment of the present invention including an avalanche amplifying structure having a lateral avalanche and a hole accumulator, including electrodes, avalanche regions, quantifiers, accumulators, regulators, substrates, dielectric layers and The positional relationship of the signal transport layer is shown.

FIG. 34 is a cross-sectional view of an exemplary multichannel device configured with the lateral avalanche amplifying structure shown in FIG. 33.

35 is a cross-sectional view of the multi-channel device of FIG. 34 configured with the lateral avalanche amplifying structure shown in FIG. 33, in accordance with an embodiment of the present invention.

36 is a top view of the multi-channel device shown in FIG. 37 in accordance with an embodiment of the present invention.

37 is a top view of a multi-channel device with one electrode in accordance with one embodiment of the present invention.

38A-38B are cross-sectional views of a number of exemplary multi-channel devices, in accordance with multiple embodiments of the present invention.

This application is directed to U.S. Provisional Application (60 / 689,417) filed June 10, 2005, entitled "High Sensitivity, High Resolution detector Device and Arrays" and U.S. Provisional Application (60 / 691,931) filed June 17, 2005. And claims priority, the contents of these applications are incorporated herein by reference in their entirety.

Preferably, the reference numbers used herein correspond to those used in US Pat. No. 6,885,827 and US application (11 / 080,019) filed March 14, 2005, both of which are US patents and US applications. It is named "High Sensitivity, High Resolution Detection of Signals". Each of these has the same inventive entity as the present application, the applicant of which is the same as the applicant of the present application. In addition, these US patents and US applications are hereby incorporated by reference in their entirety.

The details below include single channel devices, which include (1) normal quantifier, reverse bias design, (2) normal quantifier, normal bias design, (3) side quantifier, normal bias design, and (4) Changeable quantifier, identified as a normal bias design. The designs described and claimed herein may be arranged in a wide variety of array configurations, which can provide endless array designs. Various embodiments of the invention have been shown with light 26 impinging on at least one electrode. Generally low doping means less than 10 ¹⁵ cm ^-3 , and strong doping or high doping means more than 10 ¹⁷ cm ^-3 . The device described herein may be manufactured through methods well understood in the art.

As a background of the present invention, the function of the regulator is provided by its higher impedance as compared to the avalanche layer. The high impedance can be obtained by the various methods described in US Pat. No. 6,885,827, which include low doping levels, materials with low mobility to carriers, or materials with artificially reduced mobility by special treatments. do. Potential barriers between the regulator layer and adjacent layers are also used to achieve the desired impedance. Barrier height is controlled by doping in the regulator and adjacent layers. If the adjacent layer is a metal, the barrier sound may be controlled by its work function.

The regulator functions to adjust or regulate the potential of the quantifier, which then transfers the potential to the electric field, thus switching the threshold amplifier on or off, and discharging the accumulated charge from the accumulator. This is to return the accumulator to its initial state.

The high imaginary part of the impedance (because of the inductance element that shifts the current phase relative to the voltage phase) provides the regulator's desired function, which provides very low conductivity during the short time that the signal carrier propagates. And therefore all the generated charges accumulate efficiently with little emissions. On the other hand, after a short time (delay), the conductance becomes high (equivalent to the real part of the impedance), allowing the accumulated charge to be discharged and quickly return to its initial state.

The high imaginary part of the impedance is provided by the properties of the material (low mobility of the carrier) or by the presence of a potential barrier between the regulator and the adjacent layer. The properties of the material cause the current to be delayed relative to the applied voltage. Low mobility may be achieved by ion implantation (and other special treatments) or may be a property of the material itself. The barrier prevents accumulated charge (eg electrons) from flowing from the accumulator to the regulator immediately, and on the other side of the regulator there is a second barrier to other types of carriers (eg holes).

Single channel device  Normal quantifier, reverse bias

1A, a single channel device is shown for one embodiment of an avalanche amplifying structure 1 operating in Geiger mode with a reverse bias supply voltage. In general, the avalanche amplifying structure 1 comprises a first electrode 2, an avalanche region 3, a quantifier 4, an accumulator 5, a regulator 6, a substrate 7 and a second electrode 8. It is a planar structure comprising a, they are arranged and in contact in the order described. The avalanche region 3 comprises a plurality of semiconductor layers having conductance opposite to the strongly doped substrate 7. The regulator 6 is a lightly doped semiconductor material, so that a quantifier 4 is provided at the interface between the accumulator 5 and the avalanche region 3. Similarly, an accumulator 5 is provided between the regulator 6 and the avalanche region 3.

Referring now to FIG. 1B, an alternative embodiment of a reverse bias avalanche amplifying structure 1 operating in Geiger mode is shown, which in order includes a first electrode 2, a regulator 6, and an accumulator 5. ), An avalanche region 3, a quantifier 4, a substrate 7 and a second electrode 8. The avalanche region 3 comprises a plurality of semiconductor layers having conductance opposite to the strongly doped substrate 7. A quantifier 4 is provided at the interface between the substrate 7 and the avalanche region 3. The accumulator 5 is provided at the interface between the regulator 6 and the avalanche region 3.

Referring now to FIG. 1C, another alternative embodiment of a reverse bias avalanche amplifying structure 1 operating in Geiger mode is shown, where the first electrode 2 and avalanche region 3 shown in FIG. 1A are shown. Is provided between the signal transmission layers 27. A quantifier 4 is provided at the interface between the accumulator 5 and the avalanche region 3.

Various materials are applicable to the avalanche region 3, the quantifier 4, the accumulator 5, the regulator 6, the substrate 7 and the signal transmission layer 27 shown in FIGS. 1A-1C. . For example, each layer may be composed of the same or different semiconductor materials, for example Si, SiC, GaN, GaAs, and GaP, which may be appropriately doped to provide the desired electrical properties. . In other embodiments of the invention, the regulator 6 may be composed of a material having a wider band gap than the other layers. In another embodiment of the present invention, the signal transmission layer 27 may be made of a material having a narrower band gap than other layers. In another embodiment of the present invention, the first electrode 2 and / or the second electrode 8 may be made of a conductive metal or may be made of a light transmissive and conductive material, for example transparent ITO and Al. It may include, but is not limited to, doped ZnO (Al-doped-ZnO). In addition, the avalanche region 3, the quantifier 4, the accumulator 5, the regulator 6, the substrate 7 and the signal transfer layer 27 include other undoped and doped semiconductor materials. It may comprise two or more layers arranged to form a thin film structure, with or without inclusions. The layers and devices may have planar and nonplanar shapes. Similarly, the cross-sectional views may represent a planar structure and / or a radially expanded structure. The SiO ₂ layer may be composed of other equivalent materials.

Referring now to FIG. 2A, a series of material layers is shown corresponding to one exemplary embodiment of the avalanche amplifying structure 1 shown in FIG. 1A. Such devices include a transparent electrode 105, a p-Si layer 100, an n ⁺ -Si layer 102, an i-Si layer 110, an n ⁺ -Si layer 109 and an electrode 106. . The electrode 106 is preferably metal and is electrically connected to a supply power supply having a positive voltage U _sup , and the transparent electrode 105 is electrically connected to ground.

Referring now to FIGS. 2B-2C, a band diagram is provided to illustrate the functionality of the device shown in FIG. 2A. FIG. 2B shows the initial state of the device, before the appearance of the signal carrier, where a positive voltage U _sup is applied to the electrode 106 and the n ⁺ -Si layer 109 has a potential of the electrode 106. Strongly doped n ⁺ -Si layer 102 is discharged and acts as a floated electrode to obtain approximately the same potential as n ⁺ -Si layer 109. In this example, almost all voltages are applied to the p-Si layer 100. The voltage must be sufficient so that the voltage drop U _amp in the p-Si layer 100 can exceed the avalanche breakdown value in the on state. In this example, p-Si layer 100 is an avalanche threshold amplifier or Geiger mode amplifier. Referring to FIG. 2B, the voltage U _amp applied to the amplifier is equivalent to U _sup -U _r , where U _r results from a small voltage drop in the i-Si layer 110. If u _r If is too high in the first place, this invar will decrease over time, which, related to the electrons go into n ⁺ -Si layer 109 from the n ⁺ -Si layer 102 beyond the potential barrier shown in Fig. 2B Due to discharge current or field-enhanced thermoemission. i-Si layer 110 may be comprised of an i-type, lightly doped p-type, or lightly doped n-type semiconductor material. Doping of i-Si layer 110 adjusts the potential barrier height between the regulator and adjacent layers. The n ⁺ -Si layer 102 corresponding to the accumulator of FIG. 1A discharges when there is no charge current from the p-Si layer 100, when the potential is almost equal to that of the electrode 106. To discharge.

Referring now to FIG. 2C, when free carriers (electrons) appear in the high-field region of the p-Si layer 100, this results in new electrons 62 caused by zone-zone impact ionization. And over breakdown avalanche proliferation, creating a pair of holes and holes 64. The avalanche electron current increases rapidly with time and becomes larger than the flow-out current from the n ⁺ -Si layer 102. And, the electrons 62 generated in the p-Si layer 100 quickly charge the accumulator or n ⁺ -Si layer 102. The action described above reduces the voltage drop in the amplifier or p-Si layer 100 and turns off the avalanche process, so that the amplifier is turned off.

The voltage drop in the amplifier is related to the voltage rise in the i-Si layer 110 or the regulator 6 and causes redistribution of the voltage supplied between the amplifier and the regulator 6. The regulator 6 induces a delay in the discharge of the accumulator 5, which shifts the current phase in time with respect to the avalanche current. This delay is sufficient to terminate the avalanche process in the amplifier.

Although not intended to be limited by theory, the discharge delay may have one or more physical causes depending on the design and characteristics of the regulator 6 as well as the state of the device. For example, when the voltage U _r is initially low, the heat dissipation or discharge current is smaller than the charging current to the avalanche or the accumulator 5. As U _r increases, the dominant cause is self-limitation of out-flow currents due to the space charge effect, free carrier through the time regulator 6 Finite time of these, the mobility of the carriers in the regulator 6 lower than the carriers in the amplifier, or other physical mechanisms, which limit the current discharge or change its phase relative to the avalanche current. Transition The minimum delay time sufficient to turn the amplifier off is estimated to be in the range of about 10-400 picoseconds, depending on the device design and the desired gain, so it accumulates in response to one signal carrier. It represents the number of elementary charges that accumulate in the group 5.

After the amplifier is turned off, the charge current to the accumulator 5 becomes zero, the accumulator 5 discharges through the regulator 6, and the amplifier returns to the on state again. . The device then returns to the initial state shown in FIG. 2B.

The result from the avalanche proliferation charge accumulated in the accumulator 5 is strongly doped n ⁺ -Si layer 102 and n ⁺ -divided by i-Si layer 110 (capacitive reader). It may be read through the mutual capacitance of the Si layer 109 or by detecting the accumulator 5 discharge current through the regulator 6 or the current reader. Both of these read approaches lead to the appearance of charge in the electrode 106, which corresponds to the charge accumulated in the accumulator 5.

Referring now to FIG. 2D, a functional configuration of a discrete amplifier is shown with respect to the corresponding physical representation of the device of FIG. 2A. The functional configuration comprises a transmitter 9, a threshold amplifier 10, a quantifier 11, an accumulator 12, a regulator 13 and a reader 14.

The transmitter 9 corresponds to a portion of the p-Si layer 100 where the electric field is not zero. Free electrons collide in the transmitter 9 and are delivered to the input of the threshold amplifier 10.

The critical amplifier 10 corresponds to a portion of the p-Si layer 100 where the electric field is sufficient to generate collision ionization in the on state. The voltage drop in the p-Si layer 100 exceeds the breakdown voltage, thus allowing the threshold amplifier 10 to operate in Geiger mode.

The quantifier 11 corresponds to the interface between the p-Si layer 100 and the n ⁺ -Si layer 102. The potential of the quantifier regulates the avalanche process (field strength) in the threshold amplifier 10. For planar quantifier 11, the transfer constant is equal to one. For non-planar designs, transfer constants of greater than 1 are possible based on the curvature of the design, and the curvature of this design causes electric field concentrations, resulting in higher maximum electric field for the same potential. The quantifier 11 functions to transfer the accumulator 12 potential to the field strength, which defines the avalanche strength. The transfer constant may be defined as the increase or response of the electric field strength to the increase in potential.

The accumulator 12 is shown in the n ⁺ -Si layer 102, which accumulates the current from the critical amplifier 10 and regulates the potential of the quantifier 11.

The regulator 13 is shown in the i-Si layer 100, which regulates the discharge current from the accumulator and delays the discharge, turning off the threshold amplifier, as well as amplifying the charge carriers. The device is then returned to its initial state.

The reader 14, which is a capacitive variant, has a capacitance comprising an n ⁺ -Si layer 102, an i-Si layer 110, and an n ⁺ -Si layer 109. . The charge accumulated in the accumulator 12 induces the appearance of an opposite sign of charge in the n ⁺ -Si layer 109 and the second electrode 106 electrically coupled thereto.

The band diagrams of FIGS. 2B-2C also show a p-Si layer 100 having an un-depleted region close to the first electrode 105. Typical p-Si layer 100 has a width of 5-6 μm and a resistance of 4 Ohm-cm. In alternative embodiments, the width of the p-Si layer 100 may be less than the width of the depletion region so that an electric field reaches the interface between the p-Si layer 100 and the first electrode 105. Photocarriers generated by light close to the interface allow for more efficient accumulation. In some embodiments, it is desirable to prevent electrons from being injected from the electrode 105 into the p-Si layer 100 when the electric field reaches the interface. The electrode 105 may have a Schottky barrier for electrons, or may have a p ⁺ region located between the electrode 105 and the p-Si layer 100.

From the above description, it can be seen that the present invention can operate as a Geiger counter using a new internal quenching scheme that is integrated into other devices, as well as both active and passive quenching as is known in the art. Active quenching requires external or integrated active electronic elements that are not provided by the functionality described above. Passive quenching requires a resistor or resistive layer that is not provided by the functions described above.

3, 5 and 6A-6B show specific embodiments of example devices. Referring to FIG. 3, there is shown a reverse bias avalanche amplifying structure 1 having both a hole accumulator and an electron accumulator, for an embodiment of the invention. Such devices include a transparent electrode 105, a segmented SiO ₂ layer 107 (insulator), p ⁺ -Si regions (and doped regions) 103, p-Si region 112, p-Si Layer 100, p ⁻ -Si layer 110, n ⁺ -Si layer 102, n ⁺ -Si layer 109, and electrode 106. The thickness of the p-Si layer 100 should be small enough so that it can be sufficiently depleted to increase the shortwave sensitivity. Preferred embodiments of the p-Si layer 100 include a doping of 2-3 Ω-cm and a thickness of 2.5-3. The spectral range for these devices is 300-400 nm (the shortest wavelength depends on the electrode 105 material), up to 700-800 nm. For longer wavelength spectral sensitivity up to 1060 nm, the width of the p-Si layer 100 increases and the doping level decreases.

One or more p ⁺ -Si regions 103 are included to prevent injection of electrons from the transparent electrode 105 into the depleted p-Si layer 100. If the p-Si layer 100 is not sufficiently depleted and the electric field does not reach the transparent electrode 105, p ⁺ -Si regions 103 are not necessarily necessary, but in general this is very short for wavelengths. By providing low spectral sensitivity, light carriers are generated near the top surface of the p-Si layer 100. If this region is not depleted, the optical carriers are recombined and lost. The resulting device is operable but not optimal. However, when the electric field reaches the transparent electrode 105 (more optimal strain), the p ⁺ -Si regions 103 are required to block the injection of electrons. In preferred embodiments, the p-Si layer 100 has a thickness of 2-4 μm and a resistivity of 10 Ω-cm.

The p-Si region 112 is preferably composed of the same material, has the same active impurity concentration, and has a lower mobility for holes in the lateral direction along the Si-SiO interface of the p-Si layer 100. Has The p-Si region 112 is formed by p with neutral impurity concentration, irradiation or n doping.

4 shows a functional configuration of the embodiment of FIG. Unlike the device of FIG. 2A, the device of FIG. 3 comprises two accumulators 12, 16 and two regulators 13, 17, thereby discharging corresponding accumulators 12, 16. By delaying, it functions as an electron regulator as described for the i-Si layer 110 of FIG. 2A and as a hole regulator corresponding to the p-Si region 112.

When the avalanche in the p-Si layer 100 is initiated by free carriers, holes 64 accumulate at the hole accumulator or interface in the p-Si region 112, thereby comparing p with the transparent electrode 105. Increase the dislocation of the top surface of the Si layer 100. This increase in potential is localized only over the n ⁺ -Si layer 102. The voltage drop U _amp in the p-Si layer 100 decreases until the accumulated positive charge flows into the p-Si region 103 and then to the transparent electrode 105. It can be readily seen that the hole regulator operates in the same manner as the p ⁻ -Si layer 110. The resulting delay time depends on the mobility of the holes moving along the interface of the p-Si region 112.

Referring back to FIG. 4, the transmitter 9, the critical amplifier 10 and the quantifier 11 regulate the avalanche process, which comprises the n ⁺ -Si region 102 and the p-Si layer 100. Transfers the potential of the charge electron accumulator 12 to the threshold amplifier 10 at an interface between The quantifier 17 delivers a hole accumulator potential to the threshold amplifier 10 at the interface between the SiO ₂ layer 107 and Si above the n ⁺ -Si region 102 and the electron accumulator 12 receives n ^+. -Si region 102 is disposed. The hole accumulator 16 is disposed at the interface between the SiO ₂ layer 107 and the Si region 112 above the n ⁺ -Si region 102. The electron regulator 13 delays the discharge of the electron accumulator 12 following the removal of the accumulated electron charge. The hole regulator 17 delays the discharge of the hole accumulator 17 following the removal of the accumulated hole charges corresponding to the p-Si region 112, the electron reader 14 and the hole reader 18.

When the electric field reaches the p-Si region 112 and the p-Si layer 100 and the p-Si region 112 are completely depleted, the functional configuration of FIG. 2D changes to the functional configuration of FIG. 4.

FIG. 5 shows an alternative embodiment of the device of FIG. 4 where p-Si region 112 is removed and replaced by buried channel 114 for holes, i-Si region 113 being transparent. It is added to separate the p ⁺ -Si region 103 from the electrode 105. The second regulator consists of a high impedance semiconductor material between the first or transparent electrode 105 and the p ⁺ -Si region 103 (and doped regions), and has a cavity or opening in the SiO ₂ layer 107. exist. A second accumulator is formed at the interface between the avalanche region and the second regulator. The buried channel 114 is preferably a thin layer of 0.3 μm, n-doped and manufactured by methods known in the art. The buried channel 114 improves the mobility of the holes along the interface of the channel. The doping concentration in the buried channel should be sufficient to allow sufficient depletion by the electric field in the p-Si layer 100.

The buried channel 114 ensures that all holes generated by the avalanche in the p-Si layer 100 move along the layer quickly and can accumulate in the p ⁺ -Si region 103 or the hole accumulator. As a result, by filling the p ⁺ -Si region 103, its potential with respect to the transparent electrode 105 is increased. p ⁺ -Si region 103 and i-Si region 113 operate in the same manner. The result is the voltage drop in the i-Si region 113, the delay of the discharge and the switching of the threshold amplifier to the OFF state. The hole quantifier in such a device is the interface between the buried channel 114 and the p-Si layer 100.

The filling of the p ⁺ -Si region 103 causes charge to accumulate in the buried channel 114 holes and uniformly increases the potential within the buried channel 114, thereby allowing the buried channel 114 to accumulate holes. To be included in the capacitance of the group.

6A-6B illustrate alternative embodiments for the device of FIG. 5. For example, in FIG. 6D, i-Si region 113 is removed from FIG. On the other hand, in Fig. 6B, the p ^-- Si layer 110 is removed. Likewise, the devices of FIGS. 6A-6B can be made without the buried channel 114.

Single channel device  -Typical quantifier, typical bias

Various materials can be applied to the layers and regions of FIGS. 7A-7B. For example, each layer may be composed of the same or other semiconductor materials, including for example Si, SiC, GaN, GaAs and GaP, which materials are doped to provide the desired electrical properties. In other embodiments, the regulator 6 is composed of a material having a wider bandgap than other layers. In still other embodiments, signal transmission layer 27 may be comprised of a material having a narrower bandgap than other layers. In still other embodiments, the first electrode 2 and / or the second electrode 8 may include, but are not limited to, for example, transparent ITO and Al-doped AnO; It may be composed of a conductive material or a conductive metal. In addition, the layers and regions may include two or more layers arranged to form a stacked structure with or without inclusions or regions with other undoped and doped semiconductor materials. . Layers and devices can include planar and nonplanar shapes. Likewise, the cross-sectional views represent structures of planar and / or diameter limits. The SiO ₂ layer may be composed of other equivalent materials.

Referring now to FIG. 7A, a single channel element for one embodiment of an avalanche amplifying structure 1 operating in Geiger mode in the vertical direction of an avalanche is shown. In general, the avalanche amplifying structure 1 includes a regulator 6 which discharges charge from the first electrode 2, an accumulator 5 and controls the quantifier 4, and an accumulator 5 that accumulates signal charges. A planar structure comprising a quantifier 4, an avalanche region 3, a substrate 7 and a second electrode 8, which turn on and off the avalanche process, which are arranged in the described structure. The quantifier 4 is formed at the interface between the accumulator 5 and the avalanche region 3. The accumulator 5 has a limited conductance in a direction parallel to the plane of the substrate 7. In some embodiments, all the layers can be composed of the same material. In other embodiments, the regulator layer is preferably made of a semiconductor material having a wider bandgap than the remaining semiconductor layers.

Referring to FIG. 7B, an avalanche amplifying structure operating in a Geiger mode having a vertical direction of an avalanche comprising a signal transmission layer 27 disposed between and contacting the substrate 7 and the avalanche region 3 of FIG. 7A ( Another alternative embodiment of a single channel element for 1) is shown. The signal transport layer 27 generates free charge carriers under the execution of the signal, causing them to be transferred into the avalanche region 3.

With reference to FIG. 7C, a Geiger is placed in a vertical avalanche including a first electrode 2, a regulator 6, an avalanche region 3, a substrate 7 and a second electrode 8 arranged in the order mentioned. An alternative embodiment of a single channel element operating in mode is shown for avalanche amplifying structure 1. The avalanche region 3 and the regulator 6 discharge the charge from the accumulator 5 and control the quantifier 4. The function of the accumulator 5 to accumulate the signal charge and the function of the quantifier 4 to turn on / off the avalanche process is performed at the interface between the avalanche region 3 and the regulator 6. The interface between the avalanche region 3 and the regulator 6 can limit the conductance in a direction parallel to the plane of the substrate 7.

Similarly, for an amplifying avalanche structure 1 operating in Geiger mode with a vertical avalanche, an avalanche region 3, an accumulator 5 for the accumulation of signal charges, and a quantifier 4 for turning on / off the avalanche process. And a quantifier 4 which discharges charge from the accumulator 5 and constitutes a planar laminate semiconductor structure disposed entirely on the substrate 7 heavily doped between the pair of electrodes 2, 8. It is possible to include a regulator 6 for controlling. The avalanche region 3 may be made of a material of higher resistance but of the same conductivity, the accumulator 5 may be made of a highly doped semiconductor material having conductivity opposite to the substrate 7, and the regulator 6 may be made of a high impedance semiconductor material, and a quantifier 4 may be provided at the interface between the avalanche region 3 and the accumulator 5.

Referring to FIG. 8A, a series of material layers are shown to include an electrode 106, a p-Si layer 100, an n + Si region 102, an i-Si layer 110, and a transparent electrode 105. have. 8B-8C show band diagrams illustrating functionality corresponding to the device layers of FIG. 8A.

Referring now to FIGS. 8B-8C, the device includes a silicon substrate having directionality [100] and resistivity of 10-100 Ω-cm and having a widely depleted region. The n ⁺ -Si region 102 is highly doped and has a width of less than 0.5 μm. The i-Si layer 110 has a width of less than several micrometers. The device is for infrared wavelengths, where absorption in the n ⁺ -Si region 102 and i-Si layer 110 can be ignored. An alternative embodiment of the present invention includes an i-Si layer 110 composed of a semiconductor (e.g., undoped ZnO) with a wider band gap than silicon, thereby reducing absorption and shortwave sensitivity (green -Blue) can be increased. Such embodiments have an epitaxial p-Si layer 100 having a resistivity of 1-10 Ω-cm.

The operation is almost identical to the pseudo reverse bias design. This is illustrated by the band diagram for the on / off state in FIGS. 8B-8C. The main difference is that electron and hole currents can help when discharging n ⁺ -Si layer 102 (accumulator) through i-Si layer 110 (regulator).

9-12 and 14 show particular embodiments of the device shown.

Referring now to FIG. 9, a cross-sectional view of a vertical avalanche amplifying structure 1 having a ring guard region is shown and a transparent electrode 105, a SiO ₂ layer 107, a p ⁺ -Si layer 90 (substrate ) And an electrode 106. The i-Si layer 110 (regulator) is smaller in dimension than the device, preferably has a radius of several micrometers and minimizes absorption. In some embodiments, i-Si layer 110 may be comprised of a semiconductor (eg, undoped ZnO) having a wider band gap than silicon. Signal light 26 enters epitaxial p-Si layer 100 (avalanche region) through n ⁺ -Si layer 102 (accumulator). In this way, n ⁺ -Si layer 102 is typically thinner than 0.4 μm to minimize absorption in the layer. The n ⁺ -Si guard ring 108 suppresses the edge effect and an avalanche process is provided over the area lying under the n ⁺ -Si layer 102 (accumulator). In bluegreen embodiments, epitaxial p-Si layer 100 has a resistivity of 1-2 Ω-cm and a width of a few μm to minimize thermogeneration currents in the depletion region. In infrared embodiments, epitaxial p-Si layer 100 has a wider width and higher resistance of tens of micrometers. The exact value of the width and resistance of the epitaxial p-Si layer 100 can be calculated by methods understood in the art to achieve desirable spectral sensitivity and other device parameters. The operation of the described device and its functional elements (accumulator, quantifier, regulator, substrate and avalanche region) are as described above.

Referring now to FIG. 10, a vertical avalanche amplifying structure 1 of a high field implant is shown, with a transparent electrode 105, a SiO ₂ layer 107, an i-Si layer 110, an n ⁺ -Si region ( 102), p-implant layer 101, epitaxial p-Si layer 100, p ⁺ -Si layer 90 (substrate) and electrode 106. In this embodiment, the high field implant is used to suppress the edge effect instead of the diffusion guard ring of FIG. This approach minimizes the unused area of the device without avalanches. The p implant layer 101 is a thin region outside of the n ⁺ -Si region 102. Avalanche amplification is located within the p implant layer 101. The i-Si layer 110 has a reflection of several μm to minimize absorption in the layer. In some embodiments, i silicon layer 110 may be comprised of a semiconductor (eg, ZnO) having a wider band gap than silicon. The infrared embodiments of the device can operate with backside illumination (rich-through), and the tail of the electric field is lightly doped epi to effectively collect light carriers at high time resolultion. Penetrates the p-silicon layer 100 and has a low operating voltage. i silicon layer 110 (regulator) has a small radius as described above with respect to FIG.

Referring now to FIG. 11, a vertical avalanche amplifying structure with backside illumination (richthrough) is shown to show electrode 106, SiO ₂ layer 107, isilicon layer 110, n ⁺ silicon layer ( 102, n ⁻ silicon guard ring 108, epitaxial p silicon layer 100, p-silicon layer 104, p ⁺ silicon layer 103, and transparent electrode 105. The operation of the device is as described above in FIG. 9 except that a transmitter-photoconverter is provided in the p-silicon layer 104. Again, the silicon layer 110 has a radius of several micrometers, thereby minimizing light absorption in the layer. In some embodiments, i silicon layer 110 may be composed of a semiconductor having a wider band gap than silicon (eg, undoped ZnO). The p-silicon layer 104 (substrate) has high resistivity (low doping) and is fully depleted at operating voltage. The described device can detect infrared light with a wavelength up to 1.06 μm.

Avalanche events occur in the p-silicon layer 100 with high doping compared to the transmission-light conversion included by the p-silicon layer 104. p and the width of the doped silicon layer 100 is selected such that the electric field, but the fall to zero, and has a long tail, which penetrate into the p ^_ silicon layer 104 is prevented by the p ⁺ silicon layer 103 doped highly. p ^_ width of the silicon layer (104) should be sufficient to provide structural strength to the device, preferably amount to hundreds ㎛. electric field intensity in the p ^_ silicon layer 104 may be sufficient for the avalanche one, enough to allow movement within it from the free carriers are saturated speed (104V / cm), as calculated in the way that is understood in the art Should be high.

The p ⁺ silicon layer 103 should be thin enough to minimize absorption in the layer. However, the p ⁺ silicon layer 103 should not be fully depleted and its width should be sufficient to block electron injection from the transparent electrode 105 to the p − silicon layer 104. Various antireflective coatings, as understood in the art, may also be added to the device through ways understood in the art.

Referring now to FIG. 12, a vertical avalanche amplifying structure 1 with a high field implant and a hole accumulator is shown and includes a transparent electrode 105, a SiO ₂ layer 107, an n ⁺ silicon layer 102, p a silicon layer 101, epitaxial p ^_ silicon layer (100) p ⁺ silicon layer 103, epitaxial i silicon layer (113) p ⁺ silicon layer 90 (substrate), and the electrode 106 It is explained to include. The device differs from FIG. 10 in that a hole accumulator is provided by the p ⁺ silicon layer 130 and an epitaxial i silicon layer 113 is added by the hole regulator instead of the electron accumulator. In addition, the i silicon layer 110 of FIG. 10 is removed so that the n ⁺ silicon layer 102 is directly connected to the transparent electrode to avoid accumulation of electrons.

Referring now to FIG. 13, the functional elements of the vertical avalanche amplifying structure 1 from FIG. 12 are shown and described. Transmitter 9 corresponds to the depletion portion of epitaxial p ⁻ silicon layer 100, threshold amplifier 10 corresponds to p silicon layer 101, and electron quantifier 11 corresponds to n ⁺ silicon layer 102. ) And the p ⁻ silicon layer 101, the electronic reader 14 corresponds to the transparent electrode 105, and the hole quantifier 15 includes the p ⁻ silicon layer 100 and the p ⁺ silicon layer ( 130 corresponds to an interface between the holes, the hole accumulator 16 corresponds to the p ⁺ silicon layer 130, the hole regulator 17 corresponds to the epitaxial i silicon layer 113, and the hole reader 18 Electrode 106 through capacitance consisting of p ⁺ silicon region 130, epitaxial i silicon layer 113 and p ⁺ silicon layer 90 (HF portion of the signal), and epitaxial i silicon layer 113 To correspond to the current directed to electrode 106 (LF portion of the signal). The operation of the hole accumulator and hole regulator is not different from that described above, with the opposite polarity and carrier type taken into account. The device switches the avalanche amplifier OFF, followed by removal of accumulated charge in the accumulator.

The width and doping level of epitaxial p- silicon layer 100 are designed such that the layer is fully depleted. The epitaxial i silicon layer 113 may be composed of a p-type or n-type material that adjusts the barrier height for holes. p ⁺ size of the silicon layer 130, the type and the n ⁺ distance timing, jitter, a maximum voltage of the p ⁺ silicon layer 130 from the silicon layer 102, the gain at the corrected voltage, and the effect on the other performance properties Adjust the affecting parameters.

The advantage of this embodiment is that there is no additional layers and no additional absorption in front of the avalanche region, unlike the conventional design of avalanche Geiger photodetectors or non-Geiger APDs. In addition, the quenching system is located behind the operating area while allowing use of Geiger photodetectors. As a result, there is an ability to operate with a DC voltage and a quenching system that is more effective than conventional passive and active quenching methods.

Referring now to FIG. 14, a vertical avalanche amplifying structure 1 with a ring guard and hole accumulator is shown, with a transparent electrode 105, a SiO ₂ layer 107, n ⁺ silicon layer 102, n ^- silicon guard ring 108, an epitaxial ^p-silicon layer (100) p ⁺ silicon regions 130, the epitaxial i silicon layer (113) p ⁺ silicon layer 90 (substrate) and the electrode (106) It is described, including. The device differs from FIG. 12 in that the high field implant design is replaced by a guard ring design.

Single channel Devices Horizontal quantifier, vertical bias

Various materials are applicable to the layers and regions of FIGS. 15A-15O. For example, each layer may be composed of the same or different semiconductor materials, including Si, SiC, GaN, GaAs, and GaP, doped to provide the desired electrical properties. In other embodiments, the regulator 6 may be composed of a material having a wider band gap than that of the other layers. In other embodiments, the signal transport layer 27 may be composed of a material having a narrower band gap than the other layers. In other embodiments, the first electrode 2 and / or the second electrode 8 may include, but are not limited to, transparent ITO and Al doped ZnO as a conductive metal or light transmitting and conductive material. It can be configured as. In addition, the layers and regions may include two or more layers arranged to form a laminate structure with or without other undoped and doped regions of the semiconductor material. Layers and devices can include planar and non-planar shapes. Similarly, cross sectional views may represent a planar and / or a completely different range of structures. The SiO ₂ layer may be composed of other similar materials.

Referring now to FIG. 15A, an avalanche amplifying structure 1 operating in Geiger mode with a horizontal avalanche is shown, in which the first electrode 2, the regulator 6, accumulate within the layers arranged in the order described. It is described including the group 5 and the avalanche region 3, the substrate 7, and the second electrode 8. It is preferable that the avalanche region 3, the substrate 7 and the second electrode 8 be in a relatively horizontal range. Similarly, it is desirable for the first electrode 2 and the regulator 6 to be in a slightly smaller range compared to the accumulator 5. The avalanche region 3 comprises holes through its thickness in the accumulator 5. The hole and accumulator 5 must be sufficiently larger than the regulator 6 to avoid direct contact between the regulator 6 and the avalanche region 3. The perimeter of the accumulator 5 is in direct contact with the avalanche region 3 such that the interface between the two materials functions as a ring shaped quantifier 4. The accumulator 5 is responsible for accumulating the signal charge. The quantifier 4 controls the on / off states of the avalanche process. The regulator 6 discharges the charge from the accumulator 5 and controls the quantifier 4.

15B-15O show a variant of the device of FIG. 15A.

In FIG. 1B, a dielectric layer 19 composed of one or more materials understood in the art surrounds the perimeter of the regulator 6. The dielectric layer 19 preferably covers and contacts both the accumulator 5 and the avalanche region 3 without providing electrical conduits between the regulator 6 and the avalanche region 3.

In FIG. 15C, the second electrode 8 is removed from the substrate 7 and replaced with a ring-shaped structure. The second electrode is now arranged with respect to the regulator 6 and the electrode 2 in contact with the avalanche region 3 and extending over the surface comprising the accumulator 5 and the avalanche region 3.

In FIG. 15D, the first electrode 2 in FIG. 15B now completely covers both the regulator 6 and the dielectric layer 19.

In FIG. 15E, the regulator 6 has a T-shaped structure to extend over the dielectric layer 19 and cover the top surface of the dielectric layer 19. The first electrode 2 is in contact with the T-type regulator 6 with respect to the accumulator 5.

In FIG. 15F, the first electrode 2 in FIG. 15E now extends to contact and cover the T-shaped adjuster 6 to have a horizontal width that is as wide as the second electrode 8.

In FIG. 15G, the substrate 7 and the second electrode 8 extend horizontally beyond the edge of the avalanche region 3. The signal transmission layer 27 is disposed around and in contact with the avalanche region 3. It is preferable that the signal transmission layer 27 have a thickness as large as the avalanche region 3. The signal transfer layer 27 is also composed of a semiconductor material comprising an avalanche region 3 (but of a less doped composition).

In FIG. 15H, an electrically conductive contact region 25 is disposed between the regulator 6 and the accumulator 5. The contact area 25 has a less horizontal area than the accumulator 5, in order to avoid direct electrical contact with the regulator 6. The blocking layer 24 is disposed in contact with the periphery of the contact area 25. Similarly, the blocking layer 24 covers the accumulator 5 and the avalanche region 3. The blocking layer 24 is made of the same type of semiconductor material as the avalanche region 3. The blocking region 24 does not contact the first electrode 2.

In FIG. 15I, dielectric layer 19 is disposed and contacts around the regulator 6 in FIG. 15H. The dielectric layer 19 also covers the blocking layer 24 completely in contact with the avalanche region 3. The first electrode 2 is only in contact with the regulator 6.

In FIG. 15J, the first electrode 2 of FIG. 15I is now horizontally extended to cover and contact both the regulator 6 and the blocking layer 24.

In FIG. 15K, the third electrode 50 replaces the segment of the first electrode 2 from FIG. 15D with a gap between them. The first electrode 2 is in contact with the regulator 6. The third electrode 50 is in contact with the dielectric layer 19.

In FIG. 15L, the third electrode 50 replaces the segment of the first electrode 2 from FIG. 15J with a gap between them. The first electrode 2 is in contact with the regulator 6. The third electrode 50 is in contact with the dielectric layer 19.

In FIG. 15M, the accumulator 5 includes holes with the regulator 6 to contact the accumulator 5 in the vicinity of the regulator 6. The regulator 6 is now on the substrate 7.

In FIG. 15N, the dielectric layer 19 is placed in contact with the perimeter of the regulator 6 from FIG. 15M extending beyond the accumulator 5. The second electrode 2 extends horizontally to contact and cover the regulator 6 and the dielectric layer 19.

In FIG. 15O, the first electrode 2 covers only the contact with the regulator 6 in FIG. 15N.

16 and 18-27 show particular embodiments of devices.

Referring now to FIG. 16, an avalanche amplifying structure 1 in the horizontal direction is shown and a transparent electrode 105, a p-silicon layer 110, a SiO ₂ layer 107, a p ⁻ silicon layer 100, n ⁺ Silicon region 102, p silicon region 103, p ⁺ silicon layer 91 (substrate), and electrode 106 are described. 17 shows the functional components of the horizontal avalanche amplifying structure 1.

Except for the electrodes 105 and 106, the components shown in FIG. 16 may be comprised of one or more semiconductor materials, for example silicon having a doping type and concentration to achieve desired electrical properties. SiO ₂ layer 107 may be composed of other similar materials.

The transparent electrode 105 and the p-silicon layer 110 preferably have a diameter of several μm to minimize absorption therein. The transparent electrode 105 and the p ⁻ silicon layer 110 may be formed of a semiconductor having a band gap wider than that of silicon in which undoped ZnO is an example. The n ⁺ silicon region 102 (accumulator) is fabricated to have the smallest diameter possible. Electrode 106 may be composed of a metal comprising, for example, Al, Ni, NiCr, Mo, or the like, or a transparent conductive material comprising, for example, ITO or Al doped ZnO.

The ON and OFF switches of this embodiment indicate that the critical amplifier 10 has a lateral orientation and that the critical amplifier 10, the quantifier 11, the accumulator 12, and the regulator 13 are not aligned in a straight line. Except for the same as the device in Figs. 8A to 8C.

It is desirable for the p-Si region 103 to have a higher doping concentration than the p ^-- Si layer 100. Avalanche proliferation occurs only at the edge of the junction in the p-Si region 103, and both the transmitters 9 and the critical amplifiers 10 in FIG. 16B are parallel to the p ⁺ -Si layer 91. , Oriented in the lateral direction. Thus, carriers generated on top of the p ⁻ -Si layer 100 are efficiently collected by the threshold amplifiers 10. Other elements in this functional configuration operate as described above.

It is preferred that the p-Si region 103 has a width, typically a width of 1 μm and a doping level, typically 1 Ω-cm resistivity, so that the lateral field component is in this region (rich-through in the lateral direction). ) And penetrate the p ^-- Si layer 100 along the Si-SiO ₂ interface, thus collecting signal carriers and transporting them to the p-Si region 103 (critical amplifier). In some embodiments, p-Si region 103 may be configured with the same doping as in p ^-- Si layer 100. However, the n ⁺ -Si layer 102 (accumulator) is preferably thin, typically smaller than 0.4 μm. The lateral direction of the avalanche is provided by the edge breakdown effect. In another embodiment, the p-Si region 103 may be used without rich-through and may have the same diameter as the device diameter, thus completely separating the SiO ₂ layer 107 from the p ⁻ -Si layer 100. Let's do it.

The side-directional device described herein provides high sensitivity for short wavelength applications up to at least near ultraviolet (UV) and high collection efficiency for long wavelength applications up to 700-800 nm. Thus, the geometrical factor for this device, representing amplified light carriers divided by the total number of collected light-carriers, is rather close to unity.

Referring now to FIG. 18, a side-directional avalanche amplifying structure 1 is shown and described, which is a pair of transparent electrodes 105, a Si ₃ N ₄ layer 93 (insulator), n ^- InP Layer 110, p ⁺ InP region 102, n InP layer 100, n InGaAsP layer 140 (buffer), n InGaAs layer 150 (absorber), n InP layer 160 (epitaxial) , And n ⁺ InP layer 90 (substrate, orientation [100]). These layers have the opposite doping type and polarity to the above embodiment.

InGaAsP's application does not affect the overall functional configuration of the device (regulator-accumulator-quantifier-amplifier). The required wavelength is defined by the absorbing layer band gap and width, with a range of 1.06-1.6 μm. The wide-band material (from which the amplifier and substrate are constructed) InP is transparent to this wavelength. By separating the amplifier from the absorber, the quantum efficiency is increased because neither the amplifier nor the substrate surrounds the absorber from light. The insulator or Si ₃ N ₄ layer 93 replaces the SiO ₂ layer 107 described above because it provides better performance matching with the InGaAs-InP layer. An additional buffer layer between the absorber and the n InP layer 100 improves their heterobarrier properties, in particular their frequency response. Transparent electrodes 105 may be composed of ITO or Al-doped ZnO. The device can be illuminated from any side and antireflective coating added via a method understood in the prior art.

P ⁺ InP region 102 operates as an accumulator so that its interface with neighboring n InP layers 100 functions as a quantifier. The n-InP layer 110 is responsible for the delay in accumulator discharge (sufficient to turn off the critical amplifier), and is responsible for returning the critical amplifier to the initial stage by removing accumulated charge therefrom. This is a regulator. The avalanche region or threshold amplifier corresponds to the n InP layer 100.

The width and doping concentration of the n InP layer 100, the n InGaAsP layer 104, and the n InGaAs layer 150 are prepared through methods understood in the prior art. The field strength is sufficient for avalanche proliferation in the n InP layer 100 and is sufficient to ensure that a sufficiently low electric field tail in the absorber prevents tunneling and avalanche current. The electric field tail can collect the optical carriers generated from the absorber to the amplifier so that the absorber is fully depleted. The absorber width is sufficient for effective light absorption at the required wavelength. In some embodiments, the absorber may be made without any electric field penetration from the n InP layer 100, but may allow the photocarriers to reach the depletion n InP layer 100 while requiring a tunneling current at the absorber. The band gap that is present changes.

Referring now to FIG. 19, a side-direction avalanche amplifying structure 1 having transparent electrodes 150 and electrodes 106 aligned along one side of the device is shown and described. This device is an alternative embodiment of the device in FIG. 16, where the ring electrode 106 now passes through the SiO ₂ layer 107, and the p ⁺ -Si region embedded in the p ⁻ -Si layer 100. Is attached to 104. Moreover, the electrode 106 in FIG. 16 is replaced with an SiO ₂ layer 107, as shown in FIG. 19. The electrodes 106 may be made of metal or a transparent conductive material. The p ⁺ -Si region 104 prevents the injection of electrons from the electrode 106 into the p ^-- Si layer 100. The doping depth for the p ⁺ -Si region 104 is small, typically 0.3 μm. The width of the p ⁺ -Si region 104 is minimized and preferably extends slightly beyond the edge of the electrode 106. The distance between n ⁺ -Si region 102 and p ⁺ -Si region 104 should be sufficient, so that the lateral components of the electric field from p-Si region 103 are small and the tunnel current in p ⁺ -Si region 104 Does not cause The function of this device is as described above with respect to FIG.

Referring now to FIG. 20, a side-directional avalanche amplifying structure 1 with three electrodes is shown and described. This device is an alternative embodiment of the device in FIG. 16, where a ring-shaped electrode 117 is disposed around the transparent electrode 105 and contacts the SiO ₂ layer 107. The electrode 117 is made of a transparent conductive material, an example of which has been provided above. Electrode 117 enables additional adjustment of device characteristics (including but not limited to response time, spectral sensitivity to other wavelengths), and compensates for the fixed charge in the protective oxide. DC voltage is applied to electrode 117 so that the device is optimized. The protective SiO ₂ layer 107 must be thick enough to prevent avalanche processes in the p or p ⁻ layer 100 and the p-Si layer 103 generated by the vertical component of the electric field from the electrode 117. And generally 0.7 탆. The function of this device is as described above with respect to FIG.

Referring now to FIG. 21, a side-direction avalanche amplifying structure 1 with a single electrode aligned along one side of the device is shown and described. This device is an alternative embodiment of the device in FIG. 16, wherein the transparent electrode 105 completely covers the top surface of the SiO ₂ layer 107. The main advantage of this embodiment is a larger volume of p ^- to -Si layer 100 is a depletion improve the response time of the collection device and of the optical carrier. The protective SiO ₂ layer 107 is sufficient to prevent avalanche processes in the p or p ⁻ -Si layer 100 and the p-Si layer 103 generated by the vertical component of the electric field from the electrode 105. It must be thick and generally is 0.7 μm. The function of this device is as described above with respect to FIG.

Referring now to FIG. 22, a side-directional avalanche amplifying structure 1 with a blocking layer is shown and described. This device is an alternative embodiment of the device in FIG. 16, where the blocking layer is an n-Si layer 120 disposed between the SiO ₂ layer 107 and the p or p ⁻ -Si layer 100. The n-Si layer 120 is preferably thin with a doping type opposite to the p or P ^- Si layer 100 and is typically 0.3 μm. The p or p ⁻ -Si layer 100 forms a buried channel under the Si—SiO ₂ interface to improve the transport of the optical carriers along the interface. The barrier layer is prepared through a method implemented in the prior art. The advantages of this device include improved stability because the avalanche process is moved away from the interface, thereby suppressing the injection of hot carriers into SiO ₂ . FIG. 23 shows an alternative embodiment for this design, wherein the transparent electrode 105 completely covers the p ⁻ -Si layer 110 and the SiO ₂ layer 107. FIG. 24 shows an alternative embodiment for this design, wherein the transparent electrode 105 is in individual contact with the p ⁻ Si layer 100 and the third electrode 117 is in isolation with the SiO ₂ layer 107. Contact with. The function of such a device is as described above with respect to FIG.

Referring now to FIG. 25, a lateral avalanche amplifying structure 1 having a hole accumulator and a single electrode along one side of the device is shown and described. Transparent layer 105 now fills the volume occupied by p ^-- Si layer 110 and i-Si layer 113 is p or p ^- Si layer 100 and p ⁺ -Si layer 91 ( The device is different from the device in FIG. 21 in that it is provided between the substrates). The width of the p-Si layer 103 is wider than in the previous embodiments.

Referring now to FIG. 26, a side-direction avalanche amplifying structure 1 having a blocking layer, a hole accumulator, and two electrodes along one side of the device is shown and described. This device is different from the device in FIG. 24 where the transparent electrode 105 now fills the volume occupied by the P ⁻ -Si layer 110 (electron accumulator) and the width of the p-Si layer 103 is Wider, and an i-Si layer 113 (hole accumulator) and a p ⁺ -Si layer 130 are disposed between the p-Si layer 100 and the p ⁺ -Si layer 91. In FIG. 27, the electrode 117 and the n-Si layer 120 shown in FIG. 26 are removed.

Single channel device  -Changeable quantifier, normal bias

Various materials are applicable to the layers and regions in FIGS. 28A-28B. For example, each layer can be composed of the same semiconductor material or different semiconductor materials, for example Si, SiC, GaN, GaAs and GaP, which are doped to provide the required electrical properties. . In other embodiments, the regulator 6 may be composed of a material having a wider band gap than other layers. In another embodiment, the single transport layer 27 may be composed of a material having a narrower band gap than the other layers. In another embodiment, the first electrode 2 and / or the second electrode 8 can be composed of a conductive material or a light transmissive and conductive material, for example, but not necessarily limited to transparent ITO and Al-. Doped ZnO. Moreover, the layers and regions may include two or more layers arranged to form a laminated structure with or without another non-doped semiconductor material and doped semiconductor material. The layers and devices may include a flat shape and a non-flat shape. Likewise, the cross-sectional view may represent a structure of flat expansion and / or diameter expansion. The SiO ₂ layer can be composed of other comparable materials.

Referring now to FIG. 28A, an MV-based, avalanche amplifying structure 1 having a vertical direction of an avalanche having a drain and two electrodes is shown and described, and a third electrode 50 in contact with the dielectric layer 19. ), The first electrode 2 in contact with the regulator 6, the avalanche region 3, the substrate in contact with both the avalanche region 3 and the regulator 6, and the substrate 7. And a second electrode 8 in contact. Dielectric layer 19 is in contact with both avalanche region 3 and regulator 6. The avalanche region 3 contacts the outer circumference of the side of the regulator 6. When an electrical potential is applied between the first electrode 2 and the second electrode 8 and when a Geiger (over breakdown) avalanche mode is created in the avalanche region 3, the quantifier 4 and the accumulator (5) is provided at the interface between the dielectric layer 19 and the avalanche region 3, and the third electrode 50 has an applied voltage, at which voltage the charge stored on the accumulator 5 It is discharged to the first electrode 2 through 6). FIG. 28B shows the device from FIG. 28A, where the accumulator 5 is provided at the interface between the dielectric layer 19 and the avalanche region 3 and the quantifier 4 is provided with the avalanche region 3 and the substrate. (7) is provided between.

29 and 31 relate to certain embodiments of example devices.

Referring now to FIG. 29, an avalanche amplifying structure 1 having a vertical direction of an avalanche, based on a MIS having a drain and electrodes, is shown and described. The device comprises a transparent electrode 105, an electrode 117, a SiO ₂ layer 107, an i-Si layer 110, a p-Si layer 100, a p ^- Si layer 104 (epitaxial), p ⁺ Si layer 120 (substrate), and electrode 106. The device operates in Geiger mode, but this is different from the previous examples described above.

Together with the SiO ₂ layer 107 and the electrode 105, the p-Si layer 100 with an exemplary resistivity of 1 Ω-cm acts as a fully depleted MIS structure, because minority carriers are p-Si layers This is because current is discharged from (100) along the Si-SiO ₂ interface to i-Si layer 110 and then to electrode 117. The voltage to the electrode 105 must be high enough to provide a Geiger mode avalanche in the p-Si layer 100. The voltage applied to electrode 117 must be sufficient to discharge current from p-Si layer 100 to i-Si layer 110, but is required for avalanche breakdown in i-Si layer 110. Should be smaller than Although p ^- Si layer 104 has a higher potential than p-Si layer 100, due to low doping, there is no avalanche in p ^- Si layer 104. The contact between the electrode 117 and the i-Si layer 110 is preferably non-injectable and thus includes a Schottky barrier to prevent the injection of electrons. In some embodiments, a thin n ⁺ layer may be provided along the top of i-Si layer 110 to prevent electron injection. The transparent electrode 105 may be made of ITO or ZNO having high conductivity. Electrodes 106 and 107 may be constructed of metal or a transparent conductive material. The oxide thickness in the SiO ₂ layer 107 should be small to provide an effective avalanche in the p-Si layer 100, typically 0.1 μm.

Referring now to FIGS. 30A-30C, FIG. 30A shows a sequence of material layers corresponding to the structure of FIG. 29, and FIGS. 30B-30C show the material layer structure shown in FIG. 30A during various operating conditions of the amplifier. The corresponding energy band diagram is shown. FIG. 30D schematically illustrates the functional components of the avalanche amplifying structure shown in FIG. 29.

In the initial stage, the electric field strength in the p-Si layer 100 is sufficient for impact ionization when a positive voltage is applied to the transparent electrode 105. The normal operating voltage must exceed the breakdown voltage, thus initiating Geiger mode.

During amplification, avalanche proliferation occurs near the Si-SiO ₂ interface in the p-Si layer 100, as shown in FIG. 28C, by free carriers or electrons 62. This process is self-sustaining due to avalanche proliferation, where the current filaments with current density increase exponentially with time. Filament electrons accumulate at the Si—SiO ₂ interface. The mobility of these electrons is not high, so they accumulate locally, so screen the electric field in the filament area and terminate the avalanche process. The Si-SiO ₂ interface acts as an HF accumulator with time constant, defined by the mobility of electrons spread along the interface.

After amplification, initial electrons 62 result in an adjusted charge package or first package as shown in FIG. 30D. The appearance of this package at the interface comes from oxide capacitance and corresponds to the charge package at electrode 105 (HF reader), where it can be detected.

After the end of the current filament, the resulting charge flows along the interface to the LF accumulator and the area where the current filament has occurred is restored to the initial stage. The interface lead, also the HF regulator, removes charge from the HF accumulator with a delay sufficient to turn off the threshold amplifier. The Si-SiO ₂ interface functions as a quantifier as defined by the electric field in the p-Si layer 100.

Each current filament occupies a rather small area, typically an area smaller than a few square microns. Thus, some filaments may exist simultaneously in the p-Si layer 100 to produce several charge packages. As such, if the p-Si layer 100 is large enough to compare with charge spots coming from the filaments, the device acts as a multi-channel photon counter.

Referring now to FIG. 31, MIS based with drain and electrodes. An amplifying structure 1 with the vertical direction of the avalanche is shown and described. In this embodiment, an n ⁺ -Si layer 120 is provided directly between the i-Si layer 110 and the p ^-- Si layer 104 as compared to FIG.

P-Si layer 100 and SiO ₂ layer 107 with an exemplary resistivity of 1 Ω-cm act as a fully depleted MIS structure because minority carriers are Si-SiO from p-Si layer 100. This is because the current is discharged to the p ⁺ -Si layer 120 along the _two interfaces. In the absence of avalanche proliferation in the p-Si layer 100, the current charging for the LF accumulator (p ⁺ -Si layer 120) may be negligible and the LF accumulator may be a LF regulator (i-Si layer 110). Discharge current (both holes 64 and electrons 62) is in the steady-state. The charge-discharge mechanism of the LF accumulator is the same as described for FIG. 9. The oxide thickness for the SiO ₂ layer 107 is small to provide an effective avalanche in the p-Si layer 100 and is generally 0.1 μm.

Referring now to FIGS. 32A-32C, FIG. 32A shows a sequence of material layers corresponding to the structure of FIG. 31, and FIGS. 32B-32C correspond to the material layer structure shown in FIG. 32A during various operating conditions of the amplifier. An energy band diagram is shown. FIG. 32D schematically illustrates the functional components of the avalanche amplifying structure shown in FIG. 31.

In the initial stage, the electric field strength in the p-Si layer 100 is sufficient for impact ionization when a positive voltage is applied to the transparent electrode 105. The normal operating voltage must exceed the breakdown voltage, thus initiating Geiger mode.

During amplification, avalanche proliferation occurs near the Si-SiO ₂ interface in the p-Si layer 100 as shown in FIG. 32C by free carriers or electrons 62. This process is self-sustaining due to avalanche proliferation, where the current filament with current density increases exponentially with time. Filament electrons accumulate at the Si—SiO ₂ interface. The mobility of these electrons is not high, so they accumulate locally, thus screening the electric field in the filament area and ending the avalanche process. The Si-SiO ₂ interface acts as an HF accumulator with time constant, defined by the mobility of electrons spread along the interface.

After amplification, the initial electrons result in an adjusted charge package or first package as shown in FIG. 32D. The appearance of this package at the interface comes from oxide capacitance and corresponds to the charge package at electrode 105 (HF reader), where it can be detected.

After the end of the current filament, the resulting charge flows along the interface to the n ⁺ -Si layer 102 (LF accumulator) and the area where the current filament has occurred is restored to the initial stage. The interface lead, also the HF regulator, removes charge from the HF accumulator with a delay sufficient to turn off the threshold amplifier. The Si-SiO ₂ interface functions as a quantifier as defined by the electric field in the p-Si layer 100.

Each current filament occupies a rather small area, typically an area smaller than a few square microns. Thus, some filaments may exist simultaneously in the p-Si layer 100 to produce several first charge packages. The capacity and discharge current of the LF accumulator must be sufficient so as not to change its state after collection of the first charge package. However, the integration-relaxation time of the LF accumulator is higher than that of the HF accumulator. The accumulation time is controlled by the voltage applied to the electrode 117. Some charge packages can be collected within the accumulation time and the electric field is reduced in the p-Si layer 100 because the charge is removed from it. Thus, the LF accumulator accumulates a second charge package, which is also shown in FIG. 32D and consists of a predetermined number of first packages.

As shown in FIG. 32D, several amplification channels may exist simultaneously in the p-Si layer 100 depending on the number of free carriers, each of which initiates a propagation process, where they collide. Three such processes or virtual channels are shown in FIG. 32D. Each virtual channel has the same set of functional elements: reader 9, threshold amplifier 10, quantifier 11, high frequency accumulator 12, HF regulator 13, and HF. A reader 14. All HF regulators in the virtual channels are connected to a single Low Frequency (LF) accumulator 21 that accumulates first packages, which occur after they are discharged through the HF regulators 13. This second stage of the individual amplifier functional configuration forms the second adjustment packages and includes the LF accumulator 21, the LF regulator 22, the LF reader 23, all shown in FIG. 32D.

Apparently, the described device makes it possible to detect several photon pulses as digital signals or adjusted signals on the electrode 117, while the ratios generated by thermal generation at the same electrode 117 Signal pulses are easily distinguished. The voltage regulation of the LF accumulation time at electrode 117 allows the device to detect the pulse length of light with PET applicability. Also, with photon counter applicability, it is possible to count single-photon events with high time resolution by reading the signal at electrode 105.

Multi-channel device

The single-channel avalanche amplification device described above can be integrated into a variety of multi-channel devices and can provide full functionality for the photodetector with individual amplification as described in US Pat. No. 6,885,827. The following examples represent exemplary arrays and are not to be used in a limiting sense. Accordingly, the present invention encompasses all avalanche amplification devices wherein the interface between two layers in a semiconductor laminate disposed between two or more electrodes is as a quantifier, as an accumulator, or as a quantifier and accumulator. The groups perform individually or in combination to perform their functions.

Referring now to FIG. 33, an avalanche amplifying structure 1 having a lateral direction of avalanche and a hole accumulator 1 is shown and described. The device comprises a first electrode 2, a contact layer 25, an avalanche region 3, a signal transfer layer 27, a dielectric layer 19, an accumulator 5, a regulator 6, a substrate 7. , And a second electrode 8.

Referring now to FIG. 34, the structure from FIG. 33 is shown aligned to form an array of three avalanche amplifying structures 1. For the purposes of the present invention, an array means two or more avalanche amplifying structures 1 arranged in a geometric pattern. The adjacent pair of avalanche amplifying structures 10 is preferably spaced apart by not less than 0.5 μm. The spacing between the accumulators 5 may be filled with a semiconductor material constituting the avalanche region, a lightly doped semiconductor material of the same conductivity type as the accumulator 5, or a dielectric material. It is preferred that the avalanche amplifying structures 1 are geometrically and dimensionally identical. The avalanche amplifying structures 1 may include various normal forms and arbitrary forms, and may include triangles, rectangles, squares, polygons, and circles. In some embodiments, a third electrode 50 may be added to this structure as described above. The first electrodes 2, the second electrodes 8, and the third electrodes 50, and the substrates 7 may be composed of individual single continuous sheets, and avalanche amplifying structures 1 The other layers in) are attached on these sheets. The first electrodes, the second electrodes, and the third electrodes may be composed of a transparent body. In other embodiments, dielectric layer 19, blocking layer 24, or conductive region 25 may be added to this structure to enhance performance of avalanche amplifying structure 1, as described above. have.

Referring now to FIG. 35, an illustrative diagram of a multi-channel device in FIG. 34 that includes a single channel element from FIG. 33 is shown and described. The device comprises transparent electrodes 105, n ⁺ -Si regions 102, p-Si layer 103, p ⁺ regions 130, p-Si layer 100, i-Si layer 113 ), a p ⁺ -Si layer 90, and an electrode 106. The device is fabricated on a doped silicon substrate and has a resistivity and orientation of 100 [Omega] -cm and a thickness of 350 [mu] m. The i-Si layer 113 is widthless and doped epitaxial silicon, so the distance between the p ⁺ -Si regions 130 and the P ⁺ -Si layer 90 is 2 μm. P ⁺ -Si regions 130 include p ⁺ type doping, are a first epitaxial layer, and are sized to be small in dimension. The second epitaxial layer or p-Si layer 100 has a width, so the distance between n ⁺ -Si regions 102 and p ⁺ -Si regions 130 is 5 μm. The p-Si layer 100 is doped p-type and its resistivity is 7-10 Ω-cm. The third p-doped epitaxial layer has a resistance of 1 Ω-cm and a width of 2 μm. The n ⁺ -Si layer 102 is made by diffusion using n-type impurities. The top surface is oxidized to a thickness of 0.5 μm, then ITO is deposited and etched (via lithography) to form the electrodes 105. The electrodes 105 have a diameter of 2 μm, all of which are connected to each other and to the metal contact plate by the transparent conductor 105. This metal electrode 106 is manufactured through a method understood in the prior art.

The channels can be packaged to form various patterns and shapes. The distance between the channels is typically 10-14 μm. This distance may be in the range of 8-30 μm, to optimize quantum efficiency at the required wavelength, timing resolution, and to minimize channel interaction or cross talk. The greater the distance, the lower the interaction. However, larger distances reduce quantum efficiency. The optimal distance therefore depends on the final use of the device.

36 shows an exemplary plan view of a multi-channel device, wherein seven transparent electrodes 105 are disposed around the device having a transparent cover 150. A pair of wires 152 from this device to the contact plate 151 are shown, which conveys a signal to the recording device. 37 shows a device with a single transparent lid 150.

Referring now to FIGS. 38A-38E, seven additional exemplary multi-channel devices are shown and described.

In FIG. 38A, the multi-channel device is composed of three avalanche amplifying structures 1 having the vertical direction of the avalanche, as provided above in FIG. 7A. The avalanche amplifying structures 1 comprise a first electrode 2, a regulator 6, an accumulator 5, a quantifier 4, an avalanche region 3, a substrate 7, and a second electrode 8. ) And these are sorted in the order described. The individual accumulators 5 and the quantifiers 4 are separated by a distance not smaller than 0.5 μm. The space between the accumulators 5 comprises a dielectric layer 19 which is preferably composed of a lightly doped semiconductor material, and the avalanche region 3 consists of it. The accumulators 5 and the quantifiers 4 are preferably equidistant from each other and have a distance not smaller than 0.5 μm. Moreover, accumulators 5 and quantifiers 4 may have the shape of a regular polygon, square, hexagon, or circle. The first electrodes 2 can be arranged over the entire operating area of the multi-channel device. The first electrode may be a mesh electrode in contact with the regulator 6 above all of the individual accumulators 5.

In FIG. 38B, as provided in FIG. 15D, the multi-channel device is composed of three avalanche amplifying structures having a lateral direction of the avalanche. Avalanche amplifying structures 1 include a first electrode 2, a regulator 6, an accumulator 5, a substrate 7, and a second electrode 8, which are arranged in the order described. . The accumulator 5 is disposed in the hole along the avalanche region 3, so that the contact between the two elements provides a ring-shaped quantifier 4. The first electrode 2, the second electrode 8, the accumulators 5, and the regulator 6 are separated from each other by a distance not smaller than 0.5 μm. The space between the accumulators 5 comprises a dielectric layer 19, which is preferably composed of a lightly doped semiconductor material, and the avalanche region 3 consists of this. The accumulators 5 and the quantifiers 4 are preferably spaced equidistant from each other and have a distance not smaller than 0.5 μm. The first electrodes 2 may comprise a solid electrode covering the entire operating area of this structure. It is likewise possible for the first electrodes 2 to consist of a mesh electrode providing electrical contact with the regulator 6 on the individual accumulators 5. The regulator 6 may be arranged exclusively under the mesh structure of the first electrode 2. The accumulators 5 may be spaced equidistant from each other and have a distance not smaller than 0.5 μm. The accumulators 5 and the quantifiers 4 may have the shape of a regular polygon, square, hexagon, or circle.

In FIG. 38C, as provided in FIG. 15C, the multi-channel device consists of three avalanche amplifying structures 1 having the lateral direction of the avalanche. The avalanche amplifying structures 1 comprise a first electrode 2, a regulator 6, an accumulator 5, an avalanche region 3, and a substrate 7, which are arranged in the order described. The second electrode 8 is a ring-shaped structure in contact with the avalanche region 3 in the opposite direction of the substrate 7. The quantifier 4 is arranged vertically between the accumulator 5 and the avalanche region 3, so that the contact region between the two elements provides a ring-shaped quantifier 4. The second electrode 8 is a mesh-type element, so there is no electrical contact with the regulator 6 and the accumulator 5. The avalanche regions 3 and the second electrodes 8 are covered with a dielectric layer 19 so that the first electrode 2 in electrical contact with the regulator 6 in each avalanche amplifying structure 1 There is no electrical contact with the second electrode 8, the avalanche region 3, and the accumulator 5.

In FIG. 38D, the multi-channel device is composed of three avalanche amplifying structures 1 having the lateral direction of the avalanche. Avalanche amplifying structures 1 include a first electrode 2, a regulator 6, an accumulator 5, a substrate 7, and a second electrode 8, which are arranged in the order described. . The quantifier 4 is arranged vertically between the accumulator 5 and the avalanche region 3 surrounding the accumulator 5, so that the contact area between the two elements provides a ring-shaped quantifier 4. do. A dielectric layer 19 is provided between the third electrode 50 and the avalanche region 3. A second dielectric layer 19 is also provided over the third electrode 50 and in contact with the regulators 6. The dielectric layers 9 electrically insulate the first electrode 2 and the third electrode 50 from the elements constituting this structure. The third electrode 50 does not contact the regulators 6. The accumulators 5 and the regulators 6 are equidistant from each other and the distance is not smaller than 0.5 μm.

 In FIG. 38E, the multi-channel device is composed of three avalanche amplifying structures 1 having the vertical direction of the avalanche, as provided in FIG. The avalanche amplifying structures 1 comprise a quantifier 4, an accumulator 5, disposed between the first electrode 2, the avalanche region 3, an interface between the avalanche region 3 and the accumulator 5. A regulator 6, a substrate 7 and a second electrode 8, which are arranged in the order described. The first electrode 2, the second electrode 8, the accumulators 5 and the regulator 6 are separated from each other by a distance not smaller than 0.5 μm. The space between the accumulators 5 comprises a dielectric layer 19, preferably composed of a lightly doped semiconductor material, the avalanche region 3 consisting of this. The accumulators 5 and the quantifiers 4 are preferably equidistant from each other and have a distance not smaller than 0.5 μm. The first electrodes 2 may comprise a solid electrode covering the entire operating area of this structure. It is likewise possible for the first electrodes 2 to consist of a mesh electrode that provides electrical contact with the regulator 6 over the individual accumulators 5. The regulator 6 can be arranged exclusively under the mesh structure of the first electrode 2. The accumulators 5 may be equidistant from each other and have a distance not smaller than 0.5 μm. The accumulators 5 and the quantifiers 4 may have the shape of a regular polygon, square, hexagon or circle.

From the foregoing description, it can be seen that the use of the present invention increases the flexibility very much. Although the invention has been described in great detail with reference to certain preferred embodiments, other embodiments are possible. Accordingly, the spirit and scope of the appended claims should not be limited to the description of the preferred embodiments contained herein.

As will be apparent from the foregoing, the described invention includes various intelligent amplifying avalanche structures that operate according to the principles described herein. The devices are applicable as self-contained high sensitivity instruments capable of recording and counting individual electrons and photons. The devices are also applicable in array configurations.

Accordingly, the described invention is expected to be used in chemical and biological chips with photodetectors, electronic amplifiers, chemical and biological sensors, and lab-on-a-chip applications. It is immediately applicable to devices that are important for mainland defense.

Claims (165)

An avalanche amplifying structure operating in Geiger mode, (a) a doped substrate; (b) (i) an avalanche region having conductance opposite to the substrate; (ii) an accumulator that accumulates a signal charge comprised of an over-doped material having the same conductance as the substrate, wherein the accumulator contacts the avalanche region along an interface that functions as a quantifier to control the avalanche process; (iii) a laminated semiconductor structure comprising a regulator layer that discharges the accumulator and controls the quantifier, contacts the accumulator layer opposite the avalanche region and contacts the substrate; (c) a first electrode through the avalanche region opposite the accumulator; And (d) an avalanche amplifying structure operating in a Geiger mode comprising a second electrode through said substrate opposite said regulator layer. The method of claim 1, The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a high impedance material. The method of claim 1, The regulator includes a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer and the first for transfer from the direction of the substrate to the regulator. An avalanche amplifying structure operating in a Geiger mode characterized by having a second energy barrier for a plurality of second carriers of a conductivity type opposite to carriers. The method of claim 1, The avalanche amplifying structure operating in a Geiger mode, characterized in that the regulator has a high impedance in the direction perpendicular to the regulator layer. The method of claim 1, The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a low doping material. The method of claim 1, And said substrate, said avalanche region, said accumulator layer and said regulator layer are comprised of the same semiconductor material. The method of claim 1, The substrate, the avalanche region and the accumulator layer are made of the same semiconductor material, and the regulator layer is made of a material having a wider bandgap than the avalanche region, the accumulator layer and the substrate. Avalanche amplification structure. The method of claim 1, (e) an avalanche amplifying structure operating in a geiger mode further comprising an insulator having at least one opening that allows the first electrode to contact the avalanche region. The method of claim 8, (f) further comprising an over-doped region having the same conductance as the avalanche region disposed in the avalanche region between the insulator and the avalanche region at each opening to prevent direct electrical contact between the avalanche region and the first electrode. An avalanche amplifying structure operating in Geiger mode comprising a. The method of claim 9, And made of a high impedance semiconductor material between the first electrode and the doped region and further comprising a second regulator present in the opening, wherein a second accumulator is formed at the interface between the avalanche region and the second regulator. An avalanche amplifying structure operating in Geiger mode, characterized in that the. The method of claim 9, (g) an avalanche amplifying structure operating in a Geiger mode, comprising a buried layer of semiconductor material having the same conductance as said substrate, said buried layer adjacent said doped regions. The method of claim 9, And further comprising a semiconductor layer having low mobility with respect to holes in the lateral direction, said semiconductor layer being comprised of a doping material having a conductance opposite to said substrate, said avalanche region adjacent said over-doped regions. An avalanche amplifying structure operating in Geiger mode, characterized in that disposed along. The method of claim 1, A low doped semiconductor material having a conductance similar to the avalanche region, disposed between and contacting the first electrode and the avalanche region, generating a plurality of free charge carriers, and generating the free charge carry The avalanche amplifying structure operating in Geiger mode, further comprising a signal transmission layer transmitting within the avalanche. The method of claim 13, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said transfer layer are made of the same semiconductor material. The method of claim 13, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said transfer layer are made of Si. The method of claim 13, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said transfer layer are made of SiC, GaN, GaAs or GaP. The method of claim 13, The substrate, the avalanche region, the accumulator layer and the regulator layer are made of the same semiconductor material, and the signal transmission layer is made of a material having a narrower bandgap than the substrate, the avalanche region, the accumulator layer and the regulator layer. An avalanche amplifying structure operating in Geiger mode, characterized in that. An avalanche amplifying structure operating in Geiger mode, (a) a doped substrate; (b) (i) a regulator layer; And (ii) opposite the regulator layer along a second interface having a conductance opposite to the substrate and contacting the regulator layer along a first interface serving as an accumulator and serving as a quantifier to regulate the avalanche process. A laminated semiconductor structure comprising an avalanche region in contact with the substrate, wherein the accumulator accumulates signal charges, the regulator discharges the accumulator and controls the quantifier; (c) a first electrode through said regulator layer opposite said avalanche region; And (d) an avalanche amplifying structure operating in a Geiger mode comprising a second electrode through said substrate opposite said substrate. The method of claim 18, The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a high impedance material. The method of claim 18, The regulator includes a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer and the first for transfer from the direction of the substrate to the regulator. An avalanche amplifying structure operating in a Geiger mode characterized by having a second energy barrier for a plurality of second carriers of a conductivity type opposite to carriers. An avalanche amplifying structure operating in Geiger mode, (a) a doped substrate; (b) (i) an avalanche region in contact with the substrate; (ii) accumulation of signal charge, an accumulation of contacting said avalanche region opposite said substrate along an interface consisting of an over-doped material having a conductance opposite to said substrate, and functioning as a quantifier to control an avalanche process tile; And (iii) a laminated semiconductor structure including a regulator layer that discharges the accumulator, controls the quantifier, and contacts the accumulator layer opposite the avalanche region; (c) a first electrode through said regulator layer opposite said accumulator; And (d) an avalanche amplifying structure operating in a Geiger mode comprising a second electrode through said substrate opposite said avalanche region. The method of claim 21, The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a high impedance material. The method of claim 21, The regulator is adapted for transfer from the direction of the first electrode to the regulator and a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer. An avalanche amplifying structure operating in a Geiger mode, having a second energy barrier for a plurality of second carriers of a conductivity type opposite to the first carriers. The method of claim 21, (e) further comprising an insulator layer disposed on a portion of the accumulator, wherein the regulator is disposed on a portion of the accumulator. The method of claim 24, (f) further comprising a guard ring in said avalanche region, made of a low doping material in contact with said insulator layer, having the same conductance type as said accumulator, and in electrical contact with said accumulator in its periphery; An avalanche amplifying structure operating in Geiger mode. The method of claim 24, (f) having the same conductance type as the avalanche region, between the avalanche region and the accumulator on one side and between the avalanche engagement and the substrate on the other side, so that the regulator is in electrical contact only with the accumulator And a doped semiconductor material, said avalanche region adjacent said accumulator layer to avoid contacting an edge along said accumulator. The method of claim 21, And said substrate, said avalanche region, said accumulator layer and said regulator layer are comprised of the same semiconductor material. The method of claim 21, The substrate, the avalanche region and the accumulator layer are made of the same semiconductor material, and the regulator layer is made of a material having a wider bandgap than the avalanche region, the accumulator layer and the substrate. Avalanche amplification structure. The method of claim 21, (e) a low doping semiconductor material having conductance similar to the avalanche region, disposed between and contacting the second electrode and the avalanche region, generating a plurality of free charge carriers, The avalanche amplifying structure operating in Geiger mode, further comprising a signal transmission layer for transmitting into the avalanche region. The method of claim 29, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said signal transmission layer are made of the same semiconductor material. The method of claim 29, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said transfer layer are made of Si. The method of claim 29, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said transfer layer are made of SiC, GaN, GaAs or GaP. The method of claim 29, The substrate, the avalanche region, the accumulator layer and the regulator layer are made of the same semiconductor material, and the signal transmission layer is made of a material having a narrower bandgap than the substrate, the avalanche region, the accumulator layer and the regulator layer. An avalanche amplifying structure operating in Geiger mode, characterized in that. The method of claim 29, An avalanche amplifying structure operating in a Geiger mode, wherein the accumulator layer has a limited conductance parallel to the plane of the substrate. An avalanche amplifying structure operating in Geiger mode, (a) a doped substrate; (b) (i) a regulator in contact with the substrate; (ii) an accumulator composed of an over-doped semiconductor material having the same conductance as the substrate, accumulating signal charge and contacting the regulator for discharging the charge from the accumulator; (iii) an avalanche region composed of a material having the same conductivity type as the substrate, the avalanche region in contact with the accumulator; And (iv) a laminated semiconductor structure comprising a doped semiconductor of opposite conductance and type opposite to the substrate and in contact with the avalanche region and including a quantifier to control the avalanche process, wherein the regulator discharges the accumulator Control the quantifier; (c) a first electrode through the quantifier; And (d) an avalanche amplifying structure operating in a Geiger mode comprising a second electrode passing through said substrate. 36. The method of claim 35 wherein The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a high impedance material. 36. The method of claim 35 wherein The regulator includes a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer and the first for transfer from the direction of the substrate to the regulator. An avalanche amplifying structure operating in a Geiger mode, having a second energy barrier for a plurality of second carriers of a conductivity type opposite to carriers. 36. The method of claim 35 wherein (e) an avalanche amplifying structure operating in a Geiger mode further comprising an insulator layer having at least one opening for electrical contact between the first electrode and the quantifier. The method of claim 38, (f) a guard ring in said avalanche region, made of a low doping material in contact with said insulator layer, having the same conductivity type as said quantifier, and in contact with said quantifier in its periphery; An avalanche amplifying structure operating in Geiger mode. The method of claim 38, (f) further comprising a semiconductor layer comprised of a low doping material having the same conductance type as the avalanche region, And the semiconductor layer is disposed between the avalanche region and the quantifier on one side and between the avalanche region and the accumulator on the other side. An avalanche amplifying structure operating in Geiger mode, (a) an over-doped substrate having the same conductivity type as the substrate; (b) (i) a regulator; (ii) an accumulator composed of an over-doped semiconductor material having the same conductivity type as the substrate, wherein the accumulator accumulates signal charge, wherein the accumulator contacts the regulator for discharging the charge from itself, To control; (iii) an avalanche region composed of a material having the same conductivity type as the substrate, the avalanche region in contact with the accumulator; And (iv) a laminated semiconductor structure composed of an over-doped semiconductor of opposite conductance and type opposite the substrate, disposed in the avalanche region, and comprising a quantifier for controlling the avalanche process; (c) a first electrode through the quantifier; And (d) an avalanche amplifying structure operating in a Geiger mode comprising a second electrode passing through said substrate. 42. The method of claim 41 wherein The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a high impedance material. 42. The method of claim 41 wherein The regulator includes a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer and the first for transfer from the direction of the substrate to the regulator. An avalanche amplifying structure operating in a Geiger mode characterized by having a second energy barrier for a plurality of second carriers of a conductivity type opposite to carriers. An avalanche amplifying structure operating in Geiger mode, (a) a doped substrate; (i) an avalanche region contacting said substrate; And (ii) a laminated semiconductor structure comprising a control layer in contact with the avalanche region opposite the substrate along an interface that functions as a quantifier to control the avalanche process and as an accumulator to accumulate signal charge, wherein The avalanche region and the control layer discharge the accumulator and control the quantifier; (c) a first electrode through the regulator opposite the avalanche region; And (d) an avalanche amplifying structure operating in a Geiger mode comprising a second electrode through said substrate opposite said avalanche region. The method of claim 44, The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a high impedance material. The method of claim 44, The regulator is adapted for transfer from the direction of the first electrode to the regulator and a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer. An avalanche amplifying structure operating in a Geiger mode, having a second energy barrier for a plurality of second carriers of a conductivity type opposite to the first carriers. The method of claim 44, And said interface has a limited conductance parallel to the plane of said substrate. An avalanche amplifying structure operating in Geiger mode, (a) a substrate; (b) (i) an avalanche region; And (ii) an accumulator layer in contact with the avalanche region along a ring-shaped interface that accumulates signal charge, resides in a cavity within the avalanche region, and functions as a quantifier to regulate the avalanche process, wherein the avalanche region And the accumulator layer is in contact with the substrate; And (iii) a laminated semiconductor structure that discharges the accumulator, controls the quantifier, and includes a control layer in contact with the accumulator layer opposite the substrate; (c) a first electrode through said regulator layer opposite said accumulator layer; And (d) an avalanche amplifying structure operating in a Geiger mode comprising a second electrode through said accumulator layer and said substrate opposite said avalanche region. 49. The method of claim 48 wherein The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a high impedance material. 49. The method of claim 48 wherein The regulator is adapted for transfer from the direction of the first electrode to the regulator and a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer. An avalanche amplifying structure operating in a Geiger mode, having a second energy barrier for a plurality of second carriers of opposite conductivity type to the first carriers. 49. The method of claim 48 wherein The avalanche amplifying structure operating in a Geiger mode, wherein the substrate is a doped semiconductor material. 49. The method of claim 48 wherein The avalanche amplifying structure operating in Geiger mode, wherein the substrate and the avalanche region are made of the same semiconductor material. 49. The method of claim 48 wherein Wherein said substrate and said avalanche region are comprised of a semiconductor material having the same type of conductivity and said substrate is less doped than said avalanche region. The method of claim 53 wherein The avalanche region is avalanche amplifying structure operating in the Geiger mode, characterized in that made by the second electrode. The method of claim 53 wherein The avalanche region is avalanche amplifying structure operating in the Geiger mode, characterized in that made by the first electrode. 49. The method of claim 48 wherein (e) a dielectric layer disposed around the regulator layer, the dielectric layer in contact with the periphery of the regulator layer, wherein the dielectric layer contacts the accumulator layer and the avalanche region. rescue. The method of claim 56, wherein And the first electrode is in contact with the dielectric layer. The method of claim 56, wherein And the first electrode is in contact with the dielectric layer and the control layer separately. The method of claim 56, wherein And the control layer is in contact with the dielectric layer opposite the avalanche region and the accumulator layer, and the first electrode is also in contact with the control layer opposite the dielectric layer. 49. The method of claim 48 wherein And said governor layer and said avalanche region are comprised of the same semiconductor material and said regulator layer is less doped than said avalanche region. 49. The method of claim 48 wherein And the regulator layer is comprised of a semiconductor material having a bandgap wider than the avalanche region. 49. The method of claim 48 wherein (e) a signal having the same conductivity type as the avalanche region and consisting of a less doped semiconductor material, generating a plurality of free charge carriers in response to a signal, and transmitting the free charge carriers to the avalanche region And a transfer layer, wherein the substrate and the second electrode extend beyond the avalanche region, the signal transfer layer contacts the avalanche region at its periphery and contacts the substrate opposite the first electrode. An avalanche amplifying structure operating in Geiger mode, characterized in that. 63. The method of claim 62, The avalanche amplifying structure operating in Geiger mode, wherein the signal transmission layer and the avalanche region are made of the same semiconductor material. 63. The method of claim 62, The avalanche amplifying structure operating in a Geiger mode, wherein the signal transmission layer and the substrate are made of the same semiconductor material having the same conductivity type and doping concentration. 63. The method of claim 62, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said signal transmission layer are comprised of the same semiconductor material. 63. The method of claim 62, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said signal transmission layer are made of Si. 63. The method of claim 62, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said signal transmission layer are made of SiC, GaN, GaAs or GaP. 63. The method of claim 62, The avalanche amplifying structure operating in a Geiger mode, wherein the signal transmission layer is made of a semiconductor material having a narrower bandgap than the avalanche region. 49. The method of claim 48 wherein (e) a contact region electrically conductive and disposed between the regulator layer and the accumulator layer; And (f) a semiconductor material having a conductivity of the same type as the avalanche region, further comprising a blocking layer contacting the contact region at its periphery and contacting the accumulator layer and the avalanche region opposite the substrate; An avalanche amplifying structure operating in Geiger mode, characterized in that. The method of claim 69, The avalanche amplifying structure operating in a Geiger mode, wherein the substrate, the avalanche region, the accumulator layer, the regulator layer and the blocking layer are made of the same semiconductor material. The method of claim 69, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said blocking layer are made of Si. The method of claim 69, And said substrate, said avalanche region, said accumulator layer, said regulator layer and said blocking layer are made of SiC, GaN, GaAs or GaP. The method of claim 69, and (e) a dielectric layer disposed around the regulator layer, the dielectric layer in contact with the periphery of the regulator layer, wherein the dielectric layer contacts the blocking layer. The method of claim 73, wherein And said first electrode also covers and contacts said dielectric layer. The method of claim 73, wherein (h) an avalanche amplifying structure operating in a Geiger mode further comprising a third electrode in contact with said dielectric layer. The method of claim 69, Wherein said blocking layer and said avalanche region are comprised of a semiconductor material of the same conductivity type, said blocking layer and said avalanche region having the same doping concentration. The method of claim 69, Wherein said blocking layer and said avalanche region are comprised of a semiconductor material of the same conductivity type, said blocking layer having a lower doping concentration than said avalanche region. The method of claim 69, Wherein said blocking layer and said avalanche region are comprised of a semiconductor material of opposite conductivity type, said blocking layer having a lower doping concentration than said avalanche region. An avalanche amplifying structure operating in Geiger mode, (a) a substrate; (b) (i) an avalanche region; And (ii) an accumulator layer in contact with the avalanche region along a ring-shaped interface that accumulates signal charge and resides in a cavity within the avalanche region and functions as a quantifier to regulate avalanche processes, wherein the avalanche region and The accumulator layer is in contact with the substrate; And (iii) a laminated semiconductor structure that discharges the accumulator, controls the quantifier, and includes a control layer in contact with the accumulator layer opposite the substrate; (c) a first electrode through said regulator layer opposite said accumulator layer; And (d) an avalanche amplifying structure operating in a Geiger mode comprising a second electrode through the avalanche region opposite the substrate. 80. The method of claim 79 wherein The avalanche amplifying structure operating in Geiger mode, characterized in that the regulator is made of a high impedance material. 80. The method of claim 79 wherein The regulator is adapted for transfer from the direction of the first electrode to the regulator and a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer. An avalanche amplifying structure operating in a Geiger mode, having a second energy barrier for a plurality of second carriers of a conductivity type opposite to the first carriers. (a) a substrate; (b) (i) an avalanche region having the same conductance and high concentration doping as the substrate, (ii) an accumulator layer located in the cavity within the avalanche region and contacting the avalanche region along a ring-shaped interface acting as a quantifier for controlling the avalanche process, the accumulator accumulating signal charge; And (iii) a laminated semiconductor structure located in a cavity in the avalanche region and in contact with the accumulator along a ring-shaped interface, the regulator discharging the accumulator and controlling the quantifier; (c) a first electrode connected through said regulator layer opposite said substrate; And (d) avalanche amplifying structure driving in a Geiger mode comprising a second electrode extending through the substrate opposite the avalanche region, the accumulator layer and the substrate in contact with the substrate. 83. The method of claim 82, The avalanche amplifying structure, characterized in that the regulator is made of a high impedance material. 83. The method of claim 82, The regulator is adapted for transfer from the accumulator direction to the regulator layer for a first energy barrier for a plurality of first carriers accumulated in the accumulator layer and for transfer from the first electrode direction to the regulator layer. And a second energy barrier for a plurality of second carriers of a conductivity type opposite to the first carriers. 83. The method of claim 82, And further comprising a dielectric layer in contact with and disposed over the perimeter of the regulator layer extending around the accumulator layer, wherein the dielectric layer is also in contact with the accumulator layer and the avalanche layer opposite the substrate, and the first electrode also provides the An avalanche amplifying structure, said dielectric layer being in contact with and covering said dielectric layer. 83. The method of claim 82, And further comprising a barrier layer in contact with and disposed around the regulator layer extending near the accumulator layer, the barrier layer also in contact with the accumulator layer and the avalanche layer opposite the substrate, the barrier layer being the avalanche. An avalanche amplifying structure comprising a semiconductor material having conductance and low concentration doping of the same type as a region. (a) a substrate; (b) (i) an avalanche region and (ii) a regulator layer located in a cavity within said avalanche region and contacting said avalanche region along a ring-shaped interface, said avalanche region and said regulator being in contact with said substrate. A laminated semiconductor structure comprising; (c) a dielectric region in contact with the avalanche region and the regulator layer opposite the substrate—the interface between the avalanche region and the dielectric layer functions as a quantifier and an accumulator, the accumulator accumulates a single charge and the quantifier Control an avalanche process, the regulator discharging the accumulator and controlling the quantifier; (d) a first electrode located in the cavity in the dielectric layer and extending through the regulator layer opposite the substrate; (e) a second electrode extending through said substrate opposite said avalanche region and said regulator layer, said first electrode and said second electrode creating a Geiger avalanche mode in said avalanche region when electrically charged; And (f) a third electrode leading through said dielectric layer opposite said avalanche region, said third electrode discharging said accumulator through said regulator layer to said first electrode when said third electrode is electrically charged; Avalanche amplification structure driven in Geiger mode. 88. The method of claim 87 wherein The avalanche amplifying structure, characterized in that the regulator is made of a high impedance material. 88. The method of claim 87 wherein The regulator is adapted for transfer from the accumulator direction to the regulator layer for a first energy barrier for a plurality of first carriers accumulated in the accumulator layer and for transfer from the first electrode direction to the regulator layer. And a second energy barrier for a plurality of second carriers of a conductivity type opposite to the first carriers. 88. The method of claim 87 wherein The substrate is a heavily doped semiconductor, and the quantifier is provided between the avalanche region of the substrate and a semiconductor having conductivity opposite to the substrate. (a) three electrodes; (b) an avalanche region made of a material having the same conductivity type as the substrate; (c) an accumulator for accumulating signal charges; (d) a quantifier for controlling the avalanche process; (e) a regulator for discharging the accumulator and controlling the quantifier—the avalanche region, the accumulator, the quantifier and the regulator comprise a laminated semiconductor structure disposed on a heavily doped substrate, wherein the one An electrode contacts the substrate opposite the laminated semiconductor structure; (f) an intermediate layer of a lightly doped semiconductor material of the same conductance type as said substrate, said intermediate layer being in contact with said avalanche region and said second electrode; And, (g) a dielectric layer in contact with the avalanche region and the second electrode—the accumulator and the quantifier capabilities are performed along an interface between the avalanche region and the dielectric layer, wherein an electrical potential between the first and second electrodes is An avalanche amplifying structure driving in a Geiger mode comprising a Geiger avalanche mode within the avalanche region, wherein the second electrode discharges charge in the accumulator when a voltage is applied thereto. 92. The method of claim 91 wherein The avalanche amplifying structure, characterized in that the regulator is made of a high impedance material. 92. The method of claim 91 wherein The regulator includes a first energy barrier for a plurality of first carriers accumulated in the accumulator layer for transfer from the accumulator direction to the regulator layer and for transfer from the electrode direction to the regulator. An avalanche amplifying structure having a second energy barrier for a plurality of second carriers of opposite conductivity type with one carrier. 92. The method of claim 91 wherein (h) an avalanche amplifying structure further comprising a contact region made of a heavily doped material having conductance opposite to the substrate between the intermediate layer opposite the substrate and the second electrode. 92. The method of claim 91 wherein (h) an avalanche amplifying structure further comprising a second regulator disposed between the intermediate layer and the second electrode and made of a high conductance semiconductor material. (a) a substrate consisting of doped InP; (b) (i) an insulating layer; (ii) a regulator consisting of doped InP in contact with the insulating layer; (iii) an accumulator consisting of doped InP in contact with the regulator, the accumulator accumulating signal charge; (iv) a quantifier layer comprised of doped InP in contact with the accumulator, the quantifier controlling the avalanche process, the regulator discharging the accumulator and controlling the quantifier; (v) a buffer layer of doped InGaAsP in contact with the quantifier; (vi) an absorber consisting of doped InGaAs; And, (vii) a laminated semiconductor structure comprising an epitaxial layer of InP, wherein the substrate is in contact with the epitaxial layer; (c) a first electrode running through said insulating layer opposite said regulator; And, (d) an avalanche amplifying structure comprising a second electrode running through said substrate opposite said epitaxial layer. 97. The method of claim 96, The avalanche amplifying structure, characterized in that the substrate has a [100] direction. 97. The method of claim 96, The avalanche amplifying structure, wherein the insulator is Si ₃ N ₄ . And at least two avalanche amplifying structures disposed and arranged respectively to form an array, each avalanche amplifying structure comprising at least two electrodes disposed near an avalanche region layer, an accumulator layer, a regulator layer, and a substrate layer. Wherein the two layers are contacted along a first interface that functions as a quantifier, the quantifier controls the avalanche process, the accumulator accumulates signal charge, the regulator discharges the accumulator and Multi-channel structure, characterized in that for controlling. The method of claim 99, wherein Adjacent pairs of avalanche amplifying structures separated at least 0.5 μm apart. The method of claim 99, wherein Wherein said spacing between said accumulators is filled with a semiconductor material constituting said avalanche region. The method of claim 99, wherein Wherein said spacing between said accumulators is filled with a lightly doped semiconductor material having the same conductivity type as said accumulators. The method of claim 99, wherein Wherein said spacing between said accumulators is filled with a dielectric material separating said accumulators from said regulators. The method of claim 99, wherein Wherein said avalanche amplifying structure is geometrically and dimensionally identical. The method of claim 99, wherein The avalanche amplifying structure is a multi-channel structure, characterized in that the triangular, rectangular, square, polygonal or circle shape. The method of claim 99, wherein And the first electrodes are provided as single continuous elements. 107. The method of claim 106, And wherein said single continuous element is transparent. The method of claim 99, wherein And a dielectric layer within each said avalanche amplifying structure. The method of claim 99, wherein Wherein said substrate layers are provided as a single continuous element. The method of claim 99, wherein And the second electrodes are provided as single continuous elements. 113. The method of claim 110, And wherein said single continuous element is transparent. The method of claim 99, wherein And a third electrode in said avalanche amplifying structure. The method of claim 99, wherein And the third electrodes are provided as a single continuous element. 115. The method of claim 113, And wherein said single continuous element is transparent. The method of claim 99, wherein And the first electrodes are transparent. The method of claim 99, wherein And the second electrodes are transparent. The method of claim 99, wherein And the third electrodes are transparent. The method of claim 99, wherein And a blocking layer in each said avalanche amplifying structure. The method of claim 99, wherein And a signal transport layer in each said avalanche amplifying structure. The method of claim 99, wherein And a contact region within each said avalanche amplifying structure. At least two avalanche amplifying structures arranged and arranged separately to form an array, each said avalanche amplifying structure comprising at least two electrodes disposed near an avalanche region layer, a regulator layer, a dielectric layer, and a substrate, Two of the layers are contacted along a first interface that functions as a quantifier, two of the layers are contacted along a second interface that functions as an accumulator, the quantifier controls an avalanche process, and the regulator is configured to Venting and controlling the quantifier. 128. The method of claim 121, wherein Adjacent pairs of avalanche amplifying structures separated at least 0.5 μm apart. 128. The method of claim 121, wherein The gap between the accumulators is filled with a semiconductor material constituting the avalanche region. 128. The method of claim 121, wherein Wherein the spacing between the accumulators is filled with a lightly doped semiconductor material having the same conductivity type as the accumulators. 128. The method of claim 121, wherein The spacing between the accumulators is filled with a dielectric material separating the accumulators from the regulators. 128. The method of claim 121, wherein And said avalanche amplifying structures are geometrically and dimensionally identical. 128. The method of claim 121, wherein And said avalanche amplifying structures are triangular, rectangular, square, polygonal, or circular in shape. 128. The method of claim 121, wherein And the first electrodes are provided as a single continuous element. 131. The method of claim 128, And wherein said single continuous element is transparent. 128. The method of claim 121, wherein And a dielectric layer within each said avalanche amplifying structure. 128. The method of claim 121, wherein Wherein said substrate layers are provided as a single continuous element. 128. The method of claim 121, wherein And the second electrodes are provided as single continuous elements. 133. The method of claim 132, And wherein said single continuous element is transparent. 128. The method of claim 121, wherein And a third electrode in each said avalanche amplifying structure. 128. The method of claim 121, wherein And the third electrodes are provided as a single continuous element. 136. The method of claim 135, wherein And wherein said single continuous element is transparent. 128. The method of claim 121, wherein And the first electrodes are transparent. 128. The method of claim 121, wherein And the second electrodes are transparent. 128. The method of claim 121, wherein And the third electrodes are transparent. 128. The method of claim 121, wherein And a blocking layer in each said avalanche amplifying structure. 128. The method of claim 121, wherein And a signal transport layer in each said avalanche amplifying structure. 128. The method of claim 121, wherein And a contact region within each said avalanche amplifying structure. A multi-channel structure comprising at least two avalanche amplifying structures arranged and arranged separately to form an array, wherein each avalanche amplifying structure comprises at least two electrodes disposed near an avalanche region layer, a regulator layer, a dielectric layer, and a substrate. Wherein the two electrodes are contacted along an interface that functions as a quantifier and as an accumulator, the quantifier controls the avalanche process, the accumulator accumulates signal charge, and the regulator discharges the accumulator And controlling the quantizer. 143. The method of claim 143, wherein Adjacent pairs of avalanche amplifying structures separated at least 0.5 μm apart. 143. The method of claim 143, wherein The gap between the accumulators is filled with a semiconductor material constituting the avalanche region. 143. The method of claim 143, wherein Wherein the spacing between the accumulators is filled with a lightly doped semiconductor material having the same conductivity type as the accumulators. 143. The method of claim 143, wherein The spacing between the accumulators is filled with a dielectric material separating the accumulators from the regulators. 143. The method of claim 143, wherein And said avalanche amplifying structures are geometrically identical in dimension. 143. The method of claim 143, wherein And said avalanche amplifying structures are triangular, rectangular, square, polygonal, or circular in shape. 143. The method of claim 143, wherein And the first electrodes are provided as a single continuous element. 143. The method of claim 143, wherein And wherein said single continuous element is transparent. 143. The method of claim 143, wherein And a dielectric layer within each said avalanche amplifying structure. 143. The method of claim 143, wherein Wherein said substrate layers are provided as a single continuous element. 143. The method of claim 143, wherein And the second electrodes are provided as single continuous elements. 143. The method of claim 143, wherein And wherein said single continuous element is transparent. 143. The method of claim 143, wherein And a third electrode in each said avalanche amplifying structure. 143. The method of claim 143, wherein And the third electrodes are provided as a single continuous element. 158. The method of claim 157, And wherein said single continuous element is transparent. 143. The method of claim 143, wherein And the first electrodes are transparent. 143. The method of claim 143, wherein And the second electrodes are transparent. 143. The method of claim 143, wherein And the third electrodes are transparent. 143. The method of claim 143, wherein And a blocking layer in each said avalanche amplifying structure. 143. The method of claim 143, wherein And a signal transport layer in each said avalanche amplifying structure. 143. The method of claim 143, wherein And a contact region within each said avalanche amplifying structure. 143. The method of claim 143, wherein And wherein the multi-channel structure is applicable to night vision equipment for improved sensing performance in counter-terrorism applications.

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