KR20080073560A - Thin film transistor and method of manufacturing the same, and display having the same - Google Patents

Abstract

A thin film transistor, a manufacturing method thereof, and a display device having the TFT(Thin Film Transistor) are provided to crystallize an activate layer using a single laser irradiation process by adjusting a crystallizing process of the active layer using the heat, which is delivered to a metal pattern. A metal pattern(120) is formed on a predetermined region of a substrate. An active layer(140) is formed to be overlapped with the metal pattern. A gate electrode(151) is formed on the active layer, such that the gate electrode is partially overlapped with the active layer. Source and drain electrodes(161,162) are formed to be connected to a portion of the active layer through an insulation film. The source and drain electrodes are arranged to be separated from each other by a predetermined distance. A buffer layer(131) is formed on the substrate containing the metal pattern.

Description

Thin film transistor and method for manufacturing the same, and display device having same {Thin film transistor and method of manufacturing the same, and display having the same}

1 is a cross-sectional view of a thin film transistor according to an exemplary embodiment of the present invention.

2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a thin film transistor according to an embodiment of the present invention.

3 is a plan view of a metal pattern applied to the thin film transistor according to an embodiment of the present invention.

4 is a plan view of a liquid crystal display panel including a thin film transistor according to another exemplary embodiment of the present invention.

5 is a cross-sectional view taken along the line II ′ of FIG. 4;

<Explanation of symbols for the main parts of the drawings>

100 thin film transistor substrate 200 color filter substrate

110: insulating substrate 120: metal pattern

131: buffer layer 132: gate insulating film

133: insulating film 134: protective film

140: active layer 140c: channel region

140s: source region 140d: drain region

150: gate line 151: gate electrode

152 sustain electrode line 153 sustain electrode

160: data line 161: source electrode

162: drain electrodes 171 and 172: contact hole

180 pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a top gate type thin film transistor using a low temperature polysilicon (LTPS) and a method of manufacturing the same.

A thin film transistor (TFT) substrate is used as a circuit board for independently driving each pixel in a liquid crystal display (LCD), an organic electroluminescent (EL) display, and the like. The thin film transistor substrate includes a gate line, a data line, a thin film transistor, and a pixel electrode. The thin film transistor includes a gate electrode that is part of a gate line, an active layer used as a channel, a source electrode and a drain electrode that is part of a data line, and a gate insulating film and a protective film.

The active layer of the thin film transistor is formed using amorphous silicon or polysilicon. Amorphous silicon can be deposited at low temperatures and has excellent off current characteristics, but is only used to form switching elements in the display area in display devices because the charge mobility is very low, around 0.5 cm2 / Vs. The circuit forms a separate driving IC (Integrated Circuit) to be mounted around. On the other hand, since polysilicon has a fully aligned atomic structure, its charge mobility is much higher than that of amorphous silicon, which is about tens to hundreds of cm 2 / Vs, so that a thin film transistor can be used to integrate a driving circuit in a substrate at the same time as forming a pixel portion. Therefore, the driving IC cost and the process equipment cost can be reduced, and the power consumption can be lowered. Therefore, in recent years, the research which manufactures a thin film transistor by forming polysilicon on a glass substrate becomes active actively.

However, since the glass substrate for fabricating the thin film transistor is deformed at a high temperature of 600 ° C. or higher, Low Temperature Poly Silicon (LTPS), which forms amorphous silicon to form polysilicon and crystallizes at low temperature, has been proposed. An Excimer Laser Annealing (hereinafter referred to as "ELA") process has been proposed as a method to crystallize amorphous silicon. However, the ELA process cannot fabricate a high mobility polysilicon thin film transistor due to the limitation of grain size, and thus is limited in peripheral circuit integration.

As an alternative to the ELA process, a sequential lateral solidification (hereinafter referred to as "SLS") process has been proposed. The SLS process can control various particle sizes (several micrometers to single crystals) as desired compared to the ELA process, and has a wide process margin. In addition, it is attracting attention as a next-generation crystallization technology due to various advantages such as no limitation in substrate size, no need for vacuum, and greatly improved throughput.

The SLS process is a process in which amorphous silicon is locally melted by crystallization by irradiating a laser through a slit of a mask. In more detail, a portion of the amorphous silicon irradiated with the laser through the slit of the mask is completely melted, and an area not irradiated with the laser remains unmelted. Crystallization proceeds from the region irradiated with the laser to the center of the region irradiated with the laser while gradually cooling from the region irradiated with the laser. This SLS process moves the slits little by little and repeats melting and crystallization to crystallize a predetermined area of amorphous silicon. Therefore, the laser must be irradiated at least twice to crystallize a predetermined area of amorphous silicon.

Polysilicon crystallized by the SLS process has the advantage of coarse particle size and precise control of the position of the main grain boundary, but it is impossible to control the position of the implant system in the thin film transistor channel. There are disadvantages. That is, when the active layer is patterned after crystallization, the microstructure of each thin film transistor is formed.

Meanwhile, low temperature polysilicon is generally formed in a top gate structure in which a gate electrode is formed on an active layer. Accordingly, unlike an amorphous silicon thin film transistor having a bottom gate structure in which a gate blocks light incident from a lower backlight, the active layer is directly exposed to light. When the product brightness is low until recently, there was no big problem, but recently, as the demand for high brightness products increases, the light applied from the bottom becomes stronger, causing a problem of increasing the leakage current of polysilicon. Leakage current causes crosstalk, which greatly degrades product characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor capable of crystallizing a predetermined region of amorphous silicon with only one laser irradiation and a method of manufacturing the same.

Another object of the present invention is to provide a thin film transistor and a method of manufacturing the same, which can all make the same microstructure in each thin film transistor channel.

Another object of the present invention is to provide a display device having a thin film transistor which can prevent an increase in leakage current of the active layer by preventing the active layer from being exposed to light incident from a lower backlight.

A thin film transistor according to an embodiment of the present invention is a metal pattern formed in a predetermined region on the substrate; An active layer formed to overlap the metal pattern; A gate electrode formed on the active layer to partially overlap the active layer; And a source electrode and a drain electrode formed to be respectively connected to a part of the active layer through an insulating film, and spaced apart from each other by a predetermined interval.

And a buffer layer formed on the substrate including the metal pattern or on the substrate under the metal pattern.

The metal pattern may include a plurality of first metal patterns having a predetermined width and a spacing in a first row, and a second metal pattern may be formed in a second row alternately with the first metal pattern to form a plurality of metal patterns formed in the plurality of rows. Include.

And a gate insulating film formed between the active layer and the gate electrode.

The active layer includes a channel region in which impurities are not implanted, a source region in which impurities are implanted, and a drain region.

The channel region overlaps the gate electrode, and the source region and the drain region are connected to the source electrode and the drain electrode, respectively.

In another embodiment, a method of manufacturing a thin film transistor includes forming a metal pattern on a predetermined region of an upper portion of a substrate; Forming amorphous silicon to overlap the metal pattern; Irradiating the amorphous silicon with a laser to melt the amorphous silicon, and transferring heat from the laser to the metal pattern; Forming an active layer by crystallizing gradually from the amorphous silicon above the region where the metal pattern is not formed to the amorphous silicon above the region where the metal pattern is formed; Forming a gate insulating film and a gate electrode on the active layer to partially overlap the active layer; And forming a source electrode and a drain electrode connected to the predetermined region of the active layer through the predetermined region of the insulating layer after forming the insulating layer on the entire structure.

The method may further include forming a buffer layer below or on the metal pattern.

And forming an impurity ion implantation process using the gate electrode as a mask after forming the gate electrode.

In another embodiment, a display device includes: a metal pattern formed in a predetermined area on a first substrate; An active layer formed to overlap the metal pattern; A gate line formed on the substrate and extending in one direction, the gate line including a gate electrode partially overlapping the active layer; A data line extending in a direction orthogonal to the gate line, the data line including a source electrode and a drain electrode formed to be connected to a part of the active layer; And a pixel electrode formed to be connected to the drain electrode.

The display apparatus may further include a second substrate disposed to face the first substrate and having a color filter and a common electrode formed thereon.

Further comprising a liquid crystal layer formed between the first and second substrate.

The apparatus may further include a backlight unit for irradiating light from the lower portion of the first substrate.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a cross-sectional view of a thin film transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a thin film transistor according to an exemplary embodiment of the present disclosure may include a plurality of metal patterns 120 and metal patterns formed at predetermined widths and intervals on a predetermined region of an insulating substrate 110 such as a glass substrate. The buffer layer 131 formed on the substrate 110 including the 120 and the metal pattern 120 formed on the buffer layer 131 and overlap the channel region 140c, the source region 140s, and the drain region 140d. An active layer 140 including the active layer 140, a gate insulating layer 132 formed on the substrate 110 including the active layer 140, and a channel region 140c of the active layer 140 formed on the gate insulating layer 132. The source region of the active layer 140 is formed through the gate electrode 151, the insulating layer 133 formed on the substrate 110 including the gate electrode 151, and predetermined regions of the insulating layer 133 and the gate insulating layer 132. 140 s) and the drains 140d and respectively connected to and spaced apart from each other. It includes an electrode 161 and a drain electrode 162.

Here, the metal pattern 120 is formed to overlap the active layer 140, and is formed by patterning the metal layer to be discontinuously arranged. As shown in FIG. 3, the metal pattern 120 may include, for example, a plurality of first metal patterns having a predetermined width and a spacing in a first column, and a second column having a first metal pattern arranged in a first column. A staggered second metal pattern is formed. In this way, the metal pattern 120 is formed by the width and width of the active layer. In addition, the metal pattern 120 is formed using the same material as the metal layer for forming the gate electrode 151, the metal layer for forming the source electrode 161, and the drain electrode 162, or a metal material of the same category. Meanwhile, in the above embodiment, the metal pattern 120 is formed under the buffer layer 131, but the metal pattern 120 may be formed on the buffer layer 130.

The active layer 140 is formed by crystallizing amorphous silicon, and the process of crystallizing the active layer 140 is as follows. The laser is irradiated using a mask that opens a predetermined area of the amorphous silicon to melt the amorphous silicon, and heat from the laser is transferred to the lower metal pattern 120 to maintain the high temperature of the metal pattern 120. do. After the molten amorphous silicon is cooled, crystallization is performed. The amorphous silicon on the region where the metal pattern 120 is not formed is cooled faster than the amorphous silicon on the region where the metal pattern 120 is formed, and the metal pattern is gradually reduced. Amorphous silicon is crystallized while cooling to the upper amorphous silicon (120). In addition, the active layer 140 may be patterned after crystallization or may be patterned before crystallization.

Meanwhile, impurities may not be implanted in the channel region 140c of the active layer 140, and impurities may be formed in the source region 140s and the drain region 140d.

2 (a) to 2 (d) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, a metal layer is formed on an insulating substrate 110, such as a glass substrate, and then patterned to form a metal pattern 120. The metal pattern 120 is formed to overlap the active layer to be formed later, and is formed by patterning the metal layer to be discontinuously arranged. The metal pattern 120 preferably includes a plurality of first metal patterns having a predetermined width and a spacing in a first row, and a second metal pattern is formed in the second row alternately with the first metal pattern arranged in the first row. do. In this way, the metal pattern 120 is formed by the width and width of the active layer to be formed later. The metal pattern 120 is formed using at least one metal of Al, Nd, Ag, Ti, Ta, Mo, Cr, MoW, and Cu or an alloy containing them. It may be formed as a single layer, or may be formed as a multilayer formed by laminating the metals. The buffer layer 131 is formed by forming at least one material selected from an insulating material including a silicon oxide film and a silicon nitride film on the substrate 110 including the metal pattern 120.

Referring to FIG. 2B, amorphous silicon is formed on the buffer layer 131 to have a predetermined thickness. After patterning the amorphous silicon to overlap the metal pattern 120, the laser is irradiated using a mask that exposes the amorphous silicon. When the laser is irradiated, amorphous silicon is melted, and heat generated by the laser is transmitted to the metal pattern 120. Therefore, the metal pattern 120 maintains a high temperature state. Thereafter, the amorphous silicon is crystallized as it is cooled, and crystallized by cooling from the amorphous silicon of the upper portion of the region where the metal pattern 120 is not formed, and crystallized while gradually cooling to the amorphous silicon of the upper portion of the region where the metal pattern 120 is formed. Accordingly, all of the amorphous silicon is crystallized to form the active layer 140.

Referring to FIG. 2C, after the gate insulating layer 132 is formed over the entire structure including the active layer 140, a conductive layer is formed. The conductive layer is patterned to partially overlap the active layer 140 to form the gate electrode 151. Impurities are ion-implanted using the gate electrode 151 as a mask to form a source region 140s and a drain region 140d in the active layer 140 on both sides of the gate electrode 151. The active layer 140 under the gate electrode 151 where the impurities are not ion implanted becomes the channel region 140c. Here, the gate electrode 151 is formed using at least one metal of Al, Nd, Ag, Ti, Ta, Mo, Cr, MoW, and Cu or an alloy containing them. It may be formed as a single layer, or may be formed as a multilayer formed by laminating the metals.

Referring to FIG. 2 (d), an insulating film 133 is formed over the entire structure including the gate electrode 161, and then predetermined regions of the protective film 133 and the gate insulating film 132 are etched to form a source of the active layer 140. A contact hole exposing the region 140s and the drain region 140d is formed. The conductive layer is formed on the entire structure to fill the contact hole, and then patterned to be spaced apart from each other to form the source electrode 161 and the drain electrode 162. Here, the source electrode 161 and the drain electrode 162 are formed using at least one metal of Al, Nd, Ag, Ti, Ta, Mo, Cr, MoW, and Cu or an alloy containing them. It may be formed as a single layer, or may be formed as a multilayer formed by laminating the metals.

Meanwhile, in the above embodiment, the metal pattern 120 is formed below the buffer layer 131, and the active layer 140 is formed by patterning amorphous silicon and crystallizing the amorphous layer, but the metal pattern 120 is the buffer layer 131. ) And an active layer 140 may be formed by crystallizing amorphous silicon and then patterning the amorphous silicon.

4 is a plan view of a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the liquid crystal display panel taken along the line II ′ of FIG. 4.

4 and 5, a liquid crystal display panel according to an exemplary embodiment of the present invention may include a thin film transistor substrate 100 and a color filter substrate 200 facing each other, and a liquid crystal layer (not shown) formed therebetween. Include.

The thin film transistor substrate 100 includes a metal pattern 120 formed in a predetermined region on the insulating substrate 110, an active layer 140 formed to overlap the metal pattern 120, and a plurality of gate lines extending in one direction. And a plurality of data lines 160 extending in a direction crossing the gate line 150 and a pixel electrode 180 formed in the pixel region defined by the gate line 150 and the data line 160. ), A thin film transistor 155 connected to the gate line 150, the data line 160, and the pixel electrode 180, and a storage electrode formed in parallel with the gate line 150 and including the storage electrode 153. Line 152.

The metal pattern 120 is formed by discontinuously arranging metal layers at predetermined widths and intervals in a predetermined region on the insulating substrate 110. The metal pattern 120 preferably has a plurality of first metal patterns having a predetermined width and spacing formed in a first row, and a second metal pattern formed alternately with a first metal pattern arranged in a first row in a second row. do. In this manner, the plurality of rows of metal patterns 120 are formed to overlap the active layer 140. The metal pattern 120 is used for crystallization of the active layer 140, and also plays a role similar to that of a black matrix that blocks light incident from the backlight under the thin film transistor substrate 100 from affecting the active layer 140. .

The buffer layer 131 is formed on the insulating substrate 110 including the metal pattern 120. The buffer layer 131 is formed using at least one material selected from insulating materials including a silicon oxide film and a silicon nitride film. The metal pattern 120 may be formed below the buffer layer 131 or may be formed above the buffer layer 131.

The active layer 140 is formed to overlap the metal pattern 120 on the buffer layer 131. The active layer 140 is formed using low-temperature polysilicon formed by crystallizing amorphous silicon, and crystallized by cooling the amorphous silicon by irradiating the laser with amorphous laser. The laser is irradiated to melt the amorphous silicon, and the heat of the laser is transferred to the metal pattern 120 to maintain the high temperature state of the metal pattern 120. In this state, the amorphous silicon is cooled and crystallized. The amorphous silicon on the region where the metal pattern 120 is not formed cools down faster than the amorphous silicon on the region where the metal pattern 120 is formed. The crystal layer is cooled while crystallization to the amorphous silicon formed on the upper portion (120) to form an active layer (140). In addition, the active layer 140 includes a channel region 140c in which impurities are implanted under the gate electrode 151, a source region 140s in which impurities are injected at both sides of the gate electrode 151, and a drain region 140d. do. The active layer 140 may be patterned before crystallization, but may be patterned after crystallization.

The gate insulating layer 132 is formed on the substrate 110 including the active layer 140. The gate insulating film 132 is formed using at least one selected from an insulating material including a silicon oxide film and a silicon nitride film.

The gate line 150 is formed to form a conductive layer on the gate insulating layer 132 and then patterned to extend in the horizontal direction. A portion of the gate line 150 protrudes upward or downward to form the gate electrode 151. do. The gate electrode 151 is partially overlapped with the active layer 140, and is formed to overlap the channel region 140c in which impurities are not implanted.

The storage electrode line 152 including the storage electrode 153 is formed between the two gate lines 150 when the gate line 150 is formed, and may be formed in the center between the gate lines 150. It may be formed in close proximity to the gate line 150.

An insulating layer 133 is formed on the substrate 110 including the gate line 150 and the storage electrode line 152. The insulating film 133 is formed in a single layer or multiple layers using an insulating material including a silicon oxide film and a silicon nitride film. In addition, the insulating layer 133 may be formed thicker than the buffer layer 131 and the gate insulating layer 132.

The data line 160 is formed to extend perpendicularly to the gate line 150 by patterning the conductive layer, and a portion of the data line 160 protrudes to form the source electrode 161. In addition, the drain electrode 162 is formed to be spaced apart from the source electrode 161 by a predetermined interval when the data line 160 is formed. The source electrode 161 is formed so that predetermined regions of the insulating layer 133 and the gate insulating layer 132 are etched and connected to the source region 140s of the exposed active layer 140, and the drain electrode 162 is formed of the insulating layer 133. And a predetermined region of the gate insulating layer 132 is etched and connected to the drain region 140d of the exposed active layer 140.

The thin film transistor 155 causes the pixel signal supplied to the data line 160 to be charged in the pixel electrode 180 in response to the signal supplied to the gate line 150. Accordingly, the thin film transistor 155 may include a gate electrode 151 connected to the gate line 150, a source electrode 161 connected to the data line 160, and a drain electrode 162 connected to the pixel electrode 180. ), An active layer 140 and a gate insulating layer 132 formed on the substrate 110 under the gate electrode 151. In addition, characteristics of the thin film transistor 155 may vary according to impurities injected into the source region 140s and the drain region 140d of the active layer 140. For example, when the thin film transistor 155 has an n channel, a high concentration of n-type ions is implanted into the source region 140s and the drain region 140d of the active layer 140, and when the thin film transistor 155 has a p channel, P-type ions are implanted into the source region 140s and the drain region 140d of the active layer 140.

The passivation layer 134 is formed on the substrate 110 on which the data line 160 is formed. The passivation layer 134 is formed of a single layer or multiple layers using an insulating material including at least one of an inorganic insulating material and an organic insulating material. Examples of the inorganic insulating material include a silicon oxide film and a silicon nitride film having excellent insulating properties. As the organic insulating material, a low dielectric constant, BCB (Benzene Cyclo Butane), SOG (Siloxane Polymer), and polyimide resin are used.

The pixel electrode 180 is formed in the pixel region defined by the gate line 150 and the data line 160 by patterning a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 180 is connected to the drain electrode 162 through the first contact hole 171 formed by etching a predetermined region of the passivation layer 134, and the upper portion of the insulating layer 133 through the second contact hole 172. Formed to form a storage capacitor with the storage electrode 153.

The color filter substrate 200 includes a black matrix 220 formed on the insulating substrate 210, a color filter 230, an overcoat layer 240, and a common electrode 250.

The black matrix 220 is formed in an area other than the pixel area to prevent light leakage from the area other than the pixel area and optical interference between adjacent pixel areas. That is, the black matrix 220 has an opening that opens an area where the pixel electrode 180 of the thin film transistor substrate 100 is formed.

The color filter 230 is formed by repeating red, green, and blue filters with the black matrix 220 as the boundary. The color filter 230 serves to impart color to light emitted from the light source and passing through the liquid crystal layer (not shown). The color filter 230 may be formed of a photosensitive organic material.

The overcoat layer 240 is formed on the black matrix 220 which is not covered by the color filter 230 and the color filter 230. The overcoat layer 240 serves to protect the color filter 230 and to insulate the upper and lower conductive layers while planarizing the color filter 230, and may be formed using an acrylic epoxy material.

The common electrode 250 is formed on the overcoat layer 240. The common electrode 250 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode 250 applies a voltage to the liquid crystal layer (not shown) together with the pixel electrode 180 of the thin film transistor substrate.

As described above, according to the present invention, by forming a metal pattern under the active layer and controlling the crystallization of the active layer by heat transferred to the metal pattern, the active layer can be crystallized with only one laser irradiation, thereby reducing the number of processes and costs. In addition, the fine structure of the active layer can all be the same to allow patterning after crystallization, thereby increasing the process margin. In addition, a metal pattern formed under the active layer prevents light from the backlight from entering the active layer, thereby preventing leakage of the active layer.

Claims (14)

A metal pattern formed in a predetermined region on the substrate; An active layer formed to overlap the metal pattern; A gate electrode formed on the active layer to partially overlap the active layer; And And a source electrode and a drain electrode formed to be connected to a part of the active layer through an insulating film, and spaced apart from each other by a predetermined interval. The thin film transistor of claim 1, further comprising a buffer layer formed on the substrate including the metal pattern. The thin film transistor of claim 1, further comprising a buffer layer formed on the substrate under the metal pattern. The method of claim 1, wherein the metal pattern has a plurality of first metal patterns having a predetermined width and spacing are formed in a first row, and the second metal pattern is formed in a second row to alternate with the first metal pattern in a plurality of rows. A thin film transistor comprising a plurality of metal patterns formed. The thin film transistor of claim 1, further comprising a gate insulating layer formed between the active layer and the gate electrode. The thin film transistor of claim 1, wherein the active layer comprises a channel region and a source region and a drain region implanted with impurities. The thin film transistor of claim 6, wherein the channel region overlaps the gate electrode, and the source region and the drain region are connected to the source electrode and the drain electrode, respectively. Forming a metal pattern on a predetermined region on the substrate; Forming amorphous silicon to overlap the metal pattern; Irradiating the amorphous silicon with a laser to melt the amorphous silicon, and heat from the laser is transferred to the metal pattern; Forming an active layer by crystallizing gradually from the amorphous silicon above the region where the metal pattern is not formed to the amorphous silicon above the region where the metal pattern is formed; Forming a gate insulating film and a gate electrode on the active layer to partially overlap the active layer; And Forming a source electrode and a drain electrode connected to a predetermined region of the active layer through a predetermined region of the insulating layer after forming an insulating layer on the entire structure. The method of claim 8, further comprising forming a buffer layer below or over the metal pattern. The method of claim 8, further comprising performing an impurity ion implantation process using the gate electrode as a mask after forming the gate electrode. A metal pattern formed in a predetermined region on the first substrate; An active layer formed to overlap the metal pattern; A gate line formed on the substrate and extending in one direction, the gate line including a gate electrode partially overlapping the active layer; A data line extending in a direction crossing the gate line, the data line including a source electrode and a drain electrode formed to be connected to a part of the active layer; And And a pixel electrode formed to be connected to the drain electrode. The display device of claim 11, further comprising a second substrate disposed to face the first substrate and having a color filter and a common electrode formed thereon. The display device of claim 11, further comprising a liquid crystal layer formed between the first and second substrates. The display device of claim 11, further comprising a backlight unit for irradiating light from a lower portion of the first substrate.

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