KR20080073431A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to enhance display quality thereof by increasing the effective frame frequency of screen up to double times. An LCD(Liquid Crystal Display) device includes an LCD panel(10) and a driver. The LCD panel includes pixel cells at sections defined by plural gate and data lines which cross each other. The pixel cells are separated into first and second pixel cell groups with respect to a horizontal line. The driver drives differently the first and second pixel cell groups during one frame period. The one frame period includes first and second periods.

Description

Liquid crystal display device and driving method thereof

1 is a schematic view illustrating a liquid crystal display and a driving method thereof according to a first embodiment of the present invention.

2 is a frame diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

3A illustrates a screen displayed on a liquid crystal panel during one frame period of the liquid crystal display according to an exemplary embodiment of the present invention.

3B and 3C illustrate screens displayed on a liquid crystal panel during a ½ frame period of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a schematic diagram illustrating a liquid crystal display and a driving method thereof according to a second embodiment of the present invention.

5 is a schematic view illustrating a liquid crystal display and a driving method thereof according to a third embodiment of the present invention.

6A and 6B illustrate screen change in units of frames when a video is driven.

<Description of Symbols for Main Parts of Drawings>

10 liquid crystal panel 16 data driver

18: gate driver 26: timing controller

30: pixel area 32: liquid crystal cell

36: TFT

The present invention relates to a liquid crystal display and a driving method, and more particularly to a liquid crystal display and a driving method that can improve the display quality through the effective frame frequency of the screen.

As the information society develops, the demand for display devices is gradually increasing in various forms. Recently, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), Various flat panel display devices such as VFD (Vacuum Fluorescent Display) have been studied, and some of them are already used as display devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In general, a liquid crystal display (LCD) displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. Such a liquid crystal display may be classified into a liquid crystal panel displaying a video signal and a driving circuit applying a driving signal to the liquid crystal panel from the outside. Although not shown in the drawings, the liquid crystal panel is composed of two transparent substrates (glass substrates) bonded to each other with a predetermined space and a liquid crystal layer formed between the two substrates.

In the liquid crystal display device configured as described above, when the pixel voltage signal in the same direction is continuously applied to the liquid crystal layer, the liquid crystal layer deteriorates and the display quality of the screen is degraded. Has been proposed to invert the pixel voltage applied to the pixel electrode to be positive (+) or negative (-) with respect to the common voltage applied to the common electrode.

As the polarity inversion driving method, inversion driving methods such as a line inversion system, a column inversion system, and a dot inversion system are used.

The line inversion driving method has a problem in that flicker such as a stripe pattern occurs between the horizontal lines due to the crosstalk between the horizontal pixel areas, and the column inversion driving method includes the crosstalk between the vertical pixel areas. As a result, there is a problem in that a fricker phenomenon such as a stripe pattern occurs between vertical lines.

Accordingly, in order to solve the problems of the line inversion driving method and the column inversion driving method, a dot inversion driving method is proposed in which each pixel area and the adjacent pixel areas in the vertical and horizontal directions have different polarities. However, in the dot inversion driving method, the polarity of the pixel voltage signal applied to each pixel area through the data line in the data driver must be inverted every frame in the horizontal and vertical directions. The polarity variation of the data signal applied to the pixel region is increased, resulting in an increase in power consumption.

In addition to the above-described driving method, a driving method of increasing the frame frequency of the screen has been proposed to improve the display quality of the LCD. However, when the frame frequency of the screen is increased, power consumption increases, and there is a problem in that the manufacturing cost of the liquid crystal display device is increased due to the application of expensive devices to drive at a high frequency.

The liquid crystal display device and the driving method thereof according to an embodiment of the present invention have been devised to solve the above problems, and can improve the display quality by improving the effective frame frequency of the screen and reduce the manufacturing cost. It is an object of the present invention to provide a liquid crystal display and a driving method thereof.

A liquid crystal display according to an exemplary embodiment of the present invention for achieving the above object includes a liquid crystal panel including pixel cells formed in regions defined by a plurality of crossing gate lines and a plurality of data lines, and the pixel cells. And a driving circuit unit configured to divide the first pixel cell group and the second pixel cell group on the basis of a horizontal line, and to drive the first pixel cell group and the second pixel cell group with a parallax in one frame period. It is characterized by.

A driving method of a liquid crystal display device according to an exemplary embodiment of the present invention includes a plurality of data lines vertically crossing each other and a plurality of gate lines including a first gate line group and a second gate line group. A plurality of pixel cells constituting a unit pixel are divided into a first pixel cell group and a second pixel cell group based on a horizontal line, and the first pixel cell group and the second pixel cell group are divided into one frame period. It characterized in that it comprises a step of driving with a parallax.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic view illustrating a liquid crystal display and a driving method thereof according to a first embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to a first exemplary embodiment of the present invention includes a pixel region 30 formed for each region defined by a plurality of gate lines GL1 to GL4 and a plurality of data lines DL1 to DL6. ), A gate driver 18 sequentially supplying a gate driving signal to each of the gate lines GL1 to GL4, and image data R, G, and B to the gate driving signal. The data driver 16 is supplied to the data lines DL1 to DL6 so as to be synchronized with the image data R, G, and B from the outside, and the data driver 16 is supplied to the data driver 16. The data driver 16 and And a timing controller 26 for controlling the driving of the gate driver 18.

The liquid crystal panel 10 includes a transistor array substrate and a color filter array substrate bonded to each other, a spacer for maintaining a constant cell gap between the two array substrates, and a liquid crystal filled in a space provided by the spacer.

The liquid crystal panel 10 includes a TFT 36 formed in a region defined by n gate lines and m data lines, and a liquid crystal cell 32 connected to the TFT 36.

The TFT 36 supplies an analog video signal from the data lines DL1 to DL6 to the liquid crystal cell 32 in response to the gate driving signal from the gate lines GL1 to GL4.

The liquid crystal cell 32 includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the TFT 36, so that the liquid crystal cell 32 may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacity Cst for maintaining the analog video signal charged in the liquid crystal capacitor Clc until the next analog video signal is charged.

The TFT 36 includes a gate electrode connected to the gate lines GL1 to GL4, a source electrode connected to the data lines DL1 to DL6, and a drain electrode connected to the pixel electrode. At this time, each of the TFTs 36 is disposed in a staggered form along the gate lines GL1 to GL4. That is, the TFTs 36 of each of the two pixel cells 32 adjacent to the left and right along the gate lines GL1 to GL4 are connected to different data lines DL.

The timing controller 26 arranges the image data R, G, and B input from the outside so as to be suitable for driving the liquid crystal panel 10, and supplies the image data 16 to the data driver 16. In addition, the timing controller 26 uses the dot clock DLCK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync input from the outside. GCS) is generated to control the driving timing of each of the data driver 16 and the gate driver 18.

The gate control signal GCS generated by the timing controller 26 and controlling the driving timing of the gate driver 18 is composed of a first gate signal and a second gate signal. The timing controller 26 divides the period of one frame into two periods ("A", "B") each having a half frame period, as shown in FIG. One gate signal is supplied to the gate driver 16, and a second gate signal is supplied to the gate driver 16 in the second half frame ("B") period.

The gate driver 18 includes a shift register that sequentially generates the gate driving signal in response to the gate control signal GCS from the timing controller 26. In response to the gate control signal GCS including the first gate control signal and the second gate control signal input from the timing controller 26, the gate driver 18 may have an odd number in the first half frame (“A”) period. The first gate driving signal is sequentially applied to the gate lines G1 and G3, and the second gate driving signal is sequentially applied to the even-numbered gate lines GL2 and GL4 during the second half frame (“B”) period. As a result, the TFT 36 connected to the respective gate lines GL1 to GL4 is turned on.

The data driver 16 converts image data supplied from the timing controller 26 into an analog video signal in response to the data control signal DCS supplied from the timing controller 26 to gate the gate lines GL1 to GL4. The analog video signal corresponding to the line is supplied to the data lines DL1 to DL6 every time the driving signal is supplied. In this case, the data driver 16 may invert the polarity of the analog video signal supplied to the data lines DL1 to DL6 in response to the polarity control signal POL.

In the liquid crystal display according to the first exemplary embodiment of the present invention, a plurality of pixel cells 1R1 to 1B2, 2R1 to 2B2, and 3R1 to 3B2 constituting one horizontal line are divided into two pixel cell groups. The gate lines GL1 to GL4 to which the gate driving signal is applied from the gate driver 18 are driven so that the pixel cell groups are driven with a parallax on one frame, the odd-numbered gate lines GL1 and GL3 and the even-numbered gate lines GL2, Divide by GL4). Thereafter, a gate driving signal is applied to each of the divided odd-numbered gate lines GL1 and GL3 and even-numbered gate lines GL2 and GL4.

That is, the period of one frame is divided into two periods "A" and "B" as shown in FIG. 2, and during the period of "A", the odd-numbered gate line GL1 of the gate lines GL1 to GL4 is divided. A gate driving signal is applied to GL3, and a gate driving signal is applied to even-numbered gate lines GL2 and GL4 of the plurality of gate lines GL1 to GL4 during the period “B”.

More specifically, when the gate driving signal is applied to the first gate line GL1 during the first ½ frame (“A”) period of one frame, 1R1, 1B1, The 1G2 pixel cell is driven. The 1R1 pixel cell receives a data signal from the first data line DL1, the 1B1 pixel cell receives a data signal from the third data line DL3, and the 1G2 pixel cell receives data from the fifth data line DL5. Receive a signal.

Subsequently, when a gate driving signal is applied to the third gate line GL3, the 3R1, 2G1, 3B1, 2R2, 3G2, and 2B2 pixel cells connected to the third gate line GL3 are driven. The 3R1 pixel cell receives a data signal from the first data line DL1, the 2G1 pixel cell receives a data signal from the second data line DL2, and the 3B1 pixel cell receives a data signal from the third data line DL3. The 2R2 pixel cell receives the data signal from the fourth data line DL4, the 3G2 pixel cell receives the data signal from the fifth data line DL5, and the 2B2 pixel cell receives the sixth data line DL6. Data signal is supplied.

As such, the second gate line among the pixel cells that are connected to the first gate line GL1 and the third gate line GL3 and receive the gate driving signal from the connected gate lines GL1 and GL3 are driven. Adjacent R, G, and B pixel cells 1R1, 2G1, 1B1, and 2R2, 1G2, 2B2 form a unit pixel (R, G, B) with GL2 therebetween to display an input video signal. .

Also, among the pixel cells connected to the third gate line GL3 and supplied with the gate driving signal from the third gate line GL3, the 3R1 and 3B1 pixel cells are adjacent to each other with the fourth gate line GL4 interposed therebetween. The G pixel cell (not shown) and the unit pixels R, G, and B are configured, and the 3G2 pixel cell is adjacent to the R and B pixel cells (not shown) and the unit pixel with the fourth gate line GL4 interposed therebetween. R, G, and B) are configured to display the input video signal.

As shown in FIG. 3A during one frame period, when a " △ " shape image is to be displayed on the liquid crystal panel 10, the liquid crystal display according to the first embodiment of the present invention is the first half of the period of one frame. During the frame "A" period, the pixel cells 1R1, 1B1, 1G2, 3R1, 2G1, 3B1, 2R2, 3G2, connected to the first and third gate lines GL1 and GL3 corresponding to odd-numbered gate lines. 2B2) receives an image signal from data lines connected to each of them, and displays some of the entire images as shown in FIG. 3B.

Subsequently, the second and fourth gate lines GL2 and GL4 corresponding to even-numbered lines among the plurality of gate lines GL1 to GL4 are gated during the second half frame (“B”) period of one frame period. The drive signal is applied sequentially.

When a gate driving signal is applied to the second gate line GL2, 2R1, 1G1, 2B1, 1R2, 2G2, and 1B2 pixel cells connected to the second gate line G1 are driven.

The 2R1 pixel cell receives a data signal from the first data line DL1, the 1G1 pixel cell receives a data signal from the second data line DL2, and the 2B1 pixel cell receives a data signal from the third data line DL3. Is supplied, the 1R2 pixel cell is supplied with the data signal from the fourth data line DL4, the 2G2 pixel cell is supplied with the data signal from the fifth data line DL5, and the 1B2 pixel cell is the sixth data line DL6. Data signal is supplied.

Subsequently, when a gate driving signal is applied to the fourth gate line GL4, the 3G1, 3R2, and 3B2 pixel cells connected to the fourth gate line GL4 are driven. The 3G1 pixel cell receives a data signal from the second data line DL2, the 3R2 pixel cell receives a data signal from the fourth data line DL4, and the 3B2 pixel cell receives a data signal from the sixth data line DL6. Get supplied.

As such, the pixel cells 2R1, 1G1, 2B1, 2R2, 1G2, and 2B2 connected to the second gate line GL2 and supplied with the gate driving signal from the second gate line GL2 are connected to the second gate line. Adjacent R, G, and B pixel cells 2R1, 1G1, 2B1, and 2R2, 1G2, 2B2 constitute a unit pixel (R, G, B) with GL2 therebetween to display an input video signal. .

In addition, among the pixel cells connected to the fourth gate line GL4 and supplied with the gate driving signal from the fourth gate line GL4, 3G1 pixel cells are adjacent to each other with the fourth gate line GL4 interposed therebetween. G pixel cells (not shown) and unit pixels are formed, and 3R2 and 3B2 pixel cells have adjacent G pixel cells (not shown) and unit pixels R, G, and B with a fourth gate line GL4 therebetween. And display the input video signal.

As shown in FIG. 3A during one frame period, when a " △ " shape image is to be displayed on the liquid crystal panel 10, the liquid crystal display according to the first embodiment of the present invention has a second half of one frame period. During the frame "B" period, the pixel cells 2R1, 1G1, 2B1, 1R2, 2G2, 1B2, 3G1, and 3R2 connected to the second and fourth gate lines GL2 and GL4 corresponding to even-numbered gate lines. , 3B2) receives an image signal from data lines connected to each of them, and displays some of the entire images as shown in Fig. 6C.

The liquid crystal display according to the first exemplary embodiment of the present invention divides a plurality of pixel cells formed on the liquid crystal panel into two pixel cell groups based on a horizontal line, and divides the pixel cell groups divided by the above-described configuration and driving method. It is driven with a time difference of 1/2 frame on one frame. With this configuration and driving method, a portion of the entire image is displayed as shown in Fig. 3B during the first half frame ("A") period, and as shown in Fig. 3C during the second half frame ("B") period. Similarly, after displaying some of the entire images, the images displayed in these two ½ frame ("A", "B") periods are summed to display the completed image of one frame, as shown in FIG. 3A. .

In the case where a white box is to be moved to the right by 4 pixels per frame on a black background screen, a conventional LCD driving method is performed by one frame as illustrated in FIG. 6A. After this, the white box is shifted by 4 pixels.

When the screen is driven by the driving method according to the first embodiment of the present invention, as shown in FIG. 6B, one frame is divided into two half frames to display each image on the screen, and each of the displayed images is summed and completed. The image of the frame is completed. Through such a driving method, the display quality of the liquid crystal display can be improved by reducing the screen drag phenomenon when the video is driven.

Of course, this is one example. In the method of driving the liquid crystal display according to the first embodiment of the present invention, for convenience of description, the period of one frame is divided into two periods ("A", "B") and each period Although " A " and " B "

In addition, for convenience of description, the gate driving signal is applied to the odd-numbered gate line in the "A" period of one frame period to drive the pixel cells connected to the odd-numbered gate line, and to the even-numbered gate line in the "B" period. The driving of the pixel cells connected to the even-numbered gate lines by applying the gate driving signal is described above. However, the gate driving signal is applied to the even-numbered gate lines in the "A" period to drive the pixel cells connected to the even-numbered gate lines. It is also possible to drive the pixel cells connected to the odd-numbered gate lines by applying a driving signal to the odd-numbered gate lines in the "B " period.

In the liquid crystal display according to the first embodiment of the present invention, the display is configured with 60 frames per second by using the above-described configuration and driving method, thereby improving the effective frame frequency of the screen by up to 2 times. Can improve the display quality.

The liquid crystal display device according to the first embodiment of the present invention can reduce the manufacturing cost compared to the conventional liquid crystal display device for displaying a screen by configuring 75 seconds, 90 seconds, 120 frames per second through the above configuration and driving method .

4 is a schematic view illustrating a liquid crystal display and a driving method thereof according to the second embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display according to the second exemplary embodiment of the present invention includes a pixel region 30 formed for each region defined by a plurality of gate lines GL1 to GL4 and a plurality of data lines DL1 to DL6. ), A gate driver 18 sequentially supplying a gate driving signal to each of the gate lines GL1 to GL4, and image data R, G, and B to the gate driving signal. The data driver 16 is supplied to each of the data lines DL1 to DL6 so as to be synchronized with the image data R, G, and B from outside, and the data driver 16 is supplied to the data driver 16. And a timing controller 26 for controlling the driving of the gate driver 18.

The liquid crystal panel 10 includes a transistor array substrate and a color filter array substrate bonded to each other, a spacer for maintaining a constant cell gap between the two array substrates, and a liquid crystal filled in a space provided by the spacer.

The liquid crystal panel 10 includes a TFT 36 formed in a region defined by n gate lines and m data lines, and a liquid crystal cell 32 connected to the TFT 36.

The TFT 36 supplies an analog video signal from the data lines DL1 to DL6 to the liquid crystal cell 32 in response to the gate driving signal from the gate lines GL1 to GL4.

The liquid crystal cell 32 includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the TFT 36, so that the liquid crystal cell 32 may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacity Cst for maintaining the analog video signal charged in the liquid crystal capacitor Clc until the next analog video signal is charged.

The TFT 36 includes a gate electrode connected to the gate lines GL1 to GL4, a source electrode connected to the data lines DL1 to DL6, and a drain electrode connected to the pixel electrode. At this time, each of the TFTs 36 is disposed in a staggered form along the gate lines GL1 to GL4. That is, the TFTs 36 of the pixel cells 32 adjacent to each other along the gate lines GL1 to GL4 are connected to different data lines DL.

The timing controller 26 arranges the image data R, G, and B input from the outside so as to be suitable for driving the liquid crystal panel 10, and supplies the image data 16 to the data driver 16. In addition, the timing controller 26 uses the dot clock DLCK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync, which are input from the outside, to control the data control signal DCS and the gate control signal. (GCS) is generated to control the driving timings of the data driver 16 and the gate driver 18, respectively.

The gate control signal GCS generated by the timing controller 26 and controlling the driving timing of the gate driver 18 is composed of a first gate signal and a second gate signal. The timing controller 26 divides the period of one frame into two periods ("A", "B") each having a half frame period, as shown in FIG. One gate signal is supplied to the gate driver 16, and a second gate signal is supplied to the gate driver 16 in the second half frame ("B") period.

The gate driver 18 includes a shift register that sequentially generates the gate driving signal in response to the gate control signal GCS from the timing controller 26. In response to the gate control signal GCS including the first gate signal and the second gate signal input from the timing controller 26, the gate driver 18 may have an odd number of gate lines in the first ½ frame (“A”) period. First gate driving signals are sequentially applied to the gates G1 and G3, and second gate driving signals are sequentially applied to the even-numbered gate lines GL2 and GL4 during the second half frame ("B") period. The TFT 36 connected to the gate lines GL1 to GL4 is turned on.

The data driver 16 converts image data supplied from the timing controller 26 into an analog video signal in response to the data control signal DCS supplied from the timing controller 26 to gate the gate lines GL1 to GL4. The analog video signal corresponding to the line is supplied to the data lines DL1 to DL6 every time the driving signal is supplied. In this case, the data driver 16 may invert the polarity of the analog video signal supplied to the data lines DL1 to DL6 in response to the polarity control signal POL.

In the liquid crystal display according to the second exemplary embodiment of the present invention, a plurality of pixel cells 1R1 to 1B2, 2R1 to 2B2, and 3R1 to 3B2 constituting one horizontal line are divided into two pixel cell groups. The gate lines GL1 to GL4 to which the gate driving signal is applied from the gate driver 18 are driven so that the pixel cell groups are driven with a parallax on one frame, the odd-numbered gate lines GL1 and GL3 and the even-numbered gate lines GL2, The gate driving signal is applied to each of the gate lines GL1 to GL4 divided and divided by GL4.

That is, the period of one frame is divided into two periods "A" and "B" as shown in FIG. 2, and during the period of "A", the odd-numbered gate line GL1 of the gate lines GL1 to GL4 is divided. A gate driving signal is applied to GL3, and a gate driving signal is applied to even-numbered gate lines GL2 and GL4 of the plurality of gate lines GL1 to GL4 during the period “B”.

In more detail, when a gate driving signal is applied to the first gate line GL1 during the first ½ frame (“A”) period of one frame, 1R1, 1G1, and 1B1 connected to the first gate line GL1. The pixel cell is driven. The 1R1 pixel cell receives a data signal from the first data line DL1, the 1G1 pixel cell receives a data signal from the second data line DL2, and the 1B1 pixel cell receives data from the third data line DL3. Receive a signal.

Subsequently, when the gate driving signal is applied to the third gate line GL3, the 3R1, 3G1, 3B1, 2R2, 2G2, and 2B2 pixel cells connected to the third gate line GL3 are driven. The 3R1 pixel cell receives a data signal from the first data line DL1, the 3G1 pixel cell receives a data signal from the second data line DL2, and the 3B1 pixel cell receives a data signal from the third data line DL3. 2R2 pixel cell receives a data signal from a fourth data line DL4, a 2G2 pixel cell receives a data signal from a fifth data line DL5, and a 2B2 pixel cell receives a sixth data line DL6. Data signal is supplied.

As such, the pixel cells 1R1, 1G1, and 1B1 connected to the first gate line GL1 and supplied with the gate driving signal from the first gate line GL1 constitute the unit pixels R, G, and B. Display the input video signal.

In addition, the pixel cells 3R1, 3G1, 3B1 and 2R2, 2G2 and 2B2 connected to the third gate line GL3 and supplied with the gate driving signal from the third gate line G2 are driven as the unit pixels R and G. And B) to display the input video signal.

As shown in FIG. 3A during one frame period, when a " △ " shape image is to be displayed on the liquid crystal panel 10, the liquid crystal display according to the second embodiment of the present invention is the first half of the period of one frame. During the frame “A” period, the pixel cells 1R1, 1G1, 1B1, 3R1, 3G1, 3B1, 2R2, 2G2, connected to the first and third gate lines GL1 and GL3 corresponding to odd-numbered gate lines. 2B2) receives an image signal from data lines connected to each of them, and displays some of the entire images as shown in FIG. 3B.

Subsequently, the second and fourth gate lines GL2 and GL4 corresponding to even-numbered lines among the plurality of gate lines GL1 to GL4 are gated during the second half frame (“B”) period of one frame period. The drive signal is applied sequentially.

When a gate driving signal is applied to the second gate line GL2, 2R1, 2G1, 2B1, 1R2, 1G2, and 1B2 pixel cells connected to the second gate line GL2 are driven. The 2R1 pixel cell receives a data signal from the first data line DL1, the 2G1 pixel cell receives a data signal from the second data line DL2, and the 2B1 pixel cell receives a data signal from the third data line DL3. 1R2 pixel cell receives a data signal from the fourth data line DL4, 1G2 pixel cell receives a data signal from the fifth data line DL5, and 1B2 pixel cell receives a sixth data line DL6. Data signal is supplied.

Subsequently, when a gate driving signal is applied to the fourth gate line GL4, the 3R2, 3G2, and 3B2 pixel cells connected to the fourth gate line GL4 are driven. The 3R2 pixel cell receives a data signal from the fourth data line DL4, the 3G2 pixel cell receives a data signal from the fifth data line DL5, and the 3B2 pixel cell receives a data signal from the sixth data line DL5. Get supplied.

As such, the pixel cells 2R1, 2G1, 2B1, 1R2, 1G2, and 1B2 connected to the second gate line GL2 and supplied with the gate driving signal from the second gate line GL2 are driven as the unit pixel R,. G and B) are configured to display the input video signal.

In addition, the pixel cells 3R2, 3G2, and 3B2 connected to the fourth gate line GL4 and supplied with the gate driving signal from the fourth gate line GL4 form the unit pixels R, G, and B. Display the input video signal.

As shown in FIG. 3A during one frame period, when a " △ " shape image is to be displayed on the liquid crystal panel 10, the liquid crystal display according to the second embodiment of the present invention has a second half of one frame period. During the frame "B" period, the pixel cells 2R1, 2G1, 2B1, 1R2, 1G2, 1B2, 3R2, and 3G2 connected to the second and fourth gate lines GL2 and GL4 corresponding to even-numbered gate lines. , 3B2) receives an image signal from data lines connected to each of them, and displays some of the entire images as shown in Fig. 6C.

The liquid crystal display according to the second exemplary embodiment of the present invention divides a plurality of pixel cells formed on the liquid crystal panel into two pixel cell groups based on a horizontal line, and divides the pixel cell groups divided by the above-described configuration and driving method. It is driven with a time difference of 1/2 frame on one frame. With this configuration and driving method, a portion of the entire image is displayed as shown in Fig. 3B during the first half frame ("A") period, and as shown in Fig. 3C during the second half frame ("B") period. Similarly, after a part of the entire image is displayed, the images displayed in these two half-frame ("A", "B") periods are combined to display a completed image of one frame as shown in FIG. 3A.

In the case where a white box is to be moved to the right by 4 pixels per frame on a black background screen, a conventional LCD driving method is performed by one frame as illustrated in FIG. 6A. After this, the white box moves in units of 4 pixels.

When the screen is driven by the driving method according to the second embodiment of the present invention, as shown in FIG. 6B, one frame is divided into two half frames to display each image on the screen, and the completed one is added to each of the displayed images. The image of the frame is completed. Through such a driving method, the display quality of the liquid crystal display can be improved by reducing the screen drag phenomenon when the video is driven.

Of course, this is one example. In the method of driving the liquid crystal display according to the second embodiment of the present invention, for convenience of description, the period of one frame is divided into two periods ("A", "B") and each period Although " A " and " B "

In addition, for convenience of description, the gate driving signal is applied to the odd-numbered gate line in the "A" period of one frame period to drive the pixel cells connected to the odd-numbered gate line, and the gate to the even-numbered gate line in the "B" period. Although the driving of the pixel cells connected to the even-numbered gate lines by applying a driving signal has been described, in the " A " period, the gate driving signal is applied to the even-numbered gate lines to drive the pixel cells connected to the even-numbered gate lines. It is also possible to drive the pixel cells connected to the odd-numbered gate lines by applying a driving signal to the odd-numbered gate lines in the " B " period.

The liquid crystal display according to the second embodiment of the present invention is configured to display a screen by configuring 60 seconds per second through the above-described configuration and driving method, thereby improving the effective frame frequency of the screen by up to twice the liquid crystal display device. Can improve the display quality.

The liquid crystal display according to the second embodiment of the present invention can reduce the manufacturing cost compared to the conventional liquid crystal display device for displaying a screen by configuring 75 seconds, 90 seconds, 120 frames per second through the above configuration and driving method .

5 is a schematic diagram illustrating a liquid crystal display and a driving method thereof according to a third embodiment of the present invention.

Referring to FIG. 5, in the liquid crystal display according to the third exemplary embodiment, the pixel area 30 is formed for each area defined by the plurality of gate lines GL1 to GL4 and the plurality of data lines DL1 to DL3. ), A gate driver 18 sequentially supplying a gate drive signal to each of the gate lines GL1 to GL4, and data R, G, and B in synchronization with the gate drive signal. The data driver 16 to be supplied to the data lines DL1 to DL3 and the image data R, G, and B from the outside are aligned and supplied to the data driver 16 as well as the data driver 16 and the gate driver. It comprises a timing controller 26 which controls the drive of (18).

The liquid crystal panel 10 includes a transistor array substrate and a color filter array substrate bonded to each other, a spacer for maintaining a constant cell gap between the two array substrates, and a liquid crystal filled in a space provided by the spacer.

The liquid crystal panel 10 includes a TFT 36 formed in a region defined by n gate lines and m data lines, and a liquid crystal cell 32 connected to the TFT 36.

The liquid crystal cell 32 includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the TFT 36, so that the liquid crystal cell 32 may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacity Cst for maintaining the analog video signal charged in the liquid crystal capacitor Clc until the next analog video signal is charged.

The TFT 36 supplies an analog video signal from the data lines DL1 to DL3 to the liquid crystal cell 32 in response to the gate driving signal from the gate lines GL1 to GL4.

The TFT 36 includes a gate electrode connected to the gate lines GL1 to GL4, a source electrode connected to the data lines DL1 to DL3, and a drain electrode connected to the pixel electrode. At this time, each of the TFTs 36 adjacent to the left and right with one data line therebetween is connected to different gate lines GL, and each of these TFTs 36 is connected to the same data line DL.

The timing controller 26 arranges the image data R, G, and B input from the outside so as to be suitable for driving the liquid crystal panel 10, and supplies the image data 16 to the data driver 16. In addition, the timing controller 26 uses the dot clock DLCK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync input from the outside. GCS) is generated to control the driving timing of each of the data driver 16 and the gate driver 18.

The gate control signal GCS generated by the timing controller 26 and controlling the driving timing of the gate driver 18 includes a first gate signal and a second gate signal. The timing controller 26 divides the period of one frame into two periods ("A", "B") each having a half frame period, as shown in FIG. One gate signal is supplied to the gate driver 16, and a second gate signal is supplied to the gate driver 16 in the second half frame ("B") period.

The gate driver 18 includes a shift register that sequentially generates the gate driving signal in response to the gate control signal GCS from the timing controller 26. In response to the gate control signal GCS including the first gate signal and the second gate signal input from the timing controller 26, the gate driver 18 may have an odd number of gate lines in the first ½ frame (“A”) period. First gate driving signals are sequentially applied to the gates G1 and G3, and second gate driving signals are sequentially applied to the even-numbered gate lines GL2 and GL4 during the second half frame ("B") period. The TFT 36 connected to the gate lines GL1 to GL4 is turned on.

The data driver 16 converts image data supplied from the timing controller 26 into an analog video signal in response to the data control signal DCS supplied from the timing controller 26 to gate the gate lines GL1 to GL4. The analog video signal corresponding to the line is supplied to each of the data lines DL1 to DL3 every time the driving signal is supplied. In this case, the data driver 16 may invert the polarity of the analog video signal supplied to the data lines DL1 to DL6 in response to the polarity control signal POL.

In the liquid crystal display according to the third exemplary embodiment of the present invention, the plurality of pixel cells 1R1 to 1B2 and 2R1 to 2B2 constituting one horizontal line are divided into two pixel cell groups. The gate lines GL1 to GL4 to which the gate driving signal is applied from the gate driver 18 are divided into odd-numbered gate lines GL1 and GL3 and even-numbered gate lines GL2 and GL4 so as to be driven with a parallax on one frame. . Thereafter, a gate driving signal is applied to each of the divided gate lines GL1 to GL4.

That is, the period of one frame is divided into two periods "A" and "B" as shown in FIG. 2, and during the period of "A", the odd-numbered gate line GL1 of the gate lines GL1 to GL4 is divided. A gate driving signal is applied to GL3, and a gate driving signal is applied to even-numbered gate lines GL2 and GL4 of the plurality of gate lines GL1 to GL4 during the period “B”.

More specifically, when the gate driving signal is applied to the first gate line GL1 during the first ½ frame (“A”) period of one frame, 1R1, 1B1, The 1G2 pixel cell is driven. The 1R1 pixel cell receives a data signal from the first data line DL1, the 1B1 pixel cell receives a data signal from the second data line DL2, and the 1G2 pixel cell receives a data signal from the third data line DL3. Get supplied.

Subsequently, when a gate driving signal is applied to the third gate line GL3, 2R1, 2B1, and 2G2 pixel cells connected to the third gate line GL3 are driven. The 2R1 pixel cell receives a data signal from the first data line DL1, the 2B1 pixel cell receives a data signal from the second data line DL2, and the 2G2 pixel cell receives data from the third data line DL3. Receive a signal.

As such, the pixel cells 1R1, 1B1, which are connected to the first gate line GL1 and the third gate line GL3 and receive the gate driving signals from the connected gate lines GL1 and GL3, are driven. 1G2 and 2R1, 2B1, and 2G2 constitute unit pixels R, G, and B to display the input video signal.

As shown in FIG. 3A during one frame period, when a " △ " shape image is to be displayed on the liquid crystal panel 10, the liquid crystal display according to the third embodiment of the present invention is the first half of the period of one frame. During the frame "A" period, the pixel cells 1R1, 1B1, 1G2, 2R1, 2B1, and 2G2 connected to the first and third gate lines GL1 and GL3 corresponding to odd-numbered gate lines are connected to each other. A video signal is input from the data line so as to display a part of the entire image as shown in FIG. 6B.

Subsequently, the second and fourth gate lines GL2 and GL4 corresponding to even-numbered lines among the plurality of gate lines GL1 to GL4 are gated during the second half frame (“B”) period of one frame period. The drive signal is applied sequentially.

When the gate driving signal is applied to the second gate line GL2, the pixel cells 1G1, 1R2, and 1B2 connected to the second gate line G1 are driven.

The 1G1 pixel cell receives a data signal from the first data line DL1, the 1R2 pixel cell receives a data signal from the second data line DL2, and the 1B2 pixel cell receives a data signal from the third data line DL3. Get supplied.

Subsequently, when a gate driving signal is applied to the fourth gate line GL4, 2G1, 2R2, and 2B2 pixel cells connected to the fourth gate line GL4 are driven. The 2G1 pixel cell receives a data signal from the first data line DL1, the 2R2 pixel cell receives a data signal from the second data line DL2, and the 2B2 pixel cell receives a data signal from the third data line DL3. Get supplied.

As such, the pixel cells 1G1, 1R2, and 1B2 connected to the second gate line GL2 and supplied with the gate driving signal from the second gate line GL2 may be used to select the unit pixels R, G, and B. And display the input video signal.

In addition, the pixel cells 2G1, 2R2, and 2B2 connected to the fourth gate line GL4 and supplied with the gate driving signal from the fourth gate line GL4 form the unit pixels R, G, and B. Display the input video signal.

As shown in FIG. 3A during one frame period, when a " △ " shape image is to be displayed on the liquid crystal panel 10, the liquid crystal display according to the third embodiment of the present invention has a second half of one frame period. During the frame "B" period, the pixel cells 1G1, 1R2, 1B1, 2G1, 2R2, and 2B2 connected to the second and fourth gate lines GL2 and GL4 corresponding to even-numbered gate lines are respectively provided. A picture signal is input from the connected data line to display a part of the picture as shown in FIG. 6C.

The liquid crystal display according to the third exemplary embodiment of the present invention divides a plurality of pixel cells formed on the liquid crystal panel into two pixel cell groups based on a horizontal line, and divides the pixel cell groups divided by the above-described configuration and driving method. It is driven with a time difference of 1/2 frame on one frame. With this configuration and driving method, a portion of the entire image is displayed as shown in Fig. 3B during the first half frame ("A") period, and as shown in Fig. 3C during the second half frame ("B") period. Similarly, after a part of the entire image is displayed, the images displayed in these two half-frame ("A", "B") periods are combined to display a completed image of one frame as shown in FIG. 3A.

In the case where a white box is to be moved to the right by 4 pixels per frame on a black background screen, a conventional LCD driving method is performed by one frame as illustrated in FIG. 6A. After this, the white box moves in units of 4 pixels.

When the screen is driven by the driving method according to the third embodiment of the present invention, as shown in FIG. 6B, one frame is divided into two half frames to display each image on the screen, and the completed one is added to each of the displayed images. The image of the frame is completed. Through such a driving method, the display quality of the liquid crystal display can be improved by reducing the screen drag phenomenon when the video is driven.

Of course, this is one example. In the method of driving the liquid crystal display according to the third embodiment of the present invention, for convenience of description, the period of one frame is divided into two periods "A" and "B", and each period Although " A " and " B "

In addition, for convenience of description, the gate driving signal is applied to the odd-numbered gate line in the "A" period of one frame period to drive the pixel cells connected to the odd-numbered gate line, and to the even-numbered gate line in the "B" period. The driving of the pixel cells connected to the even-numbered gate lines by applying the gate driving signal is described above. However, the gate driving signal is applied to the even-numbered gate lines in the "A" period to drive the pixel cells connected to the even-numbered gate lines. It is also possible to drive the pixel cells connected to the odd-numbered gate lines by applying a driving signal to the odd-numbered gate lines in the "B " period.

In the liquid crystal display according to the third embodiment of the present invention, the display is configured with 60 frames per second by using the above-described configuration and driving method, thereby improving the effective frame frequency of the screen by up to 2 times. Can improve the display quality. In addition, by using the above-described configuration and driving method, it is possible to reduce the manufacturing cost compared to the conventional liquid crystal display device displaying a screen by configuring one second into 75, 90, 120 frames.

In the liquid crystal display according to the third exemplary embodiment, a data line for supplying a data signal to adjacent pixel cells with a data line interposed therebetween is commonly formed. As a result, manufacturing cost can be reduced by reducing the number of expensive drive ICs mounted in the data driver 16.

As described above, the liquid crystal display and the driving method according to the embodiment of the present invention display the screen by configuring 60 seconds per second to display the screen, thereby improving the effective frame frequency of the screen by up to twice the display of the liquid crystal display device. Can improve the quality.

In the liquid crystal display according to the exemplary embodiment of the present invention, a data line for supplying a data signal to adjacent pixel cells with a data line interposed therebetween is commonly formed, thereby reducing the number of expensive drive ICs mounted in the data driver. You can save money.

In the liquid crystal display according to the embodiment of the present invention, when displaying the screen by configuring 60 seconds per second, the effective frame frequency of the screen is improved by up to 2 times, and the screen is configured by 75, 90, 120 frames per second. It is possible to reduce the manufacturing cost compared to the existing liquid crystal display device displaying a.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (16)

A liquid crystal panel including pixel cells formed at respective regions defined by a plurality of crossing gate lines and a plurality of data lines; The driving circuit unit divides the pixel cell into a first pixel cell group and a second pixel cell group based on a horizontal line, and drives the first pixel cell group and the second pixel cell group with a parallax in one frame period. Liquid crystal display device comprising a. The method of claim 1, And said one frame period comprises a first period and a second period. The method of claim 2, The driving circuit unit and the timing controller, A gate driver for supplying a gate driving signal to an odd or even gate line in the first period or the second period according to a control signal from the timing controller; And a data driver for supplying a data signal to the data line in synchronization with the gate driving signal. The method of claim 1, And a unit pixel composed of three or more adjacent pixel cells on a horizontal line. The method of claim 1, And at least three pixel cells adjacent to each other with the gate line and the data line interposed therebetween. The method of claim 1, And a unit pixel comprising three or more odd-numbered pixel cells or even-numbered pixel cells on a horizontal line. The method of claim 6, And each of the plurality of data lines is commonly connected to adjacent pixel cells. In a driving method of a liquid crystal display device comprising a plurality of data lines perpendicular to each other and a plurality of gate lines composed of a first gate line group and a second gate line group, A plurality of pixel cells constituting a unit pixel are divided into a first pixel cell group and a second pixel cell group based on a horizontal line, and the first pixel cell group and the second pixel cell group are separated in one frame period. And driving the liquid crystal display device. The method of claim 8, In the driving of the first pixel cell group and the second pixel cell group with a parallax in one frame period, the one frame period is composed of a first period and a second period of the liquid crystal display Method of driving the device. Ninth, In supplying the gate driving signal in the first period, the gate driving signal is applied to the first gate line group or the second gate line group in the first period so that the first pixel cell group or the second pixel cell group is applied. And driving the liquid crystal display device. The method of claim 10, In the supply of the gate driving signal in the second period, the gate driving signal is applied to a gate line group other than the gate line group to which the driving signal is applied in the first period, thereby excluding the pixel cell group driven in the first period. And driving the pixel cell group. The method of claim 10 or 11, And the first period and the second period are the same time in the first and second periods. The method according to claim 10 or 11, wherein And the time period between the first period and the second period is not the same in the first period and the second period. The method of claim 8, A driving method of a liquid crystal display device, comprising unit pixels consisting of adjacent pixel cells on a horizontal line. The method of claim 8, And a unit pixel is formed of adjacent pixel cells with the gate line and the data line interposed therebetween. The method of claim 8, A method of driving a liquid crystal display device comprising unit pixels consisting of odd-numbered pixel cells or even-numbered pixel cells on a horizontal line.

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