KR20080066414A - Display panel - Google Patents

Abstract

A display panel is provided to define an up capacitor by crossing a prolongation unit and a protrusion pattern, thereby reducing a process error of a manufacturing process and designing the up capacitor more stably. A substrate has plural gate lines(GLn,GLn+1) and plural data lines(DLm-1,DLm,DLm+1). The data lines define plural pixel areas by crossing the gate lines. The pixel area comprises a main pixel area and a sub pixel area adjacent to the main pixel area. A first TFT(Thin Film Transistor)(T1) is formed on the substrate, and is connected to a current gate line and a current data line. A second TFT(T2) is formed on the substrate, and is connected to the current gate line and the current data line. A main pixel electrode(MP) is installed in the main pixel area, and electrically connected to a drain electrode(DE1) of the first TFT. In the main pixel electrode, a protrusion pattern is formed in an end portion adjacent to the next gate line. A sub pixel electrode(SP) is installed in the sub pixel area, and is electrically insulated form the main pixel electrode. The sub pixel electrode is electrically connected to a drain electrode(DE2) of the second TFT. A third TFT(T3) comprises a gate electrode branched from the next gate line, a first electrode(E1) electrically connected to the sub pixel electrode, and a second electrode(E2) crossing the protrusion pattern of the main pixel electrode.

Description

Display panel {DISPLAY PANEL}

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is an equivalent circuit diagram of an m × n pixel of a display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a layout of m × n pixels shown in FIG. 1.

3 is an enlarged view of a portion A of FIG. 2 and illustrates an intersecting structure between the protrusion pattern and the extension part, according to another exemplary embodiment.

FIG. 4 is an enlarged view of a portion A of FIG. 2 and illustrates an intersecting structure between the protrusion pattern and the extension part, according to another exemplary embodiment.

FIG. 5 is an enlarged view of a portion A of FIG. 2 and illustrates an intersecting structure between the protrusion pattern and the extension part, according to another exemplary embodiment.

The present invention relates to a display panel, and more particularly, to a display device capable of improving display quality.

In general, a liquid crystal display includes a lower substrate, an upper substrate provided to face the lower substrate, and a liquid crystal layer formed between the lower substrate and the upper substrate to display an image. The LCD panel includes a plurality of gate lines, a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines.

Recently, in order to improve a narrow viewing angle of a liquid crystal display, a patterned vertical alignment (PVA) mode, a multi-domain vertical alignment (MVA) mode, and a super-patterned vertical alignment (S) are used. PVA mode liquid crystal display devices have been developed.

The S-PVA mode liquid crystal display includes a pixel composed of two subpixels, and in order to form a domain having different grays in the pixels, the two subpixels respectively include main and subpixel electrodes to which different subvoltages are applied. Equipped. At this time, the eye of the person looking at the liquid crystal display recognizes the median value of the two sub-voltages, thereby preventing the gamma curve from being distorted below the mid-level gray level and thus reducing the side viewing angle. Thereby, side visibility of the liquid crystal display device can be improved.

S-PVA mode LCDs are classified into a coupling capacitor (CC) type and a two transistor (TT) type according to a driving method. The CC-type is a driving method in which a coupling capacitor is added between the main pixel electrode and the sub pixel electrode to drop the data voltage applied to the sub pixel electrode to apply a voltage lower than the main pixel voltage as the sub pixel voltage.

However, due to the misalignment due to the process error, the coupling capacitor cannot be formed normally. In addition, the area occupied by the coupling capacitor is very small by the pixel electrode occupying most of one pixel region. Therefore, there is a limit in increasing the total capacity of the coupling capacitor. This is a major cause of lowering the display quality of the display panel.

Accordingly, an object of the present invention is to provide a display panel for improving display quality.

The display panel of the present invention for achieving the above technical problem includes a substrate, a first thin film transistor, a second thin film transistor, a main pixel electrode, a sub pixel electrode and a third thin film transistor. The substrate includes a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines. A plurality of pixel areas is defined by the plurality of gate lines and the plurality of data lines. Each of the plurality of pixel areas includes a main pixel area and a sub pixel area. The first thin film transistor is connected to a current gate line and a current data line. The second thin film transistor is connected to the current gate line and the current data line. The main pixel electrode is provided in the main pixel region and is electrically connected to the drain electrode of the first thin film transistor. Here, a protrusion pattern is formed at an end of the main pixel electrode. The sub pixel electrode is provided in the sub pixel area, is electrically connected to the main pixel electrode, and is electrically connected to a drain electrode of the second thin film transistor. The third thin film transistor includes a gate electrode branched from the next gate line, a first electrode electrically connected to the sub pixel electrode, and a second electrode crossing the protrusion pattern of the main pixel electrode.

According to the present invention, the display panel of the present invention has an extension portion extending from the second electrode of the third thin film transistor and a projection pattern extending from the main pixel electrode to have an uneven shape.

In addition, by appropriately adjusting the number of the projection pattern and the extension portion, by increasing the number of the cross-sectional area formed by the cross structure, it is possible to increase the capacitance of the up capacitor.

In addition, it is possible to increase the capacitance of the up capacitor by increasing the width over the length of the extension.

As a result, the display panel according to the present invention provides improved display quality.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings. In understanding the drawings, it should be noted that like parts are intended to be represented by the same reference numerals as much as possible. In addition, in the following description, numerous specific details, such as specific processing flows, are described to provide a more general understanding of the invention. Incidentally, detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an equivalent circuit diagram of m × n pixels of a display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an n × m pixel includes an nth gate line GLn, an mth data line DLm, and first to third thin film transistors T1, T2, and T3. The first thin film transistor T1 is electrically connected to the nth gate line GLn and the mth data line DLm. Specifically, the gate electrode GE1 of the first thin film transistor T1 is electrically connected to the nth gate line GLn, and the source electrode SE1 is electrically connected to the mth data line DLm. do. In addition, the thin film transistor T1 includes a first drain electrode DE1.

The second thin film transistor T2 is electrically connected to the nth gate line GLn and the mth data line DLm. Specifically, the gate electrode GE2 of the second thin film transistor T2 is electrically connected to the nth gate line GLn, and the source electrode SE2 is electrically connected to the mth data line DLm. do. In addition, the thin film transistor T1 includes a second drain electrode DE2.

The third thin film transistor T3 is electrically connected to the n + 1 th gate line GLn and the first and second drain electrodes DE1 and DE2. In detail, the gate electrode GE3 of the third thin film transistor T3 is electrically connected to the n + 1th gate line GLn + 1 and the second electrode E1 of the third thin film transistor T3. Is connected to the capacitor C_up described below, and the first electrode E2 of the third thin film transistor T3 is connected to the drain electrode DE2 of the second thin film transistor T2. Description of this will be described in detail below.

In addition, the n × m pixel further includes a main pixel and a sub pixel, and the main pixel is connected to the first drain electrode DE1 of the first thin film transistor T1, and the sub pixel is connected to the second thin film. It is connected to the second drain electrode DE2 of the transistor T2.

The main pixel includes a first storage capacitor H_cst and a first liquid crystal capacitor H_clc. The first storage capacitor H_cst is formed by a storage electrode, an insulating layer, and a main pixel electrode. The first liquid crystal capacitor H_clc is formed by the main pixel electrode, the liquid crystal layer, and the common electrode.

The subpixel includes a second storage capacitor L_cst and a second liquid crystal capacitor L_clc. The second storage capacitor L_cst is formed by a storage electrode, an insulating layer, and a sub pixel electrode. The second liquid crystal capacitor L_clc is formed of a sub pixel electrode, a liquid crystal layer, and a common electrode.

The n × m pixel further includes an up capacitor C_up for raising the potential of the main pixel electrode and a second capacitor C_down for decreasing the potential of the sub pixel electrode. The up capacitor C_up is formed by the main pixel electrode, the first electrode E1, and the insulating layer. The down capacitor C_down is formed by the second electrode E2, the insulating layer, and the storage electrode. As a result, the second electrode E2 of the third thin film transistor T3 is electrically connected to the main pixel electrode through the up capacitor C_up.

When the n-th gate signal is applied to the n-th gate line GLn, the first and second thin film transistors T1 and T2 are turned on. Therefore, the data voltage applied to the m-th data line DLm passes through the first and second thin film transistors T1 and T2 and the main pixel electrodes of the first and second liquid crystal capacitors H_clc and L_clc. And a sub pixel electrode. Here, since the data voltages applied to the main pixel electrode and the sub pixel electrode are the same, the same voltage is charged in the first and second liquid crystal capacitors H_clc and L_clc. That is, when the voltages charged in the first and second liquid crystal capacitors H_clc and L_Clc are defined as first and second pixel voltages, the first and second pixel voltages are the same voltage during the nth horizontal scanning interval. Have a level.

When the third thin film transistor T3 is turned on in response to an nth gate signal applied to the nth gate line GLn, the third thin film transistor T3 and the up capacitor C_up are electrically connected to each other. Connected. Therefore, the voltage level of the first pixel voltage charged in the first liquid crystal capacitor H-Clc and the second pixel voltage charged in the second liquid crystal capacitor L_clc is equal to the up capacitor C-up. It is controlled by the down capacitor (C-down).

Specifically, the voltage level of the first pixel voltage increases and the voltage level of the second pixel voltage decreases by the up capacitor C-up1 and the down capacitor C-down1. In this case, the rising width of the first pixel voltage and the falling width of the second pixel voltage change according to a ratio of capacitances of the up capacitor C_up and the down capacitor C_down.

Therefore, when different voltages are applied to the first and second liquid crystal capacitors H_clc and L_clc, the alignment angles of the liquid crystal molecules included in the liquid crystal layer are changed. As a result, the main pixel and the sub pixel including the first and second liquid crystal capacitors display different gray levels. A user who uses the display device recognizes by mixing two images displayed in the main pixel and the sub pixel. Therefore, the side visibility of the display device can be improved.

FIG. 2 is a layout of m × n pixels shown in FIG. 1, and a black matrix and color pixels are omitted for simplicity of the drawing.

2, a display panel according to the present invention includes a first display substrate (not shown), a second display substrate facing the first display substrate (not shown), and the first display substrate 110 and the first display substrate. It consists of a liquid crystal layer (not shown) interposed between the two display substrates 120.

The first display substrate includes a base substrate (not shown), an m-th data line and an n-th gate line GLn, first and second thin film transistors, a main pixel electrode, a sub pixel electrode, and a third thin film transistor.

An n-th gate line GLn and a storage line STL made of a gate metal are provided on the base substrate. A common voltage is applied to the storage line STL, and a gate signal is applied to the nth gate line GLn.

The third gate branched from the first and second gate electrodes GE1 and GE2 and the n + 1 gate line GLn + 1 branched from the nth gate line GLn on the base substrate. The electrode GE3 is further provided.

A gate insulating layer covering the n-th gate line GLn and the storage line STL is further provided on the base substrate 111. On the gate insulating layer 112, an m-th data line DLm, first and second source electrodes SE1 and SE2 branched from the m-th data line DLm, and the first and second source electrodes SE1, First and second drain electrodes DE1 and DE2 are respectively spaced apart from SE2.

As a result, a first thin film transistor T1 including the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1 is formed on the base substrate. The second thin film transistor T2 including the second gate electrode GE2, the second source electrode SE2, and the second drain electrode DE2 is formed.

In addition, the gate insulating layer further includes a first electrode E1 and a second electrode E2 spaced apart from each other at a predetermined interval at a position corresponding to the third gate electrode GE3. Accordingly, the third thin film transistor T4 including the third gate electrode GE3, the first electrode E1, and the second electrode E2 is formed on the array substrate 110.

A down capacitor C_down is formed at a portion where the second electrode E2 and the storage line STL partially overlap the gate insulating layer. In addition, an extension part extending from the second electrode is formed on the gate insulating film. The extension forms one electrode of the up capacitor C_up described below.

The base substrate includes the first, second and third thin film transistors T1, T2, and T3, a passivation layer (not shown) and an organic insulating layer (not shown) covering the second electrode E2. The protective layer and the organic insulating layer have a first contact hole C1 exposing the first drain electrode DE1, a second contact hole C2 exposing the second drain electrode DE2, and a first electrode E1. The third contact hole C3 exposing the gap is formed.

The main pixel electrode MP and the sub pixel electrode SP are formed on the organic insulating layer. An opening OP is formed between the main pixel electrode MP and the sub pixel electrode SP, and is electrically separated from each other by the opening OP.

The main pixel electrode MP is electrically connected to the first drain electrode DE1 through the first contact hole C1, and the second sub pixel electrode SP is connected to the second contact hole C2. The second drain electrode DE2 is electrically connected to the second drain electrode DE2 through the second drain electrode DE2.

The main pixel electrode MP partially overlaps the storage line STL to form a first storage capacitor H-Cst, and the sub pixel electrode SP partially overlaps the storage line STL. To form a second storage capacitor L-Cst. In addition, the sub pixel electrode SP is electrically connected to the first electrode E1 through the third contact hole C3.

The main pixel electrode MP has at least one protrusion pattern having an uneven shape at an end adjacent to the n + 1th gate line GLn + 1. The protrusion pattern intersects an extension portion extending from the second electrode. The extension part is formed to intersect the at least one protrusion pattern. An up capacitor C_up is formed at an intersection of the protrusion pattern and the extension part. The protrusion pattern and the extension part are formed to completely cross. By doing so, it is possible to sufficiently secure a margin for the deviation of the misalignment between the protrusion pattern and the extension part that may occur in the manufacturing process.

As described above, as the rising width of the first pixel voltage provided to the main pixel electrode and the falling width of the second pixel voltage provided to the sub pixel electrode become larger, the visibility of the display device is improved. In other words, as the capacitance of the up capacitor C_up increases, the rising width of the first pixel voltage increases.

Hereinafter, various embodiments that can increase the capacitance of the up capacitor C_up are described.

3 to 5 are enlarged views of portion A of FIG. 2, and show various structures capable of increasing capacitance of the up capacitor C_up.

Referring to FIG. 3, two projection patterns extending from the main pixel electrode MP are formed. An extension part extending from the second electrode E2 intersects the two protrusion patterns. By doing so, two intersection regions between the protrusion pattern and the extension part are secured, thereby increasing the capacitance of the up capacitor C_up. Here, it is apparent that by forming three or more protrusion patterns, more cross sections between the protrusion patterns and the extension part may be formed.

Referring to FIG. 4, the number of protrusion patterns extending from the main pixel electrode MP is the same as the embodiment of FIG. 3. However, there is a difference in the number of extension portions extending from the second electrode. Therefore, if the two extension portions and the two projection patterns are formed to intersect, a total of four intersection regions are provided. By doing so, it is possible to increase the capacitance of the up capacitor C_up further improved in the embodiment of FIG. 3.

Referring to FIG. 5, the structure is substantially similar to the embodiment of FIG. 3. However, the width W2 of the extension shown in FIG. 5 is formed to be wider than the width W1 of the extension shown in FIG. 3. By doing this, it is possible to increase the capacitance of the up capacitor C_up.

Although not shown in the drawings, the second display substrate includes a second base substrate, a black matrix, and a common electrode. The black matrix is provided to correspond to an ineffective display area of the second base substrate, and the common electrode is provided on the black matrix and the second base substrate. An opening for dividing the main pixel electrode MP and the sub pixel electrode SP into one or more domains may be formed in the common electrode.

The liquid crystal layer is interposed between the first display substrate and the second display substrate. Therefore, a first liquid crystal capacitor H_clc is formed by the common electrode, the main pixel electrode MP, and the liquid crystal layer. A second liquid crystal capacitor L_clc is formed by the common electrode, the second sub pixel electrode SP, and the liquid crystal layer.

As described above, the display panel of the present invention has an extension portion extending from the second electrode of the third thin film transistor and a projection pattern extending from the main pixel electrode to have an uneven shape.

The extension portion and the protrusion pattern are intersected to define an up capacitor. Therefore, by reducing the process error in the manufacturing process, it is possible to design a more stable up capacitor.

In addition, by appropriately adjusting the number of the projection pattern and the extension portion, by increasing the number of the cross-sectional area formed by the cross structure, it is possible to increase the capacitance of the up capacitor.

 In addition, it is possible to increase the capacitance of the up capacitor by increasing the width over the length of the extension.

As a result, the display panel according to the present invention provides improved display quality.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (7)

A substrate having a plurality of data lines crossing the plurality of gate lines and the plurality of gate lines and defining a plurality of pixel regions each consisting of a main pixel region and a sub pixel region adjacent to the main pixel region; A first thin film transistor formed on the substrate and connected to a current gate line and a current data line; A second thin film transistor formed on the substrate and connected to the current gate line and the current data line; A main pixel electrode provided in the main pixel region, electrically connected to the drain electrode of the first thin film transistor, and having a protrusion pattern formed at an end adjacent to a next gate line; A sub pixel electrode disposed in the sub pixel area, electrically insulated from the main pixel electrode, and electrically connected to a drain electrode of the second thin film transistor; And And a third thin film transistor including a gate electrode branched from the next gate line, a first electrode electrically connected to the sub pixel electrode, and a second electrode crossing the protrusion pattern of the main pixel electrode. . The method of claim 1, An insulating film provided between the main pixel electrode and the second electrode; And the second electrode includes an electrode portion overlapping with the next gate line and an extension portion extending from the electrode portion and intersecting the protrusion pattern with the insulating layer therebetween to define a capacitor. The method of claim 2, wherein the projection pattern is made of one projection, And the extension portion intersects with the one projection. The method of claim 2, wherein the projection pattern is composed of a plurality of projections spaced apart from each other, And the extension part intersects at least two of the protrusions. The display device of claim 1, further comprising an insulating film provided between the main pixel electrode and the second electrode. The protrusion pattern is composed of a plurality of protrusions spaced apart from each other, The second electrode includes an electrode portion overlapping the next gate line and a plurality of extension portions extending from the electrode portion. And each of the plurality of extension portions intersects the plurality of protrusions with the insulating layer therebetween. The display panel of claim 5, wherein the protrusions intersecting the extension part of the plurality of protrusions have a length longer than the length of the remaining protrusions. The display panel of claim 1, wherein the protrusion pattern has an uneven shape.

Images