KR20080064524A - Common voltage generator and liquid crystal display - Google Patents

Abstract

A common voltage generator and a liquid crystal display device are provided to reduce an error rate of the common voltage generator by simplifying a configuration of the common voltage generator. A common voltage generator includes a DAC(Digital to Analog Converter)(174) and a memory(173). The DAC calibrates a level of a common voltage according to a first control signal, which is received from an external common voltage regulator. The memory stores a second control signal, which is received from the common voltage regulator corresponding to the calibrated common voltage. A voltage divider(176) divides an analog source voltage. A first comparator(175) includes a non-inverted terminal which is connected to an output terminal of the DAC, and includes an inverted terminal which is connected to a reset resistor. The reset resistor determines a minimum value for the common voltage. A second comparator(177) includes a non-inverted terminal which is connected to a dividing node, and includes an inverted terminal which is connected to an output terminal for outputting the common voltage. A MOS(Metal Oxide Semiconductor) transistor includes a gate which is connected to the output of the first comparator, and includes a source which is connected to a reset resistor, and includes a drain which is connected to the dividing node.

Description

Common Voltage Generator and Liquid Crystal Display {COMMON VOLTAGE GENERATOR AND LIQUID CRYSTAL DISPLAY}

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention; and

FIG. 2 is a diagram illustrating a common voltage generator and an external common voltage regulator shown in FIG. 1.

<Code Description of Main Parts of Drawing>

100: liquid crystal display 110: liquid crystal panel

120: data driver 130: gate driver

140: gamma voltage generator 150: timing controller

160: power supply unit 170: common voltage generation unit

The present invention relates to a common voltage generator and a liquid crystal display, and more particularly, to a common voltage generator used in a liquid crystal display.

In general, a liquid crystal display device is formed by arranging a thin film transistor substrate and a color filter substrate each having a pixel electrode and a common electrode facing each other, and injecting a liquid crystal between the two substrates, and then applying a voltage to the electrode. By moving the liquid crystal by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

The transmittance of light by the liquid crystal is irrelevant to the applied polarity and is proportional to the applied voltage. Also, when the direct current operation of the liquid crystal cell is performed for a long time, a polarization phenomenon occurs in the liquid crystal molecules. .

In order to operate the liquid crystal display by alternating current, the common electrode of the color filter substrate should be grounded and an alternating voltage of positive and negative voltages should be applied to the pixel electrode of the thin film transistor substrate. However, since it is difficult to output an alternating voltage from the data driver as a data voltage, the liquid crystal display device is alternated by fixing the common voltage to a constant positive voltage and swinging the output of the data driver to a positive voltage higher or lower than the common voltage every frame. Operate.

Conventionally, in order to fix the common voltage to a constant positive voltage, a DVR (Digital Variable Resistor) method is used. Here, the DVR generates a common voltage (VCOM) that holds the center of the common electrode, and stores the common voltage (VCOM) that shows the optimal flicker through the variable voltage at the time of initial shipment to the internal memory and uses it when necessary. Refers to an integrated circuit.

However, in order to prevent the malfunction of the DVR by the customer, the pins corresponding to the control terminal (CTL) and the control interface enable terminal (CE) are opened to block the common voltage control function before shipping.

Therefore, there is a problem that the common voltage generator of the conventional liquid crystal display includes a voltage control element, a pin, a cable, and the like, which are not used by a customer.

Accordingly, an object of the present invention is to provide a common voltage generating device and a liquid crystal display device in which voltage control elements which are not used after being mounted in a liquid crystal display device are separated.

In order to achieve the above object, the common voltage generating device of the present invention includes: a digital analog converter for calibrating a level of a common voltage according to a first control signal provided from an external common voltage adjusting device; And a memory corresponding to the calibrated common voltage and storing a second control signal provided from the common voltage adjusting device, wherein the digital to analog converter fixes the common voltage level according to the second control signal. It is preferable.

The common voltage generator of the present invention includes: a voltage divider for dividing and distributing an analog power voltage through a voltage divider node; A first comparator having a non-inverting terminal connected to an output terminal of the digital analog converter, and a reversing terminal connected to a reset resistor for determining a minimum value of the common voltage; A second comparator having a non-inverting terminal connected to the voltage dividing node and an inverting terminal connected to an output terminal for outputting the common voltage; And a MOS transistor having a gate connected to the output of the first comparator, a source connected to the reset resistor, and a drain connected to the voltage divider node.

Here, the memory is preferably EEPROM in which the second control signal can be programmed repeatedly.

In addition, the digital analog converter, the memory, the first comparator, and the MOS transistor are preferably integrated into a digital variable resistance integrated circuit.

The common voltage regulator may include a first terminal to which a power supply voltage is supplied, a second terminal to which the power supply voltage is supplied as an enable signal, a third terminal to which the first control signal is applied, and the enable signal. And a control interface that is enabled to provide the first control signal to the digital analog converter.

The common voltage regulator may include a first terminal to which a power supply voltage is supplied, a second terminal to which the power supply voltage is supplied as an enable signal, a third terminal to which the second control signal is applied, and the enable signal. And a control interface that is enabled to provide the second control signal to the memory.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a common voltage generator configured to store a control signal corresponding to a common voltage calibrated through an external common voltage adjusting device and to fix and output a level of the common voltage in response to the control signal; A gamma voltage generator for generating a gamma voltage by dividing the analog power voltage; A data driver to output a gray scale display voltage using the gamma voltage; And a liquid crystal panel displaying an image in response to the common voltage and the gray scale display voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention. As shown in FIG. 1, the liquid crystal display device 100 according to an exemplary embodiment may include a liquid crystal panel 110, a data driver 120, a gate driver 130, a gamma voltage generator 140, and a timing. The controller 150 includes a power supply unit 160 and a common voltage generator 170.

The liquid crystal panel 110 includes a color filter substrate having a color filter, a thin film transistor substrate having a thin film transistor, and a liquid crystal filled between the color filter substrate and the thin film transistor substrate.

The thin film transistor substrate includes a pixel capacitor ClC and a gate-on voltage VON to which a gray scale display voltage is applied at the intersection of the gate lines GL1,..., GLn and the data lines DL1 .., DLm. The thin film transistor TFT for applying the gray scale display voltage to the pixel capacitor ClC, the common voltage line 112 for applying the common voltage VCOM to the pixel capacitor CLC, and the pixel capacitor CLC. And an accumulation capacitor (not shown) that maintains the gradation display voltage for one frame. The gray scale display voltage is a voltage corresponding to the data DATA.

The thin film transistor TFT may include a gate connected to the gate lines GL1 through GLn, a source connected to the data lines DL1 through DLm, and a drain connected to the pixel electrode of the pixel capacitor ClC. It includes.

The liquid crystal rotates in response to an electric field formed between the common electrode of the pixel capacitor CLC to which the common voltage VCOM is applied and the pixel electrode of the pixel capacitor CLC to which the gray display voltage is applied, thereby corresponding to data corresponding to the gray scale display voltage. (DATA) is displayed.

The data driver 120 generates the gray scale display voltage corresponding to the data DATA using the gamma voltage VGMA, and applies the gray scale display voltage to the thin film transistor TFT driven by the gate-on voltage VON. To display data DATA in units of gate lines GL1, ..., GLn.

To this end, the data driver 120 receives the data control signal DCS and the data DATA from the timing controller 150, and receives the gamma voltage VGMA from the gamma voltage generator 140. The data control signal DCS includes a data start pulse STH, a data synchronization clock CPH, and a load signal TP.

The gate driver 130 sequentially applies the gate-on voltage VON to the plurality of gate lines GL1,..., GLn, and applies the gate-off voltage to the gate line to which the gate-on voltage VON is not applied. VOFF). That is, the gate driver 130 simultaneously turns on the plurality of thin film transistors TFT connected to the gate lines GL1,..., GLn sequentially selected.

To this end, the gate driver 130 receives a gate control signal GCS from the timing controller 150, and receives a gate on voltage VON and a gate off voltage VOFF from the power supply 160. The gate control signal GCS includes a gate start pulse STV and a gate synchronous clock CPV.

The gamma voltage generator 140 generates a gamma voltage VGMA by dividing the analog power voltage AVDD supplied from the power supply unit 160 and supplies it to the data driver 120.

The timing controller 150 converts the RGB data R, G, and B input from the outside into data DATA that the data driver 120 can process and supplies the data to the data driver 120. In addition, the timing controller 150 uses the synchronization signals VSYNC and HSYNC and the synchronization clock MCLK, which are input from the outside, to control signals GCS and DCS necessary for the operation of the data driver 120 and the gate driver 130. Is generated and supplied to each of the data driver 120 and the gate driver 130.

The power supply unit 160 receives a power supply voltage VDD to generate a gate-on voltage VON, a gate-off voltage VOFF, and an analog power voltage VADD to generate a gate driver 130 and a gamma voltage generator 140. ). In addition, the power supply unit 160 supplies the analog power voltage AVDD to the common voltage generator.

The common voltage generator 170 receives the analog power voltage AVDD from the power supply 160, generates a common voltage VCOM, and supplies the generated common voltage VCOM to the liquid crystal panel 110. The common voltage VCOM is preferably a voltage showing an optimal flicker level through the variable voltage at the time of shipment.

In the liquid crystal display according to the exemplary embodiment of the present invention, since the common voltage generator 170 has a configuration in which the common voltage VCOM is programmed and adjusted by an external common voltage regulating device, it is possible to provide a conventional customer. It does not include a voltage control element (Control Interface), a pin (Pin), a cable (Cable) and the like that are not used by.

The configuration and operation of the common voltage generator 170 and the external common voltage regulator of the liquid crystal display according to the exemplary embodiment of the present invention will be described in more detail with reference to FIG. 2.

FIG. 2 is a diagram illustrating a common voltage generator and an external common voltage regulator shown in FIG. 1. As shown in FIG. 2, the common voltage generator 170 may include a digital analog converter 174, a memory 173, a first comparator 175, a MOS transistor NT, a voltage divider 176, and a second comparator. (177).

The digital-to-analog converter 174 controls the sink current Iout with a control signal CTLsig to increase or decrease the level of the common voltage VCOM to calibrate. Here, the control signal CTLsig is a digital pulse signal provided from the external common voltage regulator 200 and may be, for example, a 7-bit digital pulse swinging around VDD / 2. The digital analog converter 174 may convert the calibrated control signal at a ratio proportional to the analog power supply voltage AVDD to fix the level of the common voltage VCOM under all operating conditions.

The memory 173 stores a calibrated control signal CTLsig that can fix the level of the common voltage VCOM. Here, the calibrated control signal CTLsig may be selected through the external common voltage regulator 200 at initial shipment, and maintains the common voltage VCOM level showing the optimal flicker level. The memory 173 is preferably an EEPROM (Electrically Erasable and Programmable Read Only Memory) capable of repeatedly programming the calibrated control signal CTLsig.

The first comparator 175 compares the output voltage of the digital-to-analog converter 174 provided to the non-inverting terminal (+) with the voltage applied to the reset resistor Rset provided to the inverting terminal (-). To serve as a gate. The reset resistor Rset sets the full-scale sink current that determines the minimum value of the common voltage VCOM.

The MOS transistor NT adjusts the sink current Iout according to the turn-on degree corresponding to the output of the first comparator 175 and provides the MOS transistor NT to the distribution node DN of the voltage divider 176.

The voltage divider 176 is a component that sets the maximum value of the common voltage, and includes a first resistor R1 and a second resistor R2 connected in series between the analog power supply voltage AVDD and a ground terminal. It includes. The connection node of the first resistor R1 and the second resistor R2 becomes the distribution node DN.

The second comparator 177 compares the voltage applied to the distribution node DN provided to the non-inverting terminal (+) with the output voltage fed back to the inverting terminal (−) to provide a common voltage (VCOM).

The digital-to-analog converter 174, the memory 173, the first comparator 175, and the MOS transistor NT may be implemented as an integrated digital variable resistance integrated circuit 172. In the digital variable resistance integrated circuit 172, the AVDD terminal is a terminal for inputting an analog power supply voltage (AVDD), the OUT terminal is a terminal for outputting an adjustable sink current, and the SET terminal is a full scale ( Full scale) sink current control terminal. In addition, the IN1 terminal is a terminal corresponding to the OUT1 terminal of the external common voltage regulator 200, the IN2 terminal is a terminal corresponding to the OUT2 terminal of the external common voltage regulator 200, and the IN3 terminal is an external common voltage regulator This is a terminal corresponding to the OUT3 terminal of 200.

On the other hand, the external common voltage regulator 200 is attached to a shipment inspection device (not shown) to adjust and program the common voltage VCOM at the time of initial shipment. To this end, the external common voltage regulator 200 controls a VDD terminal to which a power supply voltage VDD is supplied, a CE terminal to enable the control interface 210, a common voltage VCOM, and programs the memory 173. CTL terminal provided with signal CTLsig, OUT1 terminal corresponding to input terminal IN1 of digital variable resistance integrated circuit 172, OUT2 terminal corresponding to IN2 terminal of digital variable resistance integrated circuit 172, digital variable resistor The control interface 210 is connected to the OUT3 terminal corresponding to the IN3 terminal of the integrated circuit 172 and all terminals (VDD terminal, CE terminal, CTL terminal, OUT1 terminal, OUT2 terminal, OUT3 terminal).

The OUT1 terminal, OUT2 terminal, and OUT3 terminal of the external common voltage regulator 200 may be electrically connected to the IN1 terminal, the IN2 terminal, and the IN3 terminal of the digital variable resistance integrated circuit 172 through a cable. The OUT1 terminal, the OUT2 terminal of the external common voltage regulator 200, and the IN1 terminal and the IN2 terminal of the digital variable resistance integrated circuit 172 are connector cables 202 having a line corresponding to the control signal bits, for example, 7 bits. It is preferred that the cable be capable of transmitting data on the line.

Next, an operation of adjusting the common voltage VCOM of the common voltage unit 170 through the external common voltage adjusting device 200 will be described. In this case, the VDD terminal and the CE terminal of the external common voltage regulator 200 may be connected to each other to enable the control interface 210.

The control interface 210 of the external common voltage regulator 200 provides a control signal CTLsig provided from the outside through the CTL terminal to the digital-to-analog converter 174 through the connector cable 202.

If the control signal CTLsig remains at the "low" level for more than a certain time, the digital-to-analog converter 174 increases the sink current and thus the common voltage VCOM level decreases. If the control signal CTLsig remains at the "high" level for more than a certain time, the digital-to-analog converter 174 reduces the sink current and thus increases the common voltage VCOM level. Here, the predetermined time may be, for example, 200 μs.

Next, a programming operation of the memory through the external common voltage regulator 200 will be described. In this case, the VDD terminal and the CE terminal of the external common voltage regulator 200 may be connected to each other to enable the control interface 210.

The control interface 210 of the external common voltage regulator 200 provides a control signal CTLsig provided from the outside through the CTL terminal to the memory 174 through the connector cable 202.

The control signal CTLsig for memory programming has a ramp waveform connecting the voltage level Vpp for programming from the VDD / 2 level for the first period, and the voltage level Vpp for programming during the second period. Keep it. The common voltage regulation operation is stopped during the first period, and the memory 173 cell is biased in preparation for programming. The setting value of the digital analog converter 174 is stored in the memory 173 during the second interval. Here, the first section may be 7.5ms and the second section may be 1ms. It is desirable to maintain the ground level at least 200μs after programming.

The common voltage generator according to an embodiment of the present invention may output the calibrated common voltage through the above-described configuration and operation process, and information about the calibrated common voltage may be stored in a memory. The common voltage regulator is separated from the common voltage generator and used as a component of the liquid crystal display.

Accordingly, the common voltage generator according to the exemplary embodiment of the present invention has a configuration that does not include a common voltage regulating device which is not used after being mounted in the liquid crystal display unlike the conventional art. That is, the common voltage generation unit according to an embodiment of the present invention has an advantage in that the device configuration is simplified compared to the prior art, thereby reducing the defect rate according to a plurality of devices, and eliminating unnecessary elements, terminals, and cables, thereby reducing manufacturing costs.

Since the common voltage generator and the liquid crystal display of the present invention have a structure capable of performing common voltage adjustment and programming at the time of shipment by separating a voltage regulating element which is not used after being mounted in the liquid crystal display into an external device, The device configuration is simplified compared to the conventional common voltage generator, thereby reducing the defect rate according to a plurality of devices, and eliminating unnecessary elements, terminals, and cables, thereby reducing manufacturing costs.

In the detailed description of the present invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the spirit and scope of the art.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A digital analog converter for calibrating the level of the common voltage according to a first control signal provided from an external common voltage regulating device; And And a memory corresponding to the calibrated common voltage and storing a second control signal provided from the common voltage adjusting device. The digital-to-analog converter fixes and outputs the level of the common voltage according to the second control signal. Common voltage generator. The method of claim 1, A voltage divider for dividing and distributing the analog power voltage through the voltage dividing node; A first comparator having a non-inverting terminal connected to an output terminal of the digital analog converter, and an inverting terminal connected to a reset resistor for determining a minimum value of the common voltage; A second comparator having a non-inverting terminal connected to the voltage dividing node and an inverting terminal connected to an output terminal for outputting the common voltage; And a MOS transistor having a gate connected to the output of the first comparator, a source connected to the reset resistor, and a drain connected to the voltage divider node. Common voltage generator. 3. The common voltage generator of claim 2, wherein the memory is an EEPROM from which the second control signal can be repeatedly programmed. The method of claim 3, wherein And the digital analog converter, memory, first comparator, and MOS transistor are integrated into a digital variable resistance integrated circuit. The method of claim 4, wherein the common voltage regulator, A first terminal to which a power supply voltage is supplied; A second terminal to which the power supply voltage is supplied as an enable signal; A third terminal to which the first control signal is applied, and And a control interface enabled by the enable signal to provide the first control signal to the digital analog converter. The method of claim 4, wherein the common voltage regulator, A first terminal to which a power supply voltage is supplied; A second terminal to which the power supply voltage is supplied as an enable signal; A third terminal to which the second control signal is applied, and And a control interface enabled by the enable signal to provide the second control signal to the memory. A common voltage generator configured to store a control signal corresponding to the common voltage calibrated by an external common voltage adjusting device and to fix and output a level of the common voltage in response to the control signal; A gamma voltage generator for generating a gamma voltage by dividing the analog power voltage; A data driver to output a gray scale display voltage using the gamma voltage; And A liquid crystal panel displaying an image in response to the common voltage and the gray scale display voltage; Liquid crystal display comprising a. The method of claim 7, wherein the common voltage generator, And a memory in which the control signal is stored. The liquid crystal display of claim 8, wherein the memory is an EEPROM in which the control signal can be repeatedly programmed.

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