KR20080063975A - Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device by the same - Google Patents

Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device by the same Download PDF

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Publication number
KR20080063975A
KR20080063975A KR1020070000645A KR20070000645A KR20080063975A KR 20080063975 A KR20080063975 A KR 20080063975A KR 1020070000645 A KR1020070000645 A KR 1020070000645A KR 20070000645 A KR20070000645 A KR 20070000645A KR 20080063975 A KR20080063975 A KR 20080063975A
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South Korea
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region
silicide
spacer
film
semiconductor substrate
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KR1020070000645A
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Korean (ko)
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권형신
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삼성전자주식회사
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Priority to KR1020070000645A priority Critical patent/KR20080063975A/en
Publication of KR20080063975A publication Critical patent/KR20080063975A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device manufactured thereby are provided. A method for manufacturing a semiconductor integrated circuit device provides a semiconductor substrate having a first region and a second region defined thereon, and comprising a gate insulating film, a gate electrode, a spacer oxide film, a first spacer and a source / on a semiconductor substrate of the first and second regions. Forming a drain region, partially etching the spacer oxide film to form a recess between the first spacer and the semiconductor substrate, and between the first spacer and the gate electrode, and forming a first silicide blocking film on the entire surface of the semiconductor substrate, but filling the recess And supplying nitrogen to the first silicide blocking film in the first region and selectively removing the first silicide blocking film in the first region, wherein the first silicide blocking film fills the recess to form a second spacer. A silicide process is performed on the semiconductor substrate to expose the top surface of the gate electrode of the first region and the exposed source / drain regions. It includes forming a silicide layer on top.

Description

Method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device manufactured by the same

1 to 8 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

9 is a graph illustrating a difference in thickness of a silicide blocking layer according to whether a nitrogen injection process is performed in a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 10 is a graph illustrating an etching amount of a silicide blocking layer according to a difference in a cleaning process in a method of manufacturing a semiconductor integrated circuit device according to an exemplary embodiment of the present disclosure.

(Explanation of symbols for the main parts of the drawing)

100: semiconductor substrate 102: device isolation film

210: gate insulating film 220: gate electrode

230: spacer oxide film 240: first spacer

250: source / drain region 260: silicide film

310: first silicide blocking film 312, 322: second spacer

320: second silicide blocking film 410: mask pattern

The present invention relates to a method for manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device manufactured thereby, and more particularly, to a method for manufacturing a semiconductor integrated circuit device with improved reliability and a semiconductor integrated circuit device manufactured thereby.

As semiconductor integrated circuit devices become more integrated, the size of semiconductor devices is gradually decreasing, design rules are decreasing, and as the size of semiconductor devices is reduced, cell resistance is increasing. Therefore, as one of the solutions, the silicide layer is formed at the interface where the contact is to be formed. The silicide film serves to reduce the resistance of the interface on which the contact is formed.

Meanwhile, one semiconductor integrated circuit device includes a region in which a silicide film is not formed, and a silicide blocking film is formed on the region so that the silicide process is not affected.

The silicide blocking film is selectively formed only in a portion of the semiconductor integrated circuit device. When the silicide blocking film is formed, only the silicide blocking film on the region where the silicide film is to be formed is etched away after the silicide blocking film is formed on the entire surface of the semiconductor substrate. In order to prevent the lower transistor from being damaged in the etching process, an etch stop layer may be formed under the silicide blocking layer, for example, an oxide layer. On the other hand, when the deposition process for depositing the oxide film, which is an etch stop film, is performed, the semiconductor integrated circuit device is heated to a predetermined temperature, which can shorten the channel length of the transistor. In addition, the yield may be reduced due to impurities generated during the deposition of the oxide film.

On the other hand, in the manufacturing process of a semiconductor integrated circuit device, after forming a gate insulating film and a gate electrode, a spacer is formed in the gate electrode side surface. Here, a reoxidation process may be performed after the gate is formed to remove hot carriers and improve the reliability of the semiconductor device. By performing the reoxidation process, an oxide film is formed on the boundary between the spacer and the gate electrode and on the lower surface of the spacer.

A part of the oxide layer may be removed together when the etch stop layer under the silicide blocking layer is removed, and a portion exposed to the outside from the bottom surface of the spacer may be removed. In such a case, voids may occur on the bottom surface of the spacer. If voids occur on the lower surface of the spacer, the silicide film formed in a subsequent process may penetrate in the direction of the gate electrode, thereby degrading the reliability of the semiconductor device. Alternatively, metals deposited for contact formation may penetrate into the voids and cause shorts in subsequent processes, such as short circuits.

It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device with improved reliability.

Another object of the present invention is to provide a semiconductor integrated circuit device with improved reliability.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, which includes a semiconductor substrate having a first region and a second region defined thereon, and on a semiconductor substrate of the first and second regions. A gate insulating film, a gate electrode, a spacer oxide film, a first spacer, and a source / drain region are formed on the substrate, and the spacer oxide film is partially etched to remove the spacer oxide film between the first spacer and the semiconductor substrate and between the first spacer and the gate electrode. A recess is formed, and a first silicide blocking film is formed on the entire surface of the semiconductor substrate, and the recess is buried, nitrogen is supplied on the first silicide blocking film of the first region, and the first silicide is formed. The silicide blocking layer may be selectively removed, and the first silicide blocking layer may fill the recess to form a second spacer. To the to and proceed with the silicide process on said semiconductor substrate forming includes forming said first upper surface region and the silicide film on the upper portion of the exposed source / drain regions of the gate electrode.

In accordance with another aspect of the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a sidewall of the gate electrode. A spacer oxide film extending to a portion of the semiconductor substrate, a spacer formed on a side surface of the spacer oxide film to cover the spacer oxide film, a source / drain region formed in alignment with the gate electrode in the semiconductor substrate, and an upper portion of the gate electrode and the It includes a silicide film formed on the source / drain region.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8. 1 to 8 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

In the following description of the manufacturing method, a process that can be formed according to process steps well known to those skilled in the art will be briefly described in order to avoid being construed as obscuring the present invention.

First, referring to FIG. 1, a transistor is formed on a semiconductor substrate 100. The transistor includes a gate insulating layer 210, a gate electrode 220, a spacer oxide layer 230a, a first spacer 240, and a source / drain region 250.

The semiconductor substrate 100 may be a silicon substrate, a silicon on insulator (SOI) substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display. In addition, the semiconductor substrate 100 mainly uses a P-type substrate, and although not shown in the drawing, a P-type epitaxial layer may be grown on the semiconductor substrate 100.

The semiconductor substrate 100 may be divided into a silicide formation region and a silicide blocking region, and the silicide formation region may include an NMOS region and a PMOS region. Here, region A defines an NMOS region, region B defines a PMOS region, and region C defines a silicide blocking region.

First, the semiconductor substrate 100 is separated into an active region and an inactive region by a device isolation film 102 such as shallow trench isolation (STI) or field oxide (FOX). Subsequently, a gate insulating layer 110 and a gate electrode 120 are formed on the upper surface of the semiconductor substrate 100 including the NMOS region A, the PMOS region B, and the silicide blocking region C. The gate insulating layer 110 may be formed of, for example, a material such as a silicon oxide film (SiOx), a silicon oxynitride film (SiON), or the like. The gate electrode 120 is a conductor and may be formed to include polysilicon doped with impurities. In addition, a metal film may be included, and other material films may be included as necessary. Here, each gate electrode 120 formed in the NMOS region A, the PMOS region B, and the silicide blocking region C may have a different size. When the gate insulating film 210 and the gate electrode 220 are formed, the insulating film and the conductive film may be sequentially stacked, and then may be formed by performing a photolithography process.

Subsequently, an oxidation process may be performed on the semiconductor substrate 100 to form a spacer oxide film 230a. The oxidation process may be a reoxidation process. When the reoxidation process is performed, a spacer oxide layer 230a is formed on the side of the gate electrode 220 and the semiconductor substrate 100, and thus hot carriers are formed. Eliminate the chip and improve the reliability of the semiconductor device.

Subsequently, the first spacer 240 is formed on the sidewall of the gate electrode 220, that is, on the side surface of the spacer oxide layer 230a. Here, the first spacer may be formed on the side surface of the gate electrode 220 and on the spacer oxide layer 230a formed in the shape of the letter L on the semiconductor substrate 100.

Subsequently, an ion implantation process for forming the source / drain regions 250 on the semiconductor substrate 100 is performed. At this time, when the transistor to be formed is N-type, ions are implanted with arsenic (As) or phosphorus (P) at an energy of several tens of keV. The source / drain region 250 may be formed by ion implantation with energy of keV. The source / drain region 250 may be formed of a lightly doped drain (LDD).

Subsequently, referring to FIG. 2, the spacer oxide layer 230a of FIG. 1 is partially etched to recess the first spacer 240 and the semiconductor substrate 100, and the first spacer 240 and the gate electrode 220. To form. In this case, the etching of the spacer oxide layer 230a may be partially performed by wet etching.

3, the first silicide blocking layer 310 is formed on the entire surface of the semiconductor substrate 100. The first silicide blocking layer 310 may be a single layer, for example, an SiN layer. The first silicide blocking layer 310 may be used as a multilayer, but does not include an oxide layer. In addition, an etch stop layer is not formed under the first silicide blocking layer 310.

4, a mask pattern 410 is formed on the silicide blocking region C. Referring to FIG. The mask pattern 410 may be, for example, a photoresist pattern. In order to form the mask pattern 410 on the silicide blocking region C, a mask film (not shown) is applied to the entire surface of the semiconductor substrate 100, and the mask films of the silicide forming regions A and B are removed to silicide blocking. A mask pattern 410 blocking only the region C may be formed.

Next, referring to FIG. 5, nitrogen is supplied to the entire surface of the semiconductor substrate 100. That is, a nitrogen injection process of supplying nitrogen to the semiconductor substrate 100 is performed. When the nitrogen injection process is performed, the first silicide blocking layer 310 formed in the silicide forming regions A and B receives nitrogen, but the first silicide blocking region C blocked by the mask pattern 410 is blocked. The silicide blocking film 310 is not supplied with nitrogen. Hereinafter, the silicide blocking film of the silicide formation region (A, B) supplied with nitrogen is defined as a second silicide blocking film 320.

The second silicide blocking film 320 supplied with nitrogen and the first silicide blocking film 310 not supplied with nitrogen have different etching selectivity when a cleaning process such as SC1 (Standard Clean-1) cleaning process is performed in a subsequent process. .

Next, the mask pattern 410 is removed. In this case, when the mask pattern 410 is a photoresist pattern, the mask pattern 410 may be removed by an ashing process and a strip process.

6, the second silicide blocking layer 320 is selectively removed by performing a cleaning process on the semiconductor substrate 100, and the second silicide blocking layer 320 fills the recess to form a second recess. Spacer 322 is formed.

At this time, as the washing step, for example, the SC1 washing step can be performed. SC1 (Standard Clean-1) cleaning process is cleaned with cleaning solution (NH 4 OH / H 2 O 2 ) or BHF solution. The etching selectivity of the second silicide blocking film 320 with respect to the cleaning solution or the BHF solution used in the SC1 cleaning process is greater than the etching selectivity of the first silicide blocking film 310. Therefore, only the second silicide blocking film 320 may be selectively removed.

Alternatively, the etching process may be performed with an etching solution containing HF. In this case, the etching selectivity of the second silicide blocking film 320 with respect to the etching solution containing HF is larger than the etching selectivity of the first silicide blocking film 310. Therefore, only the second silicide blocking film 320 may be selectively removed.

Here, since the second spacer 322 is formed on the top and side surfaces of the spacer insulating film 230, the spacer insulating film 230 is not exposed to the outside. That is, the spacer insulating film 230 is completely blocked by the second spacer 322.

In the method for fabricating a semiconductor integrated circuit device according to an embodiment of the present invention, etching selection of the first and second silicide blocking layers 310 and 320 formed in the silicide forming regions A and B and the silicide blocking region C is performed. The ratio is adjusted differently, and the second silicide blocking layer 320 of the silicide formation regions A and B is removed using the ratio. Therefore, since the dry etching process for removing the silicide blocking films of the silicide forming regions A and B does not need to be performed, an oxide film is not formed as an etch stop film under the first and second silicide blocking films 310 and 320. You don't have to. If the oxide stop film is not formed, the process can be simplified and the cost can be reduced.

In addition, the second silicide blocking film 320 fills the recesses formed in the upper and side surfaces of the spacer oxide film 230 to form the second spacer 322 so that the spacer oxide film 230 is completely blocked.

Subsequently, referring to FIG. 7, a silicide process may be performed on the semiconductor substrate 100 to form the silicide layer 260 on the upper and source / drain regions 250 of the gate electrode 220 of the silicide formation regions A and B. ).

Specifically, first, a silicide metal film (not shown) is formed on the entire surface of the semiconductor substrate 100. In this case, the silicide metal film may be formed of a low resistance metal, and may be formed of, for example, titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), or the like.

Subsequently, a heat treatment process is performed on the semiconductor substrate 100. The heat treatment process may be performed using, for example, a rapid thermal process (RTP) apparatus, a furnace, or the like. When the heat treatment process is performed, the silicide film is formed by reacting the metal and silicon at a portion where the silicide metal film and the silicon are in contact with each other. Subsequently, when the unreacted silicide metal layer is removed, the silicide layer 260 is not formed in the silicide blocking region C in which the first silicide blocking layer 310 is formed, and the gate electrodes of the silicide forming regions A and B are removed. The silicide layer 260 is formed only on the upper portion of the 220 and the source / drain region 250.

In this case, the transistors of the silicide forming regions A and B include the first and second spacers 240 and 322, so that the spacer oxide film 230 is not exposed to the outside. Therefore, it is possible to structurally prevent the silicide film 260 from penetrating into the spacer oxide film 230. That is, the reliability of the semiconductor integrated circuit device can be improved.

8, the first silicide blocking layer 310 of the silicide blocking region C is removed. As a result, a second spacer 312 is formed to fill the recess formed in the top and side surfaces of the spacer oxide layer 230 of the silicide blocking region C. Referring to FIG. As a result, the silicide film 260 is formed in the silicide forming regions A and B, and the semiconductor integrated circuit device in which the silicide film 260 is not formed in the silicide blocking region C is completed.

According to the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, the time required to form the etch stop layer by not forming the etch stop layer below the first and second silicide blocking layers 310 and 320, and You can save money. In addition, it is possible to prevent the deterioration of the characteristics of the semiconductor device by eliminating the thermal process necessary for depositing the etch stop film.

On the other hand, since the silicide film 260 can be structurally prevented from penetrating the spacer oxide film 230, the reliability of the semiconductor integrated circuit device can be improved.

Hereinafter, a semiconductor integrated circuit device manufactured according to an embodiment of the present invention will be described with reference to FIG. 8.

Referring to FIG. 8, a semiconductor integrated circuit device manufactured according to an exemplary embodiment may be divided into silicide forming regions A and B and silicide blocking regions C. Referring to FIG. On the semiconductor substrate 100 in the silicide formation regions A and B, the gate insulating film 210, the gate electrode 220 formed on the gate insulating film 210, and the sidewalls of the gate electrode 220 may be formed. A second spacer 312 formed to fill the spacer oxide film 230 formed to extend to a partial region, the first spacer 240 formed on the side surface of the spacer oxide film 230, and the recesses formed on the top and side surfaces of the spacer oxide film 230. 322, a source / drain region 250 aligned with the gate electrode 220, and a silicide layer formed on the gate electrode 220 and the source / drain region 250 may be provided in the semiconductor substrate 100. .

In the silicide forming regions A and B of the semiconductor integrated circuit device according to the exemplary embodiment, the second spacers 312 and 322 may be disposed so that the spacer oxide film 230 is not exposed to the upper and side surfaces of the spacer oxide film 230. Is formed.

The second spacers 312 and 322 are formed to cover side surfaces of the spacer oxide film 230 to protect the spacer oxide film 230. In addition, the second spacer 322 of the silicide forming regions A and B secures a separation distance between the silicide layer 260 and the spacer oxide layer 230, so that the silicide layer 260 penetrates into the spacer oxide layer 230. By preventing it, the reliability of the semiconductor integrated circuit device can be improved.

9 is a graph illustrating a difference in thickness of a silicide blocking layer according to whether a nitrogen injection process is performed in a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

The graph (1) shows the thickness (a) of the silicide blocking film before the cleaning process and the thickness (b) of the silicide blocking film after the cleaning process after the nitrogen injection process is performed on the silicide blocking film. The thickness of the silicide blocking film was measured repeatedly until I-V and expressed as a standardized value. As the process conditions, N 2 was deposited on the silicide blocking film formed of SiN. The ion implantation process was performed at 3 KeV, the SC1 cleaning process was performed for 600 seconds, and the thickness of the silicide blocking film before and after the cleaning process was measured.

Graph (2) shows the thickness (c) of the silicide blocking film before the cleaning process and the thickness (d) of the silicide blocking film after the cleaning process in the semiconductor integrated circuit device in which the nitrogen injection process is not performed on the silicide blocking film. Indicates. The thickness of the silicide blocking film was measured repeatedly until VI-VIII and represented as a standardized value. As the process conditions, the SC1 cleaning process was performed for 600 seconds to the silicide blocking film formed of SiN, and the thickness of the silicide blocking film before and after the cleaning process was measured.

Referring to FIG. 9, the silicide blocking film subjected to the nitrogen injection process was etched by 50% or more by the SC1 cleaning process, but the silicide blocking film that did not undergo the nitrogen injection process hardly etched even when the SC1 cleaning process was performed. Can be. That is, it can be seen that the etch selectivity for the SC1 cleaning process of the silicide blocking film subjected to the nitrogen injection process is greater than the etch selectivity of the silicide blocking film without the nitrogen injection process.

FIG. 10 is a graph illustrating an etching amount of a silicide blocking layer according to a difference in a cleaning process in a method of manufacturing a semiconductor integrated circuit device according to an exemplary embodiment of the present disclosure.

Here, (e) represents the etching amount of the silicide blocking film formed of SiN when the SC1 cleaning process is performed after the nitrogen injection process, and (f) is HF diluted to 1/100 after the nitrogen injection process. The etching amount of the silicide blocking film formed of SiN when the cleaning process was performed with the prepared etchant was shown as a standardized value.

In addition, (g) is 1600 seconds, (h) is 1300 seconds, and (i) is the etching amount of the silicide blocking film when the cleaning process is performed for 1180 seconds.

Referring to FIG. 10, it can be seen that the etching selectivity of the silicide blocking film in which nitrogen is injected is high not only by the SC1 cleaning process but also by the etchant including HF.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the semiconductor integrated circuit device and the manufacturing method as described above has one or more of the following effects.

First, since the etch stop layer is not formed below the silicide blocking layer, time and cost required to form the etch stop layer may be reduced, and a heat process necessary for depositing the etch stop layer may be omitted, thereby deteriorating characteristics of the semiconductor device. Can be prevented.

Second, since the silicide film can be structurally prevented from penetrating into the spacer oxide film, the reliability of the semiconductor integrated circuit device can be improved.

Claims (10)

Providing a semiconductor substrate having a first region and a second region defined therein, Forming a gate insulating film, a gate electrode, a spacer oxide film, a first spacer, and a source / drain region on the semiconductor substrate of the first and second regions, Partially etching the spacer oxide layer to form a recess between the first spacer and the semiconductor substrate and between the first spacer and the gate electrode, Forming a first silicide blocking layer on the entire surface of the semiconductor substrate, and filling the recess; Supplying nitrogen on the first silicide blocking film in the first region to form a second silicide blocking film, Selectively removing the second silicide blocking film in the first region, wherein the second silicide blocking film fills the recess to form a second spacer, Performing a silicide process on the semiconductor substrate to form a silicide layer on an upper surface of the gate electrode of the first region and on the exposed source / drain regions. The method of claim 1, And the first silicide blocking film is a SiN film. The method of claim 1, Selectively removing the second silicide blocking film of the first region, The semiconductor integrated circuit device of claim 1, wherein the etching process has a larger etching selectivity for the second silicide blocking film supplied with nitrogen than the etching selectivity for the first silicide blocking film in the second region. Manufacturing method. The method of claim 3, wherein The cleaning process is a method of manufacturing a semiconductor integrated circuit device SC1 (Standard Clean-1) cleaning process. The method of claim 3, wherein And the etching solution of the cleaning process comprises an HF solution. The method of claim 1, And partially etching the spacer oxide layer to form a recess between the first spacer and the semiconductor substrate and between the first spacer and the gate electrode, by wet etching. The method of claim 1, Supplying nitrogen on the first silicide blocking film of the first region, A mask pattern for blocking the second region is formed on the second region, Supplying nitrogen to the semiconductor substrate but supplying nitrogen only to the first silicide blocking film in the first region to form a second silicide blocking film, Manufacturing the semiconductor integrated circuit device including removing the mask pattern. The method of claim 1, After forming a silicide film on the upper surface of the gate electrode in the first region and on the exposed source / drain regions, removing the first silicide blocking film formed on the second region. Way. Semiconductor substrates; A gate insulating film formed on the semiconductor substrate; A gate electrode formed on the gate insulating film; A spacer oxide layer extending along a sidewall of the gate electrode to a partial region of the semiconductor substrate; A spacer formed on a side surface of the spacer oxide film to cover the spacer oxide film; A source / drain region formed in the semiconductor substrate to be aligned with the gate electrode; And And a silicide layer formed over the gate electrode and over the source / drain region. The method of claim 9, And the silicide layer formed on the spacer oxide layer and the source / drain region is separated by the spacer.
KR1020070000645A 2007-01-03 2007-01-03 Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device by the same KR20080063975A (en)

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