KR20080063887A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20080063887A
KR20080063887A KR1020070000413A KR20070000413A KR20080063887A KR 20080063887 A KR20080063887 A KR 20080063887A KR 1020070000413 A KR1020070000413 A KR 1020070000413A KR 20070000413 A KR20070000413 A KR 20070000413A KR 20080063887 A KR20080063887 A KR 20080063887A
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KR
South Korea
Prior art keywords
hard mask
film
mask layer
cell region
layer
Prior art date
Application number
KR1020070000413A
Other languages
Korean (ko)
Inventor
오상원
Original Assignee
주식회사 하이닉스반도체
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070000413A priority Critical patent/KR20080063887A/en
Publication of KR20080063887A publication Critical patent/KR20080063887A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for fabricating semiconductor devices is provided to reduce size of a gate in periphery regions by enlarging CD(Critical Dimension) bias of a hard mask in the periphery regions. A gate insulating layer(11) and a conductive layer(12) for gate electrodes are sequentially formed on cell and periphery regions of a semiconductor substrate(10). A first hard mask layer(14) is formed on the conductive layer of the cell region and a second hard mask layer(16) having a hardness lower than the first hard mask is formed on the conductive layer of the periphery region. Patterning is performed on the first and second hard mask layers. The conductive layer and the gate insulating layer are etched by using the patterned first and second hard mask layers as a mask and then a gate is formed.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10: semiconductor substrate

11: gate insulating film

12: conductive film for gate electrode

13: nitride film

14: first hard mask film

15: first SiON film

16: second hard mask film

17: second SiON film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device capable of overcoming the limitations of photo lithography and etch recipe tuning and reducing the gate size of a peripheral region. It is about.

In general, there is a CD (Critical Dimension) difference, that is, a CD bias before and after etching of a semiconductor device manufacturing process. In general, an etching process of a semiconductor device is performed by using a predetermined photoresist pattern as an etching mask, where a final inspection CD after etching of an etching target layer with respect to a developed inspection CD (DICD) of the photoresist pattern is performed. The difference is called CD bias.

In addition, CD bias (Critical Dimension Bias) during gate etching in an isolated region, such as a peripheral region, compared to a dense region having a high pattern density, such as a cell region, according to the gate pattern density during gate etching of a semiconductor device. ) A lot occurs. Here, the CD bias difference between the dense region and the isolated region is called ID bias.

Meanwhile, in order to substantially reduce the chip size due to the reduction of the design rule, the gate size of the peripheral region as well as the cell region should be reduced. For example, in a 60nm class device, the gate size of the peripheral region should be formed to 100nm or less. However, it is very difficult to form a photoresist pattern of 100 nm or less in the peripheral region due to the limitation of the photolithography process (the process of etching the etching target after forming the photoresist pattern as an etching mask).

Thus, at present, a photoresist pattern of about 120 nm is formed, and the gate size is readjusted to about 100 nm through etching recipe tuning during gate etching.

However, in future devices below 60nm, the gate size of the peripheral area needs to be further reduced. With current technology, it is impossible to further reduce the gate size of the peripheral area due to the limitations of photolithography and etching recipe tuning. Therefore, there is a problem that it is difficult to reduce the chip size with the current technology.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and is capable of effectively reducing the chip size by overcoming the limitations of photolithography and etching recipe tuning and reducing the gate size of the peripheral region. The purpose is to provide a method.

According to an aspect of the present invention, a gate insulating film and a conductive film for a gate electrode are sequentially formed in a cell region and a peripheral region of a semiconductor substrate, and a first hard layer is formed on the conductive film of the cell region. Forming a mask film and forming a second hard mask film having a lower degree of curing than the first hard mask film on the conductive film in the peripheral region, and patterning the first hard mask film and the second hard mask film. And etching the conductive layer and the gate insulating layer using the patterned first hard mask layer and the second hard mask layer as a mask to form a gate.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same components.

Example 1

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 1A, a gate insulating film 11 and a conductive film 12 for a gate electrode are sequentially formed on a semiconductor substrate 10, and an LPC SAC (Landing) is formed on the conductive film 12 for a gate electrode. The nitride film 13 is formed to form a Plug Contact Self Aligned Contact.

Subsequently, as shown in FIG. 1B, the first hard mask film 14 is formed on the nitride film 13. The first hard mask film 14 may be formed of an amorphous carbon film or a tungsten film grown at a high temperature of at least 400 ° C. or higher.

Subsequently, the first SiON film 15 may be further formed on the first hard mask film 14.

Subsequently, as shown in FIG. 1C, after forming a photoresist pattern (not shown) that opens the peripheral region, the first SiON layer 15 and the first hard mask layer of the peripheral region are formed using an etching mask. Etch and remove (14).

Subsequently, as shown in FIG. 1D, a second hard mask film 16 having a lower degree of curing than the first hard mask film 14 is formed on the entire structure. In this case, when the first hard mask film 14 is formed of an amorphous carbon film grown at a high temperature, the second hard mask film 16 is formed of an amorphous carbon film grown at a lower temperature, for example, less than 400 ° C. do.

As is known, an amorphous carbon film has a density that varies depending on its growth temperature, so that an amorphous carbon film grown at a high temperature of 400 ° C. or more has a dense property, while an amorphous carbon film grown at a low temperature of less than 400 ° C. is porous. Since the amorphous carbon film grown at a low temperature has a lower degree of curing than that of the amorphous carbon film grown at a high temperature.

On the other hand, when the first hard mask film 14 is formed of a tungsten film, the second hard mask film 16 is preferably formed of a tungsten silicide film.

Subsequently, a front surface etching process may be performed to reduce the step difference between the cell region and the peripheral region, and a chemical mechanical polishing process may be further performed after the front surface etching process.

Subsequently, a second SiON film 17 may be further formed on the second hard mask film 16.

Subsequently, as shown in FIG. 1E, the second SiON film 17 and the second hard mask film 16 in the cell region are removed. For example, the second SiON layer 17 and the second hard mask layer 16 of the cell region may be selectively formed by an etching process of forming a photoresist pattern (not shown) that opens the cell region and using the photoresist pattern as an etching mask. Remove

In addition, the second SiON film 17 and the second hard mask film 16 in the cell region may be removed to remove the first hard mask film 14 and the first SiON 15 in the peripheral region. The second SiON film 17 and the second hard mask film of the cell region are sequentially subjected to the front-side etching process and the CMP process by targeting the first SiON film 15 of the cell region using the step between the peripheral region and the cell region. It is also possible to use a method of selectively removing only (16).

Subsequently, as shown in FIG. 1F, a photoresist is applied on the first SiON film 15 and the second SiON film 17, and an exposure and development process using a photomask is performed to obtain the photoresist pattern PR. Form.

Subsequently, the first SiON film 15, the second SiON film 17, the first hard mask film 14, and the second hard mask film 16 are etched using the photoresist pattern PR as an etching mask. The gate is formed by etching the nitride film 13, the gate electrode conductive film 12, and the gate insulating film 11 using the first and second hard mask films 14 and 16 as masks.

At this time, the side etching of the second hard mask layer 16 proceeds more severely than the first hard mask layer 14 due to the difference in curing characteristics of the first hard mask layer 14 and the second hard mask layer 16. The CD bias of the second hard mask film 16 is increased. Therefore, the gate of the peripheral region can be formed to a size less than the limit of the photolithography limit and the etching recipe tuning.

In the embodiment shown in the drawings, the first SiON film 15 and the second SiON film 17 are not removed, but the first SiON film 15 and the second SiON film 17 are removed and the SiON film, Insulating masks, such as an oxide film and a nitride film, can also be formed.

 Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, since the hard mask film of the peripheral area is formed of a material having a lower curing degree than the hard mask film of the cell area, the CD bias of the peripheral area hard mask can be increased, thereby limiting the photolithography limit and the etching recipe tuning. To overcome this problem and reduce the gate size of the peripheral area. Therefore, the chip size can be effectively reduced.

Claims (11)

Sequentially forming a gate insulating film and a conductive film for a gate electrode in the cell region and the peripheral region of the semiconductor substrate; Forming a first hard mask film on the conductive film in the cell region and forming a second hard mask film on the conductive film in the peripheral region having a lower degree of curing than the first hard mask film; Patterning the first hard mask layer and the second hard mask layer; And Etching the conductive layer and the gate insulating layer using the patterned first hard mask layer and the second hard mask layer as a mask to form a gate Method of manufacturing a semiconductor device comprising a. The method of claim 1, And the first hard mask film is formed of an amorphous carbon film grown at a high temperature of at least 400 ° C. or higher, and the second hard mask film is formed of an amorphous carbon film grown at a lower temperature than the first hard mask film. The method of claim 1, And the first hard mask film is formed of a tungsten film, and the second hard mask film is formed of a tungsten silicide film. The method of claim 1, Before the forming of the first hard mask layer and the second hard mask layer, Forming a nitride film on the conductive film Method of manufacturing a semiconductor device further comprising. The method of claim 1, Forming the first hard mask film in the cell region and forming the second hard mask film in the peripheral region, Depositing the first hard mask layer over the conductive layer; Removing the first hard mask layer formed on the peripheral region; Depositing a second hardmask film over the entire structure; And Removing the second hard mask layer formed on the cell region. Method for manufacturing a semiconductor device comprising a. The method of claim 5, wherein After depositing the first hard mask layer, Forming a SiON film on the first hard mask film Method of manufacturing a semiconductor device further comprising. The method of claim 5, wherein After depositing the second hard mask layer, Forming a SiON film on the second hard mask film Method of manufacturing a semiconductor device further comprising. The method of claim 5, wherein After depositing the second hard mask layer, Performing an entire surface etching process to mitigate the step between the cell region and the peripheral region; Method of manufacturing a semiconductor device further comprising. The method of claim 8, And a chemical mechanical polishing process after the entire surface etching process. The method of claim 5, wherein A semiconductor using a method of forming a photoresist pattern for opening the cell region when the second hard mask layer is removed from the cell region, and etching the second hard mask in the cell region using the photoresist pattern as a mask. Method of manufacturing the device. The method of claim 5, wherein When removing the second hard mask layer from the cell region, a method of selectively removing the second hard mask layer from the cell region may be performed by performing a front surface etching process and a chemical mechanical polishing process using a step between the cell region and the peripheral region. The manufacturing method of the semiconductor element used.
KR1020070000413A 2007-01-03 2007-01-03 Method for manufacturing semiconductor device KR20080063887A (en)

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KR1020070000413A KR20080063887A (en) 2007-01-03 2007-01-03 Method for manufacturing semiconductor device

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KR1020070000413A KR20080063887A (en) 2007-01-03 2007-01-03 Method for manufacturing semiconductor device

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