KR20080063596A - Semiconductor memory devices having enhanced repair rate and methods thereof - Google Patents

Abstract

A semiconductor memory device having enhanced redundancy repair rate and a method thereof are provided to increase redundancy repair rate as minimizing the increase of chip size. A main memory block(310) includes a number of memory cells storing binary data. A redundancy block(331,332,333,334) includes a basic redundancy cell to replace a defective memory cell when a specific memory cell in the main memory block has a defect, and a spare redundancy cell to replace the defective memory cell in stead of the basic redundancy cell when the basic redundancy cell has a defect. The redundancy block is arranged at the edge of the main memory block. An address decoder(341,342) selects a memory cell in the main memory block by decoding an address signal. A redundancy decoder(351,352,353,354) selects the basic redundancy cell or the spare redundancy cell corresponding to the defective memory cell, by decoding the address signal. A fuse box(361,362,363,364) enables to select a cell in the redundancy cell by the redundancy decoder, when the defective memory cell is generated.

Description

Semiconductor Memory Devices Having Enhanced Repair Rate and Methods Thereof}

1 is a block diagram illustrating a semiconductor memory device according to the prior art.

2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

4 is a flowchart illustrating a process of replacing memory redundancy.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having improved redundancy replacement efficiency and a memory redundancy replacement method.

If any one of the numerous microcells included in the memory is defective, it cannot be used as a memory and is treated as defective. However, as memory density increases, there is a high probability that defects will occur only in a small number of cells, but treating them as defective products will result in lower yields and inefficiency. Therefore, in this case, the yield is increased by replacing the defective cells by using the spare memory cells installed in the memory in advance, which is called a redundancy cell. The alternative method of redundancy cells has not been put to practical use in logic LSIs because the chip area increases and additional tests are required to eliminate defects as additional circuits are added. However, the increase in chip area in DRAM is relatively small. As a result of the increasing capacity and miniaturization of semiconductor memory products, redundancy replacement technology for defective cells becomes more important.

1 is a block diagram illustrating a semiconductor memory device according to the prior art.

Referring to FIG. 1, a semiconductor memory device generally includes a plurality of memory banks divided into blocks 110. Each memory block includes a plurality of memory cells 120 for storing data, a column address decoder (not shown) for controlling a column select line (CSL), and a row address for controlling a word line. The decoder 140 includes a low redundancy decoder and a fuse box (not shown) for controlling the low redundancy cells, column redundancy decoders 151 and 152 and a fuse box 161 and 162 for controlling the column redundancy cells. In FIG. 1, only a low address decoder, a low redundancy decoder, and a fuse box are illustrated for convenience.

In general, when a memory cell failure occurs, it is caused by focusing on some areas rather than random failures. If a defect occurs due to a defect, the defect is generated by a predetermined area due to the size of the defect. In this case, therefore, additional redundancy cells are required.

In addition, a defect may also occur in the redundancy cell itself. In this case, such a redundancy cell may not be used, thereby reducing the redundancy cell. In order to prevent this, the additional redundancy cell, the decoder and the fuse box have a disadvantage of increasing the chip area.

In the portion corresponding to the edge of the memory block, uniformity such as the level of each layer or the location of adjacent circuits is not maintained, and thus, the same characteristics as those implemented in the block may not be maintained.

SUMMARY OF THE INVENTION The present invention has been proposed to improve the inefficiency of the memory device according to the prior art, and an object thereof is to provide a semiconductor memory device and a memory redundancy control method that increase redundancy replacement efficiency while minimizing an increase in chip area. do.

In order to achieve the above object, a semiconductor memory device according to an embodiment of the present invention is a main memory block including a plurality of memory cells for storing binary data, and if a particular memory cell in the main memory block is defective, And a redundancy block including a basic redundancy cell for replacing a bad memory cell, and a spare redundancy cell for replacing the bad memory cell in place of the basic redundancy cell if the basic redundancy cell is bad. Is disposed at an edge of the main memory block.

 In addition, an address decoder which decodes an address signal and selects a memory cell in the main memory block, and when the bad memory cell occurs, decodes the address signal to generate a basic redundancy cell or a preliminary redundancy cell corresponding to the bad memory cell. A redundancy decoder for selecting a and a fuse box for determining whether a fuse is shorted according to whether or not the bad memory cell is generated, and when the bad memory cell is generated, allowing a cell in the redundancy block to be selected by the redundancy decoder. It may include.

The bad memory cell may further include a multiplexer for selecting the basic redundancy cell or the preliminary redundancy cell in the redundancy block according to the address signal.

The redundancy block may be arranged in a row line shape at upper and lower edges of the main memory block, and may be arranged in a column line shape at left and right edges of the main memory block, and the basic redundancy cell and the preliminary redundancy cell may be disposed. It may also be arranged in the form of a row line or a column line in the redundancy block.

When the bad memory cell is generated, when a redundancy cell in the main memory block including the bad memory cell is not available, a basic redundancy cell or a preliminary redundancy cell of another redundancy block disposed in an adjacent main memory block may be used.

Memory redundancy replacement method according to an embodiment of the present invention comprises the steps of testing the memory cells of the main memory block, if a particular memory cell of the main memory block is defective, replacing the defective memory cell with a basic redundancy cell, And when the basic redundancy cell is bad, replacing the bad memory cell with a spare redundancy cell.

If both the primary redundancy cell and the preliminary redundancy cell are defective, the method may further include replacing the defective memory cell with a basic redundancy cell or a preliminary redundancy cell of another adjacent main memory block edge.

Hereinafter, an electrostatic discharge protection circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

2, a semiconductor memory device generally includes a main memory block 210, a redundancy block 230, an address decoder 240, a redundancy decoder 251, and a fuse box 261.

The main memory block includes a plurality of memory cells 220 for reading or writing binary data and generally forming a memory bank. Memory cells 220 of the main memory block may be accessed by an address signal.

The redundancy block 230 includes memory cells 231 and 232 that can replace a failure in the memory cell 220 in the main memory block 210. The redundancy block 230 may be disposed at an edge of each main memory block 210. In addition, the redundancy block may include additional redundancy cells 232 in addition to the basic redundancy cell 231 capable of repairing the memory cells 220 of the main memory block 210. (Hereinafter, the basically provided redundancy cell is referred to as a basic redundancy cell, and an additional redundancy cell is referred to as a preliminary redundancy cell. Also, a memory cell in a main memory block is referred to as a main memory cell.) Therefore, a basic redundancy cell Even if a failure occurs in 231 itself, it is possible to replace the preliminary redundancy cell 232, thereby improving the replacement efficiency.

The address decoder 240 receives and decodes the address signal ADDRESS to access a specific cell indicated by the address. In FIG. 2, only a row address decoder is illustrated for convenience. The word line in the main memory block is controlled by the row address decoder.

When the main memory cell 220 is replaced with the redundancy cells 231 and 232 due to a defect, the redundancy decoders 251 and 252 receive and decode the address signal ADDRESS to decode the particular block in the redundancy block 230 indicated by the address. Make the cell accessible.

The fuse boxes 261 and 262 determine whether to access the main memory cell 220 or the redundancy cells 231 and 232 according to whether a fuse is shorted. As a method of shorting the fuse, a method of flowing an overcurrent using a program to melt and blow a fuse, a method of burning a fuse with a laser beam, a method of shorting a junction with a laser beam, a program to an EPROM memory cell, etc. Several methods can be used. In addition, although shown in the same block as the redundancy decoder in Figure 2, such a configuration may be modified differently according to the embodiment.

A semiconductor memory device according to an embodiment of the present invention may include a multiplexer 271. The multiplexer 271 may select one of the basic redundancy cell 231 and the preliminary redundancy cell 232 in the redundancy block. In addition, unlike the conventional redundancy cells are arranged on one side of the main memory block, in an embodiment of the present invention, the redundancy cells are distributed in the upper side, the lower side, or the left and right sides, so that the multiplexers are located in the same block. In addition to the redundancy cells, redundancy cells of adjacent memory blocks in close proximity may be used. In addition to adding the redundant redundancy cells 232, the replacement efficiency may be further improved by enabling the redundancy cells of the adjacent blocks.

3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

The semiconductor memory device of FIG. 3 is similar to the semiconductor memory device of FIG. 2 except for showing both the row address decoder 341 and the column address decoder 342.

Referring to FIG. 3, each main memory block 310 has a plurality of memory cells 320 storing binary data in a central portion of the block. Redundancy blocks 331, 332, 333, 334 for repair are arranged in a line form on the upper side, the lower side, the left side, and the right side of the main memory block 310, and each of the redundancy blocks 331, 332, 333, 334. In addition to the basic redundancy cell for preparing a main memory cell failure, the redundant redundancy cell for preparing a basic redundancy cell failure is included. The primary redundancy cell and the preliminary redundancy cell may be disposed in the same block and may be selected by the multiplexers 371, 372, 373, 374. According to an embodiment, the multiplexer may allow a specific redundancy cell to be selected by a control signal, or may be fixed to select a specific redundancy cell by using a fuse or the like.

Since the addition of the redundant redundancy cells is made without the addition of the redundancy decoders 351, 352, 353, and 354 and the fuse boxes 361, 362, 362, and 364, the increase in chip area compared with the conventional semiconductor memory device is not significant. Alternative efficiency can be increased.

When the main memory cell 320 is normal, the column address decoder 342 controls the vertical column selection line, and the row address decoder 341 controls the horizontal word line.

The redundancy decoder may also be divided into the low redundancy decoders 351 and 352 and the column redundancy decoders 353 and 354, and the vertical redundancy cells arranged on the left and right sides of the main memory block by the column redundancy decoders 353 and 354. 332 and 334 are controlled, and the horizontal redundancy cells 331 and 333 disposed above and below the main memory block are controlled by the low redundancy decoders 351 and 352.

In general, when a failure occurs in the main memory cell, the replacement may be performed in the unit of a column line or a row line instead of a single cell. Therefore, redundancy cells may be efficiently arranged in a line shape at the edge of the main memory block as shown in FIG. 3. . First, the basic redundancy cell to be replaced first is disposed near the center of the main memory block that is inside the preliminary redundancy cell, thereby maintaining uniformity such as the level of the stepped circuit or the adjacent circuit where the layers are implemented.

4 is a flowchart illustrating a process of replacing memory redundancy.

First, a read and write operation is tested on the main memory cell (S401), and it is determined whether or not it is normal (S402). If the memory operation is bad, a test is performed on the basic redundancy cells among the same redundancy blocks in order to replace the redundancy cells (S403). If the basic redundancy cell operates normally and can be replaced with the main memory cell, the main memory is replaced with the basic redundancy cell (S405). If a defect occurs in the basic redundancy cell and cannot be replaced, first, the redundant redundancy cells in the same block are replaced. It is tested (S406) to determine whether the replacement is possible (S408). When the spare redundancy cell is replaceable, the spare redundancy cell is replaced with the spare redundancy cell S408. If the spare redundancy cell is not replaceable, redundancy cells of not only the same block but also other adjacent blocks are tested (S409) to determine whether it is replaceable (S410). If there is a replaceable redundancy cell in the adjacent block, the main memory may be replaced with the redundancy cell of the adjacent block (S411), and in this case, the replacement is determined to be bad and ends.

1 to 4 may partially omit circuits necessary for an operation of a general semiconductor memory device such as an address driving circuit. However, these components may be variously added according to exemplary embodiments.

In the semiconductor memory device and the method of replacing memory redundancy according to an embodiment of the present invention, by replacing the redundancy cell at the edge of the memory block and adding the redundant redundancy cell without increasing the redundancy decoder and the fuse box, the replacement is minimized while minimizing the increase of the chip area. Can increase the efficiency.

In addition, when the redundancy cells in the same block are not available, the replacement cells can be replaced by the redundancy cells of the adjacent blocks, thereby further increasing the substantial replacement efficiency.

Claims (8)

A main memory block including a plurality of memory cells for storing binary data; And When a specific memory cell in the main memory block is bad, a basic redundancy cell for replacing the bad memory cell, and if the default redundancy cell is bad, a spare for replacing the bad memory cell in place of the default redundancy cell. A redundancy block including redundancy cells; And wherein the redundancy block is disposed at an edge of the main memory block. The method of claim 1, An address decoder for decoding an address signal to select a memory cell in the main memory block; A redundancy decoder for decoding the address signal and selecting a basic redundancy cell or a preliminary redundancy cell corresponding to the bad memory cell when the bad memory cell occurs; And The semiconductor device may further include a fuse box configured to determine whether a fuse is shorted according to whether the defective memory cell is generated and to select a cell in the redundancy block by the redundancy decoder when the defective memory cell occurs. Memory device. The semiconductor memory device of claim 2, further comprising: a multiplexer for selecting the basic redundancy cell or the preliminary redundancy cell in the redundancy block according to the address signal when the bad memory cell occurs. The semiconductor memory device of claim 1, wherein the redundancy block is disposed in a row line at upper and lower edges of the main memory block, and arranged in a column line form at left and right edges of the main memory block. The semiconductor memory device of claim 4, wherein the basic redundancy cell and the preliminary redundancy cell are arranged in a row line or a column line in the redundancy block. 6. The method of claim 5, wherein when the bad memory cell occurs, when a redundancy cell in the main memory block including the bad memory cell is not available, a basic redundancy cell or a preliminary redundancy of another redundancy block disposed in an adjacent main memory block. A semiconductor memory device comprising a cell. Testing the memory cells of the main memory block; If a specific memory cell of the main memory block is defective, replacing the defective memory cell with a basic redundancy cell; And If the basic redundancy cell is bad, replacing the bad memory cell with a preliminary redundancy cell. 8. The method of claim 7, further comprising the step of replacing the defective memory cell with a basic redundancy cell or a spare redundancy cell at an edge of another adjacent main memory block when both the primary redundancy cell and the preliminary redundancy cell are bad. To replace memory redundancy

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