KR20070034652A - Column Redundancy Circuit and Semiconductor Column Repair Method of Semiconductor Memory Device - Google Patents

Abstract

A column redundancy circuit in a semiconductor memory device having at least one subblock having memory cells connected to a plurality of local bit lines is disclosed. Such a column redundancy circuit includes a column fuse box portion for fusing when a defective cell exists among memory cells and a local bit line connected to the defective cell and a local bit line connected to a global bit line corresponding to the defective cell. In order to replace with a redundancy bit line, a local wi-pass unit is provided for disabling the local bit line connected to the defective cell by a signal applied from the column fuse box unit and enabling the local redundancy bit line. Thus, the present invention can provide an improved column redundancy circuit, thereby increasing repair efficiency in a semiconductor memory device by repairing a plurality of local bit line units connected to a global bit line.

Redundancy, Column, Global, Local, Fuse

Description

Column redundancy circuit in semiconductor memory device and column repair method according to the present invention

1 is a configuration diagram schematically showing an example of a column redundancy circuit at a conventional block level.

FIG. 2 is a diagram illustrating a column redundancy structure at an I / O level by enlarging one sub-block in FIG. 1; FIG.

Figure 3 is a schematic diagram showing a column redundancy circuit according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a column redundancy structure at an I / O level by enlarging one sub-block in FIG. 3. FIG.

<Description of the symbols for the main parts of the drawings>

100: column fuse box 102: column decoder

104: Global Wipaths 106: Local Wipaths

108: section decoder 120: sub block

110: redundancy global bitline decoder

122: main decoder RPT1 to RPT4: redundancy pass transistor

YPT21 ~ YPT28, YPT31 ~ YPT38: Wipass Transistor

GBL0 ~ GBL3: Global bitline LBL0 ~ LBL3: Local bitline

RLBL0 ~ RLBL3: Local Redundancy Bitline

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a redundancy circuit for repairing defective cells in a semiconductor memory device and a repair method thereof.

If any one of the numerous memory cells in the semiconductor memory device is defective, it will not function as the semiconductor memory device and will be treated as defective. However, as the degree of integration of semiconductor memory devices increases, there is a high probability that defects may occur only in a small amount of memory cells, but discarding them as defective products is an inefficient processing method that lowers the yield of good products.

Therefore, in this case, a method of increasing the acquisition rate of a good product has been adopted by replacing a defective cell by using a preliminary memory cell disposed in a semiconductor memory device.

In this way, the redundancy circuit is arranged to rescue defective cells which may occur randomly during the manufacture of the semiconductor memory device.

However, as the redundancy circuit is disposed, the area of the chip increases, and the increase in the test required for the repair is a problem, which is not practical in a large scale integrated circuit (LSI), but particularly, a DRAM (DRAM); Dynamic Random Access Memory) has been adopted in earnest from 64K to 256K DRAM due to the relatively small increase in chip area.

More specifically, in a semiconductor memory device, the redundancy circuit further arranges extra cells in addition to the actual capacity of the semiconductor memory device (eg, nxn) (eg, (n + m) x (n + m '). Where m and m 'correspond to a number representing the size of the redundancy cell), a row or column containing one or more defective cells after analyzing whether a bad memory cell is present Is a circuit for fabricating a defect-free semiconductor memory device by disconnecting and connecting to the redundancy cell, resulting in a capacity of nxn.

Hereinafter, a column redundancy circuit of a semiconductor memory device will be described with reference to the accompanying drawings.

1 is a configuration diagram schematically showing an example of a column redundancy circuit at a conventional block level.

Referring to FIG. 1, a plurality of sub blocks (SB) 20 is provided, and a repair unit for the plurality of sub blocks 20 is a global bit line (GBL). A semiconductor memory device having a structure of) is shown. Reference numeral 20 denotes a main row decoder MD, and reference numeral 18 denotes a section row decoder SD connected to the main row decoder MD, which is not closely related to the present invention, and thus a detailed description thereof is omitted. do.

Each of the sub-blocks SB includes a plurality of memory cells formed at intersections of a word line and a bit line.

The global bit lines GBL may be provided in plural (n global bit lines, for example, n = 16), and each of the global bit lines GBL may include a plurality of (eg, four). Local Bit Line (LBL) is connected. The global bit line GBL is selectively enabled by a global Y pass GYP 14 that receives a signal decoded by the column decoder DEC 12. Thus, data is written to the sub-block 20 accessed by the selected global bit line GBL through the write driver W / D, or the sense amplifier S / A from the accessed sub-block 20 is written. Amplified through and output to the outside. The data is transmitted and received via a plurality of section data lines SDL (eg, 16). This will be described in more detail with reference to FIG. 2.

FIG. 2 is a block diagram illustrating a column redundancy structure at an I / O level by enlarging one subblock of FIG. 1.

Referring to FIG. 2, four local bit lines LBL0 to LBL3 connected to each of the plurality of global bit lines GBL0 to GBL15 are provided in one sub block 20. Four redundancy local bit lines RLBL0 to RLBL3 are also connected to one redundancy global bit line RGBL. Here, a plurality of memory cells (not shown) are connected to each of the four local bit lines LBL0 to LBL3 connected to each of the plurality of global bit lines GBL0 to GBL15, and to one redundancy global bit line RGBL. A plurality of redundancy memory cells (not shown) are also connected to the four redundant local bit lines RLBL.

When a column address specifying the sub block 20 is applied, an arbitrary global bit line among the global bit lines GBL0 to GBL15 is selected, and the Wi-Fi transistors YPT1 are decoded by the decoded signals B7_Y0 to B7_Y3. ~ YPT16) is turned on. Thus, the local bit line connected to the memory cell to be accessed among the local bit lines LBL0 to LBL3 is enabled.

If one or more defective cells in any one or more subblocks of the plurality of subblocks 20 are generated, a column fuse box (RCP) arranged in units of the subblocks 20 may be used. 10 of FIG. 1 is used.

The column fuse box 10 corresponding to the defective cell is fused, so that when the address specifying the defective cell is input, the corresponding global bit line GBL is not selected and the redundancy global bit line RGBL is selected. By being selected, the semiconductor memory device is allowed to operate normally.

However, as described above, in the conventional semiconductor memory device, since the repair unit is a global bit line, when one repair is performed, a plurality of local bit lines are repaired at the same time, resulting in a problem of deteriorating repair efficiency. It is.

Accordingly, an object of the present invention is to provide a column redundancy circuit for improving the problem that the repair efficiency of the conventional semiconductor memory device is lowered.

Another object of the present invention is to provide a column redundancy circuit having a column fuse box for repairing a plurality of local bit line units connected to a global bit line.

Another object of the present invention is to provide a column repair method for repairing a local bit line in a sub block of a semiconductor memory device.

In order to achieve the above objects, a column redundancy circuit in a semiconductor memory device having at least one sub block having memory cells connected to a plurality of local bit lines according to an aspect of the present invention is characterized in that a defective cell of the memory cells includes: A column fuse box portion for fusing when present; And replacing the local bitline connected to the defective cell and the global bitline corresponding to the defective cell with a local redundancy bitline connected to a redundant memory cell by the signal applied from the column fuse box unit. And disabling a local bit line connected to the local bit line and enabling a local redundancy bit line.

The column fuse box unit may be disposed to correspond to a column of the sub block.

In addition, the global bit line corresponding to the defective cell may be enabled by the global wi-pass unit when an address specifying the defective cell is input during the operation of the semiconductor memory device.

In addition, the redundancy memory cells may correspond to each of the global bit lines and may be disposed for each sub block.

According to an aspect of the present invention, there is provided a column repair method of a semiconductor memory device including at least one sub block having memory cells connected to a plurality of local bit lines, wherein a defective cell is present among the memory cells. Selectively disables a local bit line connected to the defective cell and selectively enables a column fuse box unit disposed in each sub block to enable a local redundancy bit line connected to a redundant memory cell for replacing the defective cell. It is characterized by fusing.

Here, the local redundancy bit line is enabled when an address corresponding to the defective cell is input during operation of the semiconductor memory device, and corresponds to a plurality of local bit lines connected to a global bit line corresponding to the defective cell. Each sub block may be arranged.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The descriptions in the embodiments are only shown and limited by way of example, for the purpose of helping those skilled in the art to understand the present invention, and thus used to limit the scope of the present invention. Would not be.

3 is a schematic diagram illustrating a column redundancy circuit according to an embodiment of the present invention.

Referring to FIG. 3, a semiconductor memory including at least one subblock SB 120 having memory cells (not shown) connected to a plurality of local bit lines (refer to FIG. 4 and LBL0 to LBL3 of FIG. 4). The column redundancy circuit in the apparatus includes a column fuse box portion RCP 100 and a local wipath portion YP.

The column fuse box unit 100 is fused when a defective cell exists among the memory cells. The column fuse box unit 100 is disposed to correspond to the columns of the plurality of sub blocks 120.

The local wipe path YP disables the local bit line connected to the defective cell by a signal applied from the fused column fuse box unit 100. And enable the local redundancy bitline.

Thus, a local bit line connected to the defective cell and connected to a global bit line (GBL) corresponding to the defective cell is replaced with a local redundancy bit line connected to a redundant memory cell.

After the repair of the semiconductor memory device is completed, when an address for designating the defective cell is input during operation of the semiconductor memory device, a signal decoded by the redundant global bit line decoder (RGD) 110 may be globally wiped. Applied to the unit 104. In addition, the semiconductor memory device may be enabled by enabling the global bit line GBL corresponding to the defective cell by the global wi-pass unit GYP 104 and activating a local redundancy bit line that replaces a defective local bit line. It works normally.

A redundancy memory cell is connected to the local redundancy bit line to replace a plurality of memory cells connected to the bad local bit line. The redundancy memory cells (not shown) correspond to each of the global bit lines and are disposed for each sub block.

FIG. 4 is a block diagram illustrating a column redundancy structure at an I / O level by enlarging one sub-block in FIG. 3.

Referring to FIG. 4, local redundancy bit lines RLBL0 to RLBL3 corresponding to local bit lines LBL0 to LBL3 connected to the global bit lines GBL0 to GBL3 are disposed. Reference numerals YPT21 to YPT28 and YPT31 to YPT38 are Wi-Fi transistors for enabling a local bit line to be selected among the local bit lines LBL0 to LBL3 by the decoded column address signals B7_Y0 to B7_Y3. In addition, reference numerals RPT1 to RPT4 denote local redundancy bit lines RLBL0 to RLBL3 by fusing the column fuse box RCP to replace the local bit lines connected to the defective memory cells when the semiconductor memory device is repaired. Are redundant pass transistors for selectively enabling.

According to the present invention, when a column address specifying a bad memory cell is input, a local fuse line connected to the bad memory cell is disabled, and a corresponding column redundancy bit line is enabled so that the column fuse box (RCP of FIG. 3) is enabled. Is fused. Thus, the repaired semiconductor memory device can be operated normally.

In the case of the conventional global bit line repair, after one global bit line corresponding to the bad memory cell is replaced by the redundancy bit line, it is impossible to repair another global bit line in the same sub block. However, in the present invention, by repairing in a local bit line unit, even if a local bit line connected to one global bit line is repaired in one sub block, the local bit line connected to another global bit line may be repaired. There is an advantage that repair efficiency becomes high

According to an embodiment of the present invention, a column repair method of a semiconductor memory device having at least one sub block having memory cells connected to a plurality of local bit lines may include a column fuse box unit selectively disposed corresponding to a column of the sub block. It is characterized by fusing.

By selectively fusing the column fuse box unit corresponding to the column of the sub block, the local bit line connected to the defective cell is disabled when the defective cell is present among the memory cells. The local redundancy bit line coupled to the redundancy memory cell for replacing the defective cell is enabled.

Referring to FIG. 4, the local redundancy bit line is enabled when an address corresponding to the defective cell is input during operation of the semiconductor memory device, and four local bits connected to a global bit line corresponding to the defective cell. Each sub block may be disposed to correspond to a line.

The column redundancy circuit and the repair method thereof of the semiconductor memory device according to the embodiment of the present invention are not limited to the above embodiments, and various designs and applications can be made without departing from the basic principles of the present invention. It will be obvious to those of ordinary skill in the art.

As described above, the present invention provides an improved column redundancy circuit, thereby increasing the repair efficiency in the semiconductor memory device.

In addition, the present invention provides an improved column redundancy circuit, so that the repair can be performed in units of a plurality of local bit lines connected to the global bit lines.

In addition, the present invention has an effect of increasing the repair efficiency in a semiconductor memory device by providing an improved column repair method.

Claims (6)

A column redundancy circuit in a semiconductor memory device having at least one sub block having memory cells connected to a plurality of local bit lines, the column redundancy circuit comprising: A column fuse box unit for fusing when a defective cell is present among the memory cells; And In order to replace a local bit line connected to the defective cell and a global bit line corresponding to the defective cell with a local redundancy bit line connected to a redundancy memory cell, the defective cell is connected to the defective cell by a signal applied from the column fuse box unit. And a local wipath portion for disabling the connected local bitline and for enabling the local redundancy bitline. The method of claim 1, And the column fuse box portion is disposed to correspond to a column of the sub block. The method of claim 1, And a global bit line corresponding to the defective cell is enabled by a global wi-pass unit when an address specifying the defective cell is input during operation of the semiconductor memory device. The method of claim 1, And the redundancy memory cell corresponds to each of the global bit lines and is disposed in each of the sub-blocks. A method of repairing a column of a semiconductor memory device having at least one sub block having memory cells connected to a plurality of local bit lines, the method comprising: In order to disable a local bit line connected to the defective cell when a defective cell exists among the memory cells, and to enable a local redundancy bit line connected to a redundant memory cell for replacing the defective cell. A method of repairing a column of a semiconductor memory device, the method comprising selectively fusing a column fuse box unit corresponding to a column. The method of claim 5, The local redundancy bit line, It is enabled when an address corresponding to the defective cell is input during operation of the semiconductor memory device, and is disposed in each of the subblocks corresponding to a plurality of local bitlines connected to a global bitline corresponding to the defective cell. A method of repairing a column of a semiconductor memory device.

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