KR20080061946A - Method for manufacturing semiconductor device with enhancing pattern cd uniformity - Google Patents

Abstract

A method for manufacturing a semiconductor device for enhancing pattern CD uniformity is provided to suppress CD variation by deriving a photoresist sine curve. A lower part structure of a real device pattern and a real etch target layer are formed on a test wafer(110). Test photoresist layers with different thickness are formed on the test wafers(120). An exposure and developing processes are performed to the test photoresist layers(130). CDs of the patterns formed on the test photoresist layers is measured(140). The measures CDs are calculated as a graph about the thickness variation of the test photoresist layers(150). The thickness located at the minimum point or the maximum point is selected as the thickness of a process photoresist pattern to be formed on the real wafer(160). A photoresist layer of the selected thickness is formed on the real wafer on which the lower part structure and the etch target layer are formed(170). The process photoresist layer is exposed and developed.

Description

Method for manufacturing semiconductor device with enhancing pattern CD uniformity

1 is a process flowchart schematically shown to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.

2 and 3 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

4 is a graph showing a pattern threshold line width change according to a change in thickness of a photoresist layer measured according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method for manufacturing a semiconductor device for improving the critical line width uniformity of a pattern.

As semiconductor devices are highly integrated, the size of circuit patterns constituting DRAM memory devices is rapidly being reduced. As the size of a minimum transistor constituting a memory cell becomes smaller and smaller, a process margin for forming a peripheral circuit pattern is gradually becoming shorter than that of a cell. In 60nm or 50nm devices under development, the minimum transistor size is reduced to less than 100nm, resulting in very narrow process margins.

Lack of process margins may cause a defect in critical dimension (CD) of the gate pattern of the transistor, which may affect the operation of the actual memory device chip. In order to improve the CD uniformity of the actual circuit pattern on the wafer such as the gate pattern, it is necessary to first improve the line width uniformity of the photoresist pattern formed on the etching target layer such as the gate layer or the hard mask layer.

By the way, the line width of the photoresist pattern is affected by various patterning environments, and in particular, the variation of the pattern CD is caused by the thickness of the photoresist layer. Substantially depending on the thickness of the photoresist layer, the CD of the pattern to be formed exhibits sine curve variability. That is, the photoresist layer is simply thick and developed at more exposure energy, and conversely, the photoresist layer does not tend to be fully exposed and developed at less energy. The exposure energy to which the photoresist is developed may vary depending on the refractive index, the thickness of the photoresist layer and the wavelength band of the exposure source used in the exposure equipment. Therefore, the pattern CD developed at a given exposure energy used in the actual process is also measured to vary depending on the thickness of the photoresist layer.

Therefore, in order to further mitigate or suppress CD variability of the photoresist pattern and to realize a more uniform pattern CD uniformity, a process of first selecting an appropriate thickness of the photoresist layer is required.

An object of the present invention is to provide a semiconductor device manufacturing method for selecting a thickness of a photoresist layer capable of improving the critical line width uniformity of a pattern.

One aspect of the present invention for the above technical problem, the step of forming a substructure of the actual device pattern and the actual etching target layer on the test wafer, forming a test photoresist layer on the test wafers with a different thickness, Performing exposure and development on the test photoresist layers; Measuring line widths of the pattern formed on the exposed and developed test photoresist layer, calculating the measured line widths as a graph of a change in thickness of the test photoresist layers, positioned at a minimum or maximum point of the graph Selecting a thickness of the process photoresist layer to be formed on the actual wafer, forming a process photoresist layer having the predetermined thickness on the actual wafer on which the lower structure of the device pattern and the etching target layer are formed, and A semiconductor device manufacturing method comprising exposing and developing the process photoresist layer is provided.

The etching target layer may include a gate layer and a hard mask layer.

The test wafer may use a wafer processed in parallel with the actual wafer.

According to the present invention, it is possible to provide a semiconductor device manufacturing method for selecting a thickness of a photoresist layer capable of improving the critical line width uniformity of a pattern.

In an embodiment of the present invention, a method of fabricating a semiconductor device for improving the uniformity of the pattern critical line width (CD) by resetting the thickness of the photoresist layer in consideration of a process change accompanying the process of manufacturing the semiconductor device is provided. When the lower structure is formed on the semiconductor substrate for manufacturing the semiconductor device, the thickness of the photoresist layer formed to cover the etching target layer, which is the lower structure, is reset.

Until the lower structure is formed on the semiconductor substrate, many process schemes, types of semiconductor substrates and various kinds of layers are introduced, and thickness changes also proceed. In addition, due to a margin issue of the exposure process, the photoresist type and the bottom anti-reflective coating (BARC) change also proceed. In order to reflect these changes in the thickness of the photoresist layer, the thickness setting of the photoresist layer is formed by exposing the photoresist layer on the actual wafer on which the actual element formation is in progress and exposing the gate pattern threshold line width of the minimum transistor. CD) is performed by measuring.

The actual semiconductor device fabrication process proceeds to form a photoresist layer on a wafer on which a base line structure or substructure is formed. At this time, the thickness of the photoresist layer is split and set differently, and the exposure is performed with the same exposure energy for each wafer. Since the CD of the pattern to be measured varies depending on the thickness of the photoresist layer, a graph for this is calculated. The obtained CD change graph according to the PR thickness change is obtained in the form of a sine curve, and in the CD graph of the measured transistor according to the PR thickness, the portion which can minimize the influence on the CD change amount due to the thickness variation, for example, The thickness of the photoresist at the minimum or maximum point of the sine curve is selected.

Factors affecting the CD uniformity of the gate pattern include the surface topology, thickness, and refractive index of the underlying structure of the photoresist (PR) layer, such as the gate layer and the hard mask layer on the wafer. Can be considered It can be understood that the variation of the pattern CD occurs substantially in accordance with the thickness of the photoresist layer itself. In the exemplary embodiment of the present invention, the thickness of the photoresist layer capable of implementing CD uniformity may be optimally selected by reflecting the influence of the underlying structure on the wafer on which the actual process is performed, in setting the thickness of the photoresist layer. Therefore, CD variation of the photoresist pattern can be further suppressed, and CD uniformity of the lower hard mask layer pattern patterned by the photoresist pattern or the gate pattern thereunder can be further increased.

1 is a process flowchart schematically shown to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2 and 3 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 4 is a graph showing a pattern threshold line width change according to a change in thickness of a photoresist layer measured according to an exemplary embodiment of the present invention.

Referring to FIG. 1, in the method of manufacturing a semiconductor device according to an embodiment of the present invention, a test wafer for selecting a thickness of a photoresist layer may include a real wafer on which a substructure of an actual device pattern and an actual etching target layer are formed. Use as. First, a substructure of an actual device pattern and an actual etching target layer are formed on a test wafer (110 in FIG. 1). Since the test wafer uses an actual wafer or a wafer on which the equivalent process has been performed, the test wafer may be a wafer having a lower structure and an etching target layer as shown in FIG. 2.

Referring to FIG. 2, an isolation layer 215 for forming an active region 211 is formed on the wafer 210, and a gate dielectric layer 230 and a gate layer 250 are formed. In this case, the gate layer 250 may include a conductive polysilicon layer 251 and a tungsten (W) or tungsten silicide (WSix) layer 251 which are used to construct the actual transistor device. A capping layer 270 of silicon nitride for self-aligned contact (SAC) is formed on the gate layer 250. The structure of these layers and the structure of the underlying device isolation layer 215 cause surface height variations, ie topologies, different from bare wafers on the surface of the wafer 210.

The hard mask layer 290, which is an etching target layer, is formed on the lower structure. The photoresist layer is introduced to be used in the process of patterning the hard mask layer 290, but substantially gives a pattern to the pattern of the hard mask layer 290, and the gate layer according to the pattern of the hard mask layer 290. A pattern profile such as 250 depends. Thus, the photoresist layer may be understood as an etch mask introduced for patterning the gate layer 250.

The actual wafer 210 on which the actual device formation process is performed or the wafer on which the equivalent process is performed is used as a test wafer.

1 and 3, the test photoresist layer 330 is formed on the test wafers 210 with different thicknesses (120 of FIG. 1). In this case, when the photoresist is coated such that the thickness of the test photoresist layer 330 is different for each test wafer 210, the rotation speed (rpm) of the spinner may be changed. In addition, a bottom anti-reflective layer 310 may be introduced under the test photoresist layer 330 in the same manner as in the actual process.

Subsequently, an exposure 370 is performed by introducing a photomask 350 introduced into the test photoresist layers 330 during the exposure process on the actual process. The photomask 350 may be introduced to include a mask pattern 351 to impart the shape of the gate pattern. Therefore, such an exposure process may be understood as an exposure process on an actual process or a process equivalent thereto. Thus, exposure is performed on the respective test wafers 210 with the same or the same exposure energy (130 in FIG. 1). Thereafter, the exposed test photoresist layers 330 are developed.

The critical line widths (CDs) of the pattern formed on the exposed and developed test photoresist layer (330 of FIG. 3) are measured (140 of FIG. 1). Since the test photoresist layers 330 are formed by splitting the wafers 210 into different thicknesses, the measured CDs are also variously measured.

Referring to FIG. 4 along with FIG. 1, the measured critical line widths are calculated as a graph 400 of the change in thickness of the test photoresist layers 330 (150 of FIG. 1). Graph 400 of Figure 4 shows the calculated results. The calculated graph 400 shows the tendency of the CD change to have a sinusoidal curve according to the PR thickness.

Based on the result of the graph 400, the thickness of the photoresist layer which can minimize the amount of CD change according to the variables actually involved in the process is selected (160 in FIG. 1). In the result of the graph 400 of FIG. 4, the PR thickness corresponding to the maximum point 410 or the minimum point 430 of the graph 400 is selected. At these points 410 and 430, the CD effect due to variation in PR thickness in actual process or variation in patterning environment variable can be minimized.

Subsequently, a patterning process of forming, exposing and developing a process photoresist layer having a predetermined thickness is performed on the actual wafer on which the lower structure of the device pattern and the etching target layer are formed as shown in FIGS. 2 and 3 (FIG. 1). Of 170). The CD of the patterns according to the patterning result may be formed to have a more uniform line width since the thickness of the photoresist layer may be optimized to realize pattern uniformity.

According to the present invention described above, it is possible to secure the process margin of the transistor and the uniformity of the pattern critical line width (CD) which are employed in the DRAM or the logic device LSI. By using a real wafer that has been processed in real or equivalent processes, a CD variation graph according to the thickness change of the photoresist layer, that is, a PR sine curve, is derived to reflect the process state. The thickness of the layer can be selected. Therefore, CD fluctuation in an actual process can be suppressed more. More uniform CD uniformity can be obtained.

As mentioned above, although this invention was demonstrated in detail through the specific Example, it is not preferable that this invention is interpreted as limited to this. Embodiments of the invention are preferably to be interpreted as being provided to those skilled in the art to more fully describe the invention. In addition, it can be understood that the present invention can be modified or improved by those skilled in the art within the technical idea of the present invention.

Claims (3)

Forming the underlying structure of the actual device pattern and the actual etching target layer on the test wafer; Forming a test photoresist layer having different thicknesses on the test wafers; Performing exposure and development on the test photoresist layers; Measuring line widths of a pattern formed in the exposed and developed test photoresist layer; Calculating the measured line widths as a graph of a change in thickness of the test photoresist layers; Selecting the thickness located at the minimum or maximum point of the graph as the thickness of the process photoresist layer to be formed on the actual wafer; Forming a process photoresist layer having a predetermined thickness on an actual wafer on which a lower structure of the device pattern and an etching target layer are formed; And Exposing and developing the process photoresist layer. The method of claim 1, The etching target layer is a semiconductor device manufacturing method comprising a gate layer and a hard mask layer. The method of claim 1, The test wafer is a semiconductor device manufacturing method using a wafer that is processed in parallel with the actual wafer.

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