KR20080061602A - Semiconductor chip for tap pakage - Google Patents

Abstract

A semiconductor chip for a TAP(tape automated bonding) package is provided to increase misalignment tolerance of a chip pad and a lead caused by deformation of a circuit board by using chip pads with mutually different widths. Inner chip pads(222,223) are disposed on a semiconductor substrate(210), one-dimensionally arranged on a first column parallel with a first side of the semiconductor substrate. Outermost chip pads(221) are disposed on the semiconductor substrate, one-dimensionally arranged on a second column between the first column and the first side. When seen from a vertical cross section parallel with the first side, the inner chip pads have a greater width than that of the outermost chip pads. When seen from a lateral view facing the first side, the outermost chip pads can be positioned between the inner chip pads.

Description

Semiconductor chip for TAP package {semiconductor chip for TAP pakage}

1 is a plan view schematically illustrating a semiconductor device for describing a semiconductor chip for a tab package according to the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 is a plan view illustrating a semiconductor chip for a tab package according to the present invention.

** Description of the symbols for the main parts of the drawings **

100: semiconductor device

110: circuit board

120: lead

130: bond finger

140: bump

200: semiconductor chip

210: semiconductor substrate

220: Chip Pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip for tab packages, and more particularly to a semiconductor chip for tab packages having a plurality of rows of chip pads.

In general, with the rapid expansion of the market for personal portable communication products and liquid crystal display (LCD) products, the trend of miniaturization, thinning, and lightening of semiconductor packages has continued. One package type developed to cope with this trend is a package using a wiring film. For example, a tape carrier package (TCP), a chip-on-film (COF) package, and the like correspond to this. As such, the film-like package uses a bonding technique known as tap automated bonding (TAB) to realize the interconnection between the semiconductor chip and the circuit board.

However, with increasing integration and miniaturization of semiconductor integrated circuit chips, the number of chip pads formed on the chip surface increases, while the spacing between adjacent chip pads decreases. However, there is a limit to the number of chip pads that can be formed on a chip surface of a limited size, and the discovery between chip pads must be maintained at a certain level or more. Under these circumstances, one of the proposals for arranging as many chip pads as possible over a predetermined interval is a staggered arrangement of chip pads. In other words, since the zigzag arrangement is easy to implement fine pitch, the pitch of the chip pad is mainly applied to a product using a fine pitch of 30 μm or less.

On the other hand, as described above, the film-type package implements the interconnection using a bonding technique known as tap automated bonding (TAB), which is formed on bumps and circuit boards formed on chip pads. It is made by joining with the formed lead. Such bump and lead bonding is performed by a bonding tool applying a constant amount of heat and pressure to the junction of the bump and the lead. Happens. In this case, a misalignment may occur between the leads of the circuit board and the bumps of the chip pads due to the difference between the thermal strain of the circuit board and the thermal strain of the semiconductor chip.

However, as the pitch of the chip pads decreases, the size of the bumps bonded to the leads of the circuit board also decreases. Accordingly, the tolerance of misalignment caused by deformation of the circuit board when the bump and the lead are joined is reduced. That is, in the semiconductor package to which the zigzag arrangement method is applied, the bump size located inside the semiconductor chip is the same as the bump size located outside the semiconductor chip, thereby reducing the margin for misalignment.

An object of the present invention is to provide a semiconductor chip for a tab package having a chip pad having a width greater than that of the chip pad disposed on the outside.

In order to achieve the above object, a semiconductor package for a tab package according to the present invention includes a semiconductor substrate and an internal chip disposed one-dimensionally on a first column arranged on the semiconductor substrate and parallel to a first side of the semiconductor substrate. Pads; And outermost chip pads disposed on the semiconductor substrate and arranged one-dimensionally in a second row between the first row and the first side, wherein the inner chip pads are perpendicular to the first side. It has a larger width than the outermost chip pads when seen from a cross sectional view.

Preferably, the outermost chip pads may be located between the inner chip pads when viewed from a side view facing the first side, respectively.

Preferably, the semiconductor substrate may have a rectangular or square shape.

Preferably, the outermost chip pads and the inner chip pads may be made of aluminum or copper.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present embodiment is not limited to the embodiment disclosed below and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. Like numbers refer to like elements throughout.

1 is a plan view schematically illustrating a semiconductor device for describing a semiconductor chip for a tab package according to the present invention.

Referring to FIG. 1, the semiconductor device 100 includes a semiconductor chip 200 having a chip pad. The semiconductor chip 200 may be mounted on the circuit board 110. A plurality of bumps 140 are provided on the semiconductor chip 200. In addition, a plurality of parallel leads 120 are disposed on the circuit board 110. In addition, a bond finger 130 is disposed at a position in direct contact with the bump 140 and is a part of the lead 120. The semiconductor device 100 may include an LCD driver IC (LDI) package applied to a liquid crystal display device (LCD) or a DDI (PDP driver IC) package applied to a plasma display panel (PDP). Display Driver IC) package may be provided.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

Referring to FIG. 2, a semiconductor chip 200 having a chip pad 220 is provided. A bump 140 is attached to the chip pad 220. The chip pad 220 electrically connects the internal circuit of the semiconductor chip 200 and the external circuit board 110. The chip pad 220 may be an aluminum layer or a copper layer. In addition, the bump 140 may be one selected from the group consisting of gold, nickel, and copper.

The circuit board 110 may be a flexible circuit board made of an organic material that bends well such as polyimide. Also provided is a bond finger 130 disposed on the circuit board 110 and in contact with the bump 140. The bond finger 130, which is part of the lead 120, may be primarily a copper layer. In addition, the bond finger 130 may be plated with a tin layer. The bond fingers 130 are connected to each other by forming the bump 140 and the eutectic alloy.

After making this joint connection, this connection is sealed by an insulator such as under fill resin or non-conductive paste (NCP).

3 is a plan view illustrating a semiconductor chip for a tab package according to the present invention.

Referring to FIG. 3, a semiconductor chip 200 having a semiconductor substrate 210 is provided. The chip pads 220 disposed on the semiconductor substrate 210 have three rows. In this case, the first chip pad 221 is disposed around the edge of the semiconductor substrate 210. The first chip pad 221 is disposed in parallel to one side L1 of the adjacent semiconductor substrate 210. The second chip pad 222 is disposed inside the first chip pad 221. The width W2 of the second chip pad 222 is greater than the width W1 of the first chip pad 221. The second chip pad 222 is also disposed parallel to the first chip pad 221. In addition, a third chip pad 223 is disposed inside the second chip pad 222. The width W3 of the third chip pad 223 is larger than the width W2 of the second chip pad 222. In addition, the third chip pad 223 is disposed in parallel to the second chip pad 222.

That is, the width of the chip pad 220 disposed inside the edge of the semiconductor chip 200 is larger than the width of the chip pad 220 disposed outside.

In addition, the chip pad 220 is provided on the semiconductor chip 200 in a zigzag arrangement. In other words, the outermost chip pads 221 are located between the inner chip pads 222 and 223 when viewed from a side view facing the one side L1 of the semiconductor substrate 210, respectively.

 Although the chip pad 220 is provided in a zigzag arrangement, the first chip pad 221, the second chip pad 222, the third chip pad 223, the second chip pad 222, The first chip pads 221 may be sequentially disposed.

In addition, although the shape of the chip pad 220 has a rectangular shape in the drawing, the chip pad 220 may have a polygonal shape such as a triangle and a pentagon.

In addition, although the shape of the semiconductor chip 200 has a rectangular shape, the semiconductor chip 200 may have a square shape.

Meanwhile, the bumps 140 attached to the chip pads 220 having different areas may have different sizes. That is, the size of the bump 140 attached to the third chip pad 223 may be greater than that of the bump 140 attached to the second chip pad 222 and the first chip pad 221. . As a result, the bond finger 130, which is a part of the lead 120, may be more stably bonded to the bump 140 attached to the third chip pad 223.

In other words, even when the bond finger 140 of the lead 120 is inclined and aligned with the chip pad 220 of the semiconductor chip 200 due to the deformation of the circuit board 110, the width of the third chip pad 223 is increased. The width W2 of the second chip pad 222 is greater than the width W2 of the second chip pad 222, and the width W2 of the second chip pad 222 is greater than the width W1 of the first chip pad 221. Can be formed to minimize the risk of bonding failure.

That is, when the semiconductor chip 200 and the circuit board 110 are bonded to each other by forming the width of the chip pad 220 larger than the chip pad 220 disposed around the edge of the semiconductor chip 200. Due to the deformation of the circuit board 110, the margin of misalignment between the bond finger 140 of the circuit board 110 and the bump 140 of the chip pad 220 may be increased.

Although described in detail with respect to the preferred embodiment of the present invention as described above, those of ordinary skill in the art, without departing from the spirit and scope of the invention defined in the appended claims Various modifications may be made to the invention.

As described above, according to the present invention, the chip pads having different widths can increase the margin due to misalignment of the chip pads and leads due to deformation of the circuit board.

Claims (4)

Semiconductor substrates; Internal chip pads disposed on the semiconductor substrate and arranged one-dimensionally on a first row parallel to the first side of the semiconductor substrate; And And outermost chip pads disposed on the semiconductor substrate and arranged one-dimensionally in a second column between the first row and the first side, And the inner chip pads have a larger width than the outermost chip pads when viewed from a vertical cross-section parallel to the first side. The method of claim 1, Wherein the outermost chip pads are positioned between the inner chip pads when viewed from a side view facing the first side, respectively. The method of claim 1, The semiconductor substrate is a tab package semiconductor chip having a rectangular or square shape. The method of claim 1, The outermost chip pad and the inner chip pad are semiconductor chips for tab packages made of aluminum or copper.

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