KR20080061183A - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to move a common electrode adjacent to a data line toward a data line area, thereby improving the aperture ratio of a pixel area. A metal layer is formed on a substrate. Thereafter, a gate electrode, a gate line, a common electrode and the first storage electrode(106) are formed on the substrate by a photo-lithographic manner. A gate insulating layer, an amorphous silicon layer and a dope amorphous silicon layer are sequentially formed on the substrate and thereafter an organic insulating layer(120) is formed. The first organic insulating layer pattern is formed by the photo-lithographic manner including a diffraction mask or a half tone mask. A channel area is formed by the first organic insulating layer as a mask and the second organic insulating layer pattern is formed. A metal layer is formed on the substrate having the second organic insulating layer pattern and source/drain electrodes and a data line(105) are formed by the photo-lithographic manner. A passivation layer is formed on the substrate and a contact hole for exposing a portion of the drain electrode and the pad area is formed. A transparent conductive layer is formed on the substrate having the passivation layer and then the second storage electrode(107) and a pixel electrode(107a) are formed by the photo-lithographic manner.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

1 is a plan view illustrating a pixel structure of a transverse electric field type liquid crystal display device according to the related art.

2 is a plan view illustrating a pixel structure of a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

3A through 3F are cross-sectional views illustrating a manufacturing process of a transverse electric field type liquid crystal display device along the lines II ′ and II-II ′ of FIG. 2.

4A to 4F are cross-sectional views illustrating a manufacturing process of a transverse electric field type liquid crystal display device according to another exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

101: gate wiring 105: data wiring

101a: gate electrode 103: common wiring

103a: common electrode 120: organic insulating film

106: first storage electrode 107: second storage electrode

107a: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having improved pixel aperture ratio and a method of manufacturing the same.

In general, as the modern society changes to information socialization, the importance of the liquid crystal display (LCD) module, which is one of information display devices, is gradually increasing. Cathode ray tube (CRT), which is widely used so far, has many advantages in terms of performance and cost, but has many disadvantages in terms of miniaturization or portability.

In order to compensate for the shortcomings of the CRT, a liquid crystal display capable of realizing light and small, high brightness, large screen, low power consumption, and low cost has been developed. The liquid crystal display device not only has superior display resolution than other flat panel display devices, but also has a response characteristic that is faster in quality than a CRT when a moving image is realized.

Such a liquid crystal display device forms a electric field between a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate, and twists the liquid crystal interposed between the substrates, thereby displaying an image of a twisted nematic (TN: Twisted). The Nematic method is mainly used.

However, the liquid crystal display device using the twisted nematic method has a disadvantage that the viewing angle is very narrow.

Recently, in order to solve the narrow viewing angle problem, the development of a liquid crystal display device employing various new methods has been actively conducted. In this method, an in-plane switching mode (IPS) or an OCB method (optically) is used. compensated birefrigence mode).

Among these, the transverse electric field type liquid crystal display device forms two electrodes on the same substrate (lower substrate) in order to drive the liquid crystal molecules in a horizontal state with respect to the substrate, and applies a voltage between the two electrodes. The electric field is generated in the horizontal direction with respect to the substrate.

Therefore, in such a transverse electric field system, the long axis of the liquid crystal molecules does not stand in the direction perpendicular to the substrate (twist nematic method). For this reason, the birefringence change of the liquid crystal with respect to the visual direction is small, and has the viewing angle characteristic superior to the conventional TN type liquid crystal display device.

Hereinafter, a pixel structure of a transverse electric field type liquid crystal display device according to the related art will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a pixel structure of a transverse electric field type liquid crystal display device according to the related art.

Referring to FIG. 1, a pixel region is defined by crossing a gate wiring 1 and a data wiring 5, and a thin film transistor TFT which is a switching element is disposed in the crossing region. A region corresponding to the pixel region of the gate wiring 1 is formed to have a wide width to serve as the gate electrode 1a of the thin film transistor TFT.

In the pixel region, the common wiring 3 is formed to cross the data wiring 5 in a direction parallel to the gate wiring 1, branched from the common wiring 3 to the pixel region, and the data wiring ( The common electrode 3a is formed in the direction parallel to 5).

A first storage electrode 6 for forming a storage capacitor is formed at an edge of the common electrode 3a, that is, an area adjacent to the gate electrode 1a. The common wiring 3, the common electrode 3a, and the first storage electrode 6 form a closed loop in the pixel area.

A second storage electrode 7 electrically contacting the drain electrode of the thin film transistor TFT is formed on the first storage electrode 6, and a plurality of pixels are directed from the second storage electrode 7 toward the pixel region. The electrode 7a is branched.

In the pixel area, the common electrode 3a and the pixel electrode 7a are alternately formed at predetermined intervals, and the second storage electrode 7 and the pixel electrode 7a are both formed of a transparent conductive material.

However, in the conventional transverse electric field type liquid crystal display device, since the common electrode 3a is disposed in parallel in the region adjacent to the data line 5, the aperture ratio of the pixel region is reduced.

In addition, when the position of the common electrode 3a adjacent to the data line 5 is formed to overlap the data line 5 to improve the aperture ratio, the parasitic capacitance formed between the data line 5 and the common electrode 3a is increased. This causes a problem of deterioration of operating characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method for manufacturing the same in which the aperture ratio of the pixel region is improved by moving the common electrode adjacent to the data wiring to the data wiring region.

Another object of the present invention is to provide a liquid crystal display and a method of manufacturing the same, which minimize the parasitic capacitance generated between the data line and the common electrode by increasing the distance between the data line and the common electrode.

In order to achieve the above object, the liquid crystal display device manufacturing method according to the present invention,

Forming a metal film on the substrate and then performing an exposure and etching process using a photolithography method including a mask to form a gate electrode, a gate wiring, a common electrode, and a first storage electrode;

Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an organic insulating film;

Exposing and etching a photolithography method including a diffraction mask or a halftone mask on the substrate on which the organic insulating layer is formed to form a first organic insulating layer pattern;

Forming a channel region by etching the first organic insulating pattern as a mask, and forming a second organic insulating pattern;

Forming a metal film on the substrate on which the second organic insulating film pattern is formed, and then exposing and etching the photolithography method including a mask to form source / drain electrodes and data lines;

Forming a protective layer on the substrate on which the source / drain electrodes and the data line are formed, and forming a contact hole exposing a portion of the drain electrode and a pad region; And

Forming a second conductive electrode and a pixel electrode by forming a transparent conductive film on the substrate on which the protective film is formed, and then exposing and etching the photolithography method including a mask.

According to another embodiment of the present invention, a method of manufacturing a liquid crystal display device is provided.

Forming a metal film on the substrate and then performing an exposure and etching process to form a gate electrode, a gate wiring, a common electrode, and a first storage electrode;

Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an organic insulating film;

Exposing and etching a photolithography method including a diffraction mask or a halftone mask on the substrate on which the organic insulating layer is formed to form a first organic insulating layer pattern;

Forming a channel region by etching the first organic insulating pattern as a mask, and forming a second organic insulating pattern;

Forming a metal film on the substrate on which the second organic insulating film pattern is formed, and then exposing and etching the metal film to form source / drain electrodes and data lines;

A passivation layer is formed on the substrate on which the source / drain electrodes and the data line are formed, a photoresist is formed, and then exposed to form a photoresist pattern. The contact hole exposing a portion of the drain electrode and a pad region is formed using the mask. Doing; And

Forming a transparent conductive film on the substrate on which the photoresist pattern is formed, and then forming a second storage electrode and a pixel electrode by a lift-off process of removing the photoresist pattern with a strip solution.

According to another embodiment of the present invention,

Board;

Data wirings and gate wirings arranged crosswise to define pixel regions on the substrate;

A thin film transistor disposed at an intersection of the data line and the gate line;

A common electrode and a pixel electrode disposed alternately in the pixel region; And

The common electrode is formed on the substrate so that the data lines overlap, and the organic insulating layer is interposed between the common electrode overlapping the data lines and the data lines.

According to the present invention, the aperture ratio of the pixel region is improved by moving the common electrode adjacent to the data wiring to the data wiring region.

In addition, the present invention minimizes the parasitic capacitance generated between the data line and the common electrode by increasing the distance between the data line and the common electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a pixel structure of a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a pixel region is defined by crossing the gate wiring 101 and the data wiring 105, and a thin film transistor TFT which is a switching element is disposed in the crossing region. A region of the gate wiring 101 corresponding to the pixel region is formed to have a wide width to serve as the gate electrode 101a of the thin film transistor TFT.

The common wiring 103 is formed to cross the data wiring 105 in a direction parallel to the gate wiring 101 in the pixel region, and the common electrode 103a branches from the common wiring 103 to the pixel region. do. At this time, the common electrode 103a adjacent to the data line 105 among the common electrodes 103a branching from the common line 103 is formed under the data line 105 to overlap the data line 105.

Therefore, in the present invention, the aperture ratio of the pixel region is improved by making the common electrode formed in the pixel region adjacent to the data wiring overlap with the data wiring.

In addition, an organic insulating layer 120 such as photoacryl is formed under the data line 105 to minimize parasitic capacitance that may be generated due to overlap of the common electrode 103a and the data line 105. That is, the organic insulating film 120 is disposed between the data line 105 and the common electrode 103a to maximize the distance between the data line 105 and the common electrode 103a to minimize the size of the parasitic capacitance. The organic insulating layer 120 may use an organic insulating material having a small dielectric constant such as an acryl organic compound, Teflon, benzocyclobutene (BCB), cytotope (cytop), or perfluorocyclobutane (PFCB).

The first storage electrode 106 for forming a storage capacitor is formed at an edge of the common electrode 103a, that is, an area adjacent to the gate electrode 101a. The common wiring 103, the common electrode 103a, and the first storage electrode 106 form a closed loop in the pixel area.

A second storage electrode 107 is formed on the first storage electrode 106 to be in electrical contact with the drain electrode of the thin film transistor TFT, and a plurality of pixels are directed from the second storage electrode 107 toward the pixel region. The electrode 107a is branched.

In the pixel area, the common electrode 103a and the pixel electrode 107a are alternately formed at predetermined intervals, and the second storage electrode 107 and the pixel electrode 107a are both formed of a transparent conductive material.

The transparent conductive material may be indium-oxide (hereinafter referred to as "ITO"), indium-zinc-oxide (hereinafter referred to as "IZO"), or indium-tin-zinc-oxide. (Indium-Tin-Zinc-Oxide; hereafter referred to as "ITZO").

In the present invention, the organic insulating film 120 is formed below the data line 105 to reduce the parasitic capacitance due to overlap of the common electrode 103a and the data line 105.

In addition, the common electrode 103a adjacent to the data wiring 105 was moved to the data wiring 105 region to increase the aperture ratio of the pixel region.

3A to 3F are cross-sectional views illustrating a process of manufacturing a transverse electric field type liquid crystal table market value along lines II ′ and II-II ′ of FIG. 2.

As shown in Fig. 3A, the region I-I 'is a thin film transistor formation region, and the region II-II' is a data wiring formation region. After depositing a metal thin film on the insulating substrate 100, the gate wiring 101, the gate electrode 101a, the common electrode 103a, the common wiring (not shown) and the first by a photolithography method including a mask. The storage electrode 106 is formed.

Although not shown in the drawing, the common electrode 103a protrudes from the common wiring into the pixel area and is integrally formed with the first storage electrode 106. In the present invention, the common electrode 103a is formed in the region where the data wiring is to be formed to improve the aperture ratio of the pixel region.

As described above, when the gate wiring 101, the gate electrode 101a, and the like are formed, as shown in FIG. 3B, the gate insulating film 102, the amorphous silicon film 104, and the doped silicon oxide film are doped on the insulating substrate 100. After the amorphous silicon film 112 is formed sequentially, an organic insulating film is subsequently formed.

When the organic insulating film is formed on the insulating substrate 100 as described above, the exposure process is performed by using a diffraction mask or a halftone mask to form the first organic insulating pattern 200.

The first organic insulating pattern 200 is formed in a region where a channel region is to be formed and a region where a data line is to be formed, and has a predetermined step.

When the first organic insulating layer pattern 200 is formed as described above, as shown in FIG. 3C, the amorphous silicon layer 112 and the amorphous silicon layer 104 doped with the first organic insulating layer pattern 200 as a mask are used. Etch At this time, due to the etching process, the upper portion of the channel region is removed from the first organic insulating pattern, leaving only the second organic insulating pattern 200a. The second organic insulating pattern 200a exists only in the data line region. As shown in the region II-II ′, the amorphous silicon film 104, the doped amorphous silicon film 112, and the second organic insulating film pattern 200a are present on the common electrode 103a.

In addition, the amorphous silicon film 104 formed in the I-I 'channel region serves as a channel layer, and the doped amorphous silicon film 112 serves as an ohmic contact layer.

When the amorphous silicon film 104 and the doped amorphous silicon film 112 are patterned as described above, as shown in FIG. 3D, the insulating substrate 100 forms the aluminum, aluminum alloy, or copper-based metal film, and then a mask. It is etched by a photolithography method including a to form the source / drain electrodes (117a, 117b) and the data line 105.

The second organic insulating layer pattern 200a may be disposed under the data line 105 to secure the distance of the common electrode 103a. The organic insulating layer uses an acryl organic compound having a low dielectric constant, Teflon, benzocyclobutene (BCB), cytope, or perfluorocyclobutane (PFCB).

As described above, when the source / drain electrodes 117a and 117b are formed on the insulating substrate 100, as shown in FIG. 3E, the passivation layer 119 is formed on the entire region of the insulating substrate 100 and the mask is formed. The photolithography method includes etching a portion of the drain electrode 117b, a gate pad, and a data pad to expose a portion of the drain electrode 117b.

3F, a transparent conductive material such as ITO, ITZO, or IZO is formed on the insulating substrate 100 on which the protective film 119 is formed, and then a photolithography method including a mask is performed. The second storage electrode 107 and the pixel electrode 107a are formed by exposure and etching.

In the present invention, a common electrode adjacent to the data line among the common electrodes formed in the pixel area is formed under the data line to improve the aperture ratio of the pixel area. In addition, the parasitic capacitance between the data line and the common electrode, which will be generated due to the improvement of the pixel area aperture ratio, is minimized by inserting the organic insulating film pattern between the data line and the common electrode.

4A to 4F are cross-sectional views illustrating a manufacturing process of a transverse electric field type liquid crystal display device according to another exemplary embodiment of the present invention. The pixel structure is the same as that of FIG.

As shown in FIG. 4A, a metal thin film is deposited on the insulating substrate 300, and then the gate wiring 301, the gate electrode 301a, the common electrode 303a, and the common layer are formed by a photolithography method including a mask. A wiring (not shown) and the first storage electrode 306 are formed.

Although not shown in the drawing, the common electrode 303a protrudes from the common wiring to the pixel area and is integrally formed with the first storage electrode 306. In the present invention, the common electrode 303a is formed in the region where the data wiring is to be formed to improve the aperture ratio of the pixel region.

As described above, when the gate wiring 301, the gate electrode 301a, and the like are formed, as illustrated in FIG. 4B, the gate insulating layer 302, the amorphous silicon layer 304, and the doped doping layer are doped on the insulating substrate 300. After the amorphous silicon film 312 is formed sequentially, an organic insulating film is subsequently formed.

When the organic insulating film is formed on the insulating substrate 300 as described above, the exposure process is performed using a diffraction mask or a halftone mask to form the first organic insulating pattern 400.

The first organic insulating pattern 400 is formed in a region where a channel region is to be formed and a region where a data line is to be formed, and has a predetermined step.

When the first organic insulating layer pattern 400 is formed as described above, as shown in FIG. 4C, the doped amorphous silicon layer 312 and the amorphous silicon layer 304 are formed using the first organic insulating layer pattern 400 as a mask. Etch it. At this time, the upper portion of the channel region is removed from the first organic insulating pattern by the etching process, leaving only the second organic insulating pattern 400a. The second organic insulating pattern 400a is present only in the data line region. As illustrated, the amorphous silicon film 304, the doped amorphous silicon film 312, and the second organic insulating film pattern 400a are present on the common electrode 303a.

In addition, the amorphous silicon film 304 formed in the channel region serves as a channel layer, and the doped amorphous silicon film 312 serves as an ohmic contact layer.

When the amorphous silicon film 304 and the doped amorphous silicon film 312 are patterned as described above, as shown in FIG. 4D, the insulating substrate 300 forms the aluminum, aluminum alloy, or copper-based metal film, and then a mask. It is etched by a photolithography method including a to form the source / drain electrodes 317a, 317b and the data line 305.

A second organic insulating layer pattern 400a may be disposed under the data line 305 to secure the distance of the common electrode 303a. The organic insulating layer uses an acryl organic compound having a low dielectric constant, Teflon, benzocyclobutene (BCB), cytope, or perfluorocyclobutane (PFCB).

As described above, when the source / drain electrodes 317a and 317b are formed on the insulating substrate 300, as shown in FIG. 4E, the passivation layer 319 is formed on the entire region of the insulating substrate 300.

When the protective film 319 is formed on the insulating substrate 300 as described above, the photoresist is applied, and then exposed and developed using a mask to form the photoresist pattern 500.

When the photoresist pattern 500 is formed, an etching process is performed using the photoresist pattern 500 to expose a portion of the drain electrode 317b and expose a gate pad and a data pad. The photoresist pattern 500 may be provided in an area other than that of the protective layer 319. That is, the photoresist pattern 500 remains in the data line 305 region.

Then, a transparent conductive film 310 such as ITO, IZO, or ITZO is subsequently formed on the insulating substrate 300. The transparent conductive layer 310 is formed on the photoresist pattern 500 and on the passivation layer 319 formed in the exposed drain electrode 317b and the data line 305.

As described above, when the transparent conductive film 310 is formed on the insulating substrate 300, as shown in FIG. 4F, a strip solution is formed on the insulating substrate 300 by a lift-off process. The photoresist pattern, which has been formed, is removed.

When the lift-off process is performed as described above, while the photoresist pattern is removed by the strip solution, the transparent conductive film 310 formed on the photoresist pattern is removed. Therefore, in the transparent conductive film formed on the exposed drain electrode 317b, the second storage electrode 307 and the pixel electrode 307a are formed.

In addition, while the photoresist pattern formed in the area of the data line 305 is also removed, the transparent conductive film formed on the photoresist pattern is removed to expose the protective film 319.

In the present invention, a common electrode adjacent to the data line among the common electrodes formed in the pixel area is formed under the data line to improve the aperture ratio of the pixel area. In addition, the parasitic capacitance between the data line and the common electrode, which will be generated due to the improvement of the pixel area aperture ratio, is minimized by inserting the organic insulating film pattern between the data line and the common electrode.

As described in detail above, the present invention has the effect of improving the aperture ratio of the pixel region by moving the common electrode adjacent to the data wiring to the data wiring region.

In addition, the present invention has the effect of minimizing the parasitic capacitance generated between the data line and the common electrode by increasing the distance between the data line and the common electrode.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

Claims (15)

Forming a metal film on the substrate and then performing an exposure and etching process using a photolithography method including a mask to form a gate electrode, a gate wiring, a common electrode, and a first storage electrode; Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an organic insulating film; Exposing and etching a photolithography method including a diffraction mask or a halftone mask on the substrate on which the organic insulating layer is formed to form a first organic insulating layer pattern; Forming a channel region by etching the first organic insulating pattern as a mask, and forming a second organic insulating pattern; Forming a metal film on the substrate on which the second organic insulating film pattern is formed, and then exposing and etching the photolithography method including a mask to form source / drain electrodes and data lines; Forming a protective layer on the substrate on which the source / drain electrodes and the data line are formed, and forming a contact hole exposing a portion of the drain electrode and a pad region; And Forming a second conductive electrode and a pixel electrode by forming a transparent conductive film on the substrate on which the protective film is formed, and then exposing and etching the photolithography method including a mask. The method of claim 1, wherein the second organic insulating pattern is formed under the data line. The method of claim 1, wherein the common electrode is formed on a substrate under the data line. The method of claim 1, wherein the organic insulating layer is any one of an acryl organic compound, Teflon, BCB (benzocyclobutene), cytotope, or perfluorocyclobutane (PFCB). . The method of claim 1, wherein the transparent conductive film is one of ITO, IZO, or ITZO. Forming a metal film on the substrate and then performing an exposure and etching process to form a gate electrode, a gate wiring, a common electrode, and a first storage electrode; Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an organic insulating film; Forming a first organic insulating pattern by exposing and etching a photolithography method including a diffraction mask or a halftone mask on the substrate on which the organic insulating layer is formed; Forming a channel region by etching the first organic insulating pattern as a mask, and forming a second organic insulating pattern; Forming a metal film on the substrate on which the second organic insulating film pattern is formed, and then exposing and etching the metal film to form source / drain electrodes and data lines; A passivation layer is formed on the substrate on which the source / drain electrodes and the data line are formed, a photoresist is formed, and then exposed to form a photoresist pattern. The contact hole exposing a portion of the drain electrode and a pad region is formed using the mask. Doing; And Forming a second storage electrode and a pixel electrode in a lift-off process of forming a transparent conductive film on the substrate on which the photoresist pattern is formed, and then removing the photoresist pattern with a strip solution. The method of claim 6, wherein the second organic insulating pattern is formed under the data line. The method of claim 6, wherein the common electrode is formed on a substrate under the data line. The method of claim 6, wherein the organic insulating layer is any one of an acryl organic compound, Teflon, BCB (benzocyclobutene), cytotope, and perfluorocyclobutane (PFCB). . The method of claim 6, wherein the transparent conductive film is any one of ITO, IZO, and ITZO. Board; Data wirings and gate wirings arranged crosswise to define pixel regions on the substrate; A thin film transistor disposed at an intersection of the data line and the gate line; A common electrode and a pixel electrode disposed alternately in the pixel region; And And a common electrode formed on the substrate such that the data lines overlap, and an organic insulating layer interposed between the common electrode overlapping the data lines and the data lines. The liquid crystal display of claim 11, wherein the organic insulating layer is any one of an acryl organic compound, Teflon, BCB (benzocyclobutene), cytotope, and perfluorocyclobutane (PFCB). 12. The liquid crystal display device according to claim 11, wherein the pixel electrode is any one of ITO, IZO and ITZO. 12. The liquid crystal display device according to claim 11, wherein an organic insulating film is interposed below the data line. 12. The liquid crystal display device of claim 11, further comprising an amorphous silicon film and a doped amorphous silicon film between the data line and a common electrode formed under the data line.

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