KR20080060529A - Flat panel with a function of preventing a static electicity - Google Patents

Abstract

A flat display panel having a function of preventing static electricity is provided to enable pixels on a display area, which responds to a gate signal on a gate line, to charge a pixel data signal on a corresponding data line, thereby preventing the deterioration of an image displayed on an LCD(Liquid Crystal Display) panel. A flat display panel(10) having a function of preventing static electricity comprises pixels, static electricity prevention lines(ML), first MCs(Mute Cells), and second MCs. The pixels are connected to gate lines and data lines corresponding to each of areas divided by the gate lines and the data lines. The first MCs are respectively connected to the end or the other end of the gate lines to mute static electricity on a corresponding gate line to the static electricity prevention lines, and have at least one transistor(MT1,MT2,MT3). The second MCs are respectively connected to an end or the other end of the data lines to mute static electricity on a corresponding data line to the static electricity prevention lines, and have at least one second transistor(MT4,MT5,MT6). The first transistor has a channel of a smaller size than the channel of the second transistor.

Description

Flat Panel with a Function of Preventing a Static Electicity

1 is a block diagram schematically illustrating a liquid crystal display including a liquid crystal panel according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating the liquid crystal panel shown in FIG. 1 in detail.

≪A brief description of the main parts of the drawings≫

10 liquid crystal panel 12 gate driver

14: data driver 16: timing controller

100: display area 110: non-display area

112: peripheral circuit area 114: pad area

DL1 to DLm: data line DMC1 to DMC2m: data mute cell

DP1 to DPm: Data Pad GL1 to GLn: Gate Line

GMC1 to GMC2n: Gate mute cell GP1 to GPn: Gate pad

ML: Mute line MT, MT1 ~ MT6: Thin film transistor

The present invention relates to a flat panel for displaying an image, and more particularly to a flat panel having an antistatic function for preventing the inflow of static electricity.

Flat panel panels, such as liquid crystal panels, electro-luminescence display panels, and plasma display panels, enable lightweight and slim display devices. In addition, the flat panel facilitates the implementation of a large screen. Because of these advantages, flat panel panels are being used as display devices for computer systems, television receivers, and telecommunications devices in place of conventional cathode ray tubes.

Such a flat panel includes pixels arranged in an active trix, and a plurality of gate lines (or scan lines) and a plurality of data lines (or source lines) to enable scanning thereof. Multiple gate lines cause pixel cells to be selected line by line. The plurality of data lines cause the pixel data signal to be supplied to the selected pixel cells. The gate signal on the gate line has a larger swing width than the pixel data signal (or source signal) on the data line. This is because the data pixel voltage drives one pixel while the gate signal (or scan signal) drives one line of pixels.

In addition, a circuit for protecting the static electricity for protecting the pixels from static electricity is added to the flat panel. The antistatic circuit mutes the static electricity that will enter the pixel through the gate line and / or the data line so that the pixel is not damaged by the static electricity.

The antistatic circuit that mutes the static electricity may leak the current of the gate signal supplied to the pixels through the gate line. This is because although the voltage swing width of the gate signal is larger than that of the pixel data signal, the resistance component of the antistatic circuit is set constant regardless of the gate line and the data line. This leakage of gate signal current makes the pixel unable to respond accurately to the pixel data signal. For this reason, the image displayed on the flat panel may deteriorate. As a result, the image quality of the image displayed on the flat panel inevitably falls due to leakage of the gate signal current.

Accordingly, it is an object of the present invention to provide a flat panel having an antistatic function suitable for preventing leakage of signal current.

Another object of the present invention is to provide a flat panel suitable for displaying high quality images.

In accordance with an aspect of the present invention, there is provided a flat panel according to an embodiment of the present invention, wherein each of the regions divided by the gate lines and the data lines is connected to a corresponding gate line and a corresponding data line. Prevent wiring One of the first and the other ends of the first mute cells and the data lines having at least one first transistor connected to one of the one end and the other end of the gate line, respectively to mute the static electricity on the corresponding gate line; Two mute cells, each connected to either one, having at least one second transistor to mute the static electricity on the corresponding data line. The first transistor has a channel of a smaller size than the second transistor.

The channel of the first transistor may be formed at about 5/30 in the ratio of width / length.

The channel of the second transistor will be formed at about 10/20 in the ratio of width / length.

Each of the pixels includes a liquid crystal cell.

Other objects, other features, and other advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments associated with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a liquid crystal display including a liquid crystal panel according to an exemplary embodiment of the present invention. Referring to FIG. 1, the liquid crystal display includes a gate driver 12 connected to a plurality of gate lines GL1 to GLn on the liquid crystal panel 10 and a plurality of data lines DL1 to on the liquid crystal panel 10. A data driver 114 connected to the DLm). In the liquid crystal panel 10, a plurality of pixel regions arranged in an active matrix form are distinguished by crossing the gate lines GL1 to GLn and the data lines DL1 to DLm. Pixels are formed in each of the plurality of pixel regions. The pixel includes a thin film transistor MT connected to a corresponding gate line GL and a corresponding data line DL, and a liquid crystal cell CLC connected to the thin film transistor MT and a common electrode Vcom. . The thin film transistor MT switches the pixel data signal to be supplied to the corresponding liquid crystal cell CLC from the corresponding data line DL in response to a gate signal on the corresponding gate line GL.

The gate driver 12 sequentially enables a plurality of gate lines GL1 to GLn for one frame (period of one vertical synchronizing signal) sequentially by a predetermined period (for example, one horizontal synchronizing signal). Let's do it. To this end, the gate driver 12 generates a plurality of gate signals having exclusively enable pulses which are sequentially shifted for each period of the horizontal synchronization signal. The gate enable pulse included in each of the plurality of gate signals has the same width as the period of the horizontal synchronization signal. The enable pulse included in each of the plurality of gate scan signals is generated once every frame period. The gate signal maintains a voltage level of approximately -7V when disabled, while having a voltage level of approximately 15V when enabled. In other words, the gate signal has a swing width of approximately 22V. To generate these multiple gate scan signals, the gate driver 12 responds to gate control signals GCS. The gate control signals GCS include a gate start pulse GSP and a gate clock GSC. The gate start pulse GSP has a pulse of a specific logic (for example, high logic) corresponding to a period of one horizontal synchronization signal from the start of the frame period. The gate clock GSC has the same period as the horizontal synchronization signal.

The data driver 14 corresponds to the number of data lines DL1 to DLm whenever one of the plurality of gate lines GL1 to GLn is enabled (that is, the number of pixels arranged in one gate line). Generate pixel data signals). Each pixel data signal of one line is supplied to a corresponding pixel (ie, a liquid crystal cell) on the liquid crystal panel 10 via a corresponding data line DL. Each of the pixels arranged on the gate line GL passes an amount of light corresponding to a voltage level of the pixel data signal. In order to generate pixel data signals for one line, the data driver 14 sequentially generates one line of pixel data for each period of the enable pulse included in the gate signal in response to the data control signal DCS. Enter it. The data driver 14 simultaneously converts sequentially input pixel data for one line into a pixel data signal in analog form. The pixel data signal has a voltage level of approximately 0V to 4.5V. In other words, the pixel data signal has a significantly lower voltage than the gate signal.

The gate driver 12 and the data driver 14 are controlled by the timing controller 16. The timing controller 16 inputs the synchronization signals SYNC from an external video data source (for example, an image demodulation module included in a television receiving module or a graphics module included in a computer system) not shown. The sync signals SYNC include a data clock Dclk, a data enable signal DE, a horizontal sync signal Hsync, a vertical sync signal Vsync, and the like. The timing controller 16 uses the synchronization signals SYNC to allow the gate driver 12 to sequentially scan the plurality of gate lines GL1 to GLn on the liquid crystal panel 10 every frame. The gate control signals GCS required to generate a plurality of gate signals are generated. In addition, the timing controller 16 sequentially inputs one line of pixel data VDs to the data driver 12 every cycle in which the gate line GL is enabled, and sequentially inputs one line of pixel data VDs. It generates data control signals DCS necessary for converting and outputting pixel data into a pixel data signal in an analog form. Further, the timing controller 16 inputs a pixel data stream VDf divided in units of frames (one image unit) from a video data source. The timing controller 16 divides the pixel data stream VDf for each frame into the pixel data stream VDs for each line, and divides the pixel data stream VDs for the divided line to the data driver 14. Supply.

FIG. 2 is a circuit diagram showing in detail the liquid crystal panel shown in FIG. The liquid crystal panel 10 of FIG. 2 is divided into a display area 100 positioned at the center and a non-display area 110 surrounding the display area 100. As illustrated in FIG. 1, pixels including the thin film transistor MT and the liquid crystal cell CLC are arranged in an active matrix in the display area 100.

The non-display area 110 includes a peripheral circuit area (or wiring area) 112 positioned outside the display area 100 and a pad area 114 extending upward and leftward from the peripheral circuit area 112. Separated by. An antistatic circuit is disposed in the peripheral circuit region 112. The antistatic circuit may include n first gate mute cells GMC11 to GMC1n and the gate line electrically connected to one ends of the gate lines GL1 to GLn toward the gate pads GP1 to GPn. N second gate mute cells GMC21 to GMC2n electrically connected to the other ends of the fields GL1 to GLn. In addition, the antistatic circuit includes: m first data mute cells DMC11 to DMC1m electrically connected to one end of each of the data lines GL1 to GLn toward the data pads DP1 to DPm; And m second data mute cells DMC21 to DMC2m electrically connected to the other ends of the data lines DL1 to DLm. The mute line ML is connected to a voltage source (not shown) of "0V".

At least two tape carriers in which the gate driver 12 and the data driver 14 are disposed or one of the gate driver 12 and the data driver 14 is mounted in the pad region 114, respectively. The Tape Carrier Package is electrically connected. To this end, gate pads GP1 to DPn and data pads DP1 to DPm that are electrically connected to the gate and data drivers 12 and 14 are formed in the pad region 114. Each of the pads 114A and 114B is electrically connected to a corresponding gate line GL1 to GLn or data lines DL1 to DLm from the display area 100.

The first and second gate mute cells GMC11 to GMC2n discharge high-potential positive or negative static electricity flowing into the corresponding gate line GL from the outside toward the mute line ML. To this end, each of the first and second gate mute cells GMC11 to GMC2n includes first and second thin film transistors MT1 and MT2 connected in series between a corresponding gate line GL and the mute line ML. And a third thin film transistor MT3 responsive to a voltage on a connection point between these thin film transistors MT1 and MT2. The first thin film transistor MT1 has a gate terminal and a source terminal commonly connected to the mute line ML, and the second thin film transistor MT2 has a gate commonly connected to a corresponding gate line GL. Terminal and drain terminal. The first and second thin film transistors MT1 and MT2 divide a difference voltage between a voltage on a corresponding gate line GL and a voltage on the mute line ML, and divide the divided voltage into the third thin film transistor ( Supply to the gate terminal of MT3). In other words, the first and second thin film transistors MT1 and MT2 perform a function of a resistor constituting a voltage divider. The third thin film transistor MT3 has a corresponding gate line GL and the mute line ML depending on whether the voltage divided by the first and second thin film transistors MT1 and MT2 is higher or lower than its threshold voltage. Open and close the current path between When the voltage divided by the first and second thin film transistors MT1 and MT2 is higher than a threshold voltage, the third thin film transistor MT3 connects the corresponding gate line GL to the mute line ML. . At this time, high-potential positive or negative static electricity on the corresponding gate line GL is discharged toward the mute line ML, so that one line of pixels in the display area connected to the corresponding gate line GL are discharged. (Ie, the thin film transistors MT) are not damaged by static electricity. To this end, the first and second thin film transistors MT1 and MT2 may have a third voltage in a level range between voltages (ie, −7 V and +15 V) of the negative and positive gate signals on the corresponding gate line GL. In order to supply a voltage equal to or lower than the threshold voltage (ie, 0.7) of the thin film transistor MT3, the resistance values of the voltage division ratio are set to have relatively large resistance values. In order to have a relatively large resistance value, the first and second thin film transistors MT1 and MT2 have channels of a relatively small size. For example, the first and second thin film transistors MT1 and MT2 have channels having a width / length ratio of 5/30. The first and second thin film transistors MT1 and MT2 of the relatively small channel prevent the negative and positive gate signals from leaking toward the mute line ML. The gate signal on the gate line GL, which is not thus leaked, allows the pixels on the display area 100 to accurately charge the pixel data signal. Thereby, the image displayed on the liquid crystal panel 10 will not deteriorate. As a result, the liquid crystal panel according to the present invention can display high quality images.

The first and second data mute cells DMC11 to DMC2m discharge the high potential positive or negative static electricity flowing into the corresponding data line DL from the outside toward the mute line ML. To this end, each of the first and second data mute cells DMC11 to DMC2m includes fourth and fifth thin film transistors MT4 and MT5 connected in series between a corresponding data line DL and the mute line ML. And a sixth thin film transistor MT6 responsive to the voltage on the connection point between these thin film transistors MT4 and MT5. The fourth thin film transistor MT4 includes a gate terminal and a source terminal commonly connected to the mute line ML, and the fifth thin film transistor MT5 is commonly connected to a corresponding data line DL. Terminal and drain terminal. The fourth and fifth thin film transistors MT1 and MT2 divide a voltage difference between a voltage on a corresponding data line DL and a voltage on the mute line ML, and divide the divided voltage into the sixth thin film transistor. Supply to the gate terminal of MT6). In other words, the fourth and fifth thin film transistors MT4 and MT6 perform a function of a resistor constituting a voltage divider. The sixth thin film transistor MT6 has a corresponding data line DL and the mute line ML depending on whether the voltage divided by the fourth and fifth thin film transistors MT4 and MT5 is higher or lower than its threshold voltage. Open and close the current path between When the voltage divided by the fourth and fifth thin film transistors MT4 and MT5 is higher than a threshold voltage, the sixth thin film transistor MT6 connects the corresponding data line DL to the mute line ML. . At this time, high-potential positive or negative static electricity on the corresponding data line DL is discharged toward the mute line ML, so that one column of pixels in the display area connected to the corresponding data line GL are discharged. (Ie, the thin film transistors MT) are not damaged by static electricity. For this purpose, the fourth and fifth thin film transistors MT4 and MT5 may have threshold voltages of the sixth thin film transistor MT6 in the level range of the pixel data signal on the corresponding data line DL (ie, 0V to 4.5V). That is, it is set to have the resistance values of the voltage dividing ratio so that a voltage of 0.7) or less can be supplied, but have relatively small resistance values. The fourth and fifth thin film transistors MT1 and MT2 having a relatively small resistance value easily discharge static electricity lower than the voltage of the gate signal and higher than the pixel data signal on the data line DL toward the mute line ML. In order to have a relatively small resistance value, the fourth and fifth thin film transistors MT4 and MT5 have channels of a relatively large size. For example, the fourth and fifth thin film transistors MT4 and MT5 have channels having a width / length ratio of 10/20.

As described above, in the antistatic function liquid crystal panel according to the present invention, the mute cells connected to the gate line include transistors of a relatively small channel as compared with the transistors constituting the mute cell connected to the data line. Relatively small channel transistors can minimize or prevent current in the gate signal from leaking from the gate line toward the mute line. Thus, the pixels on the display area responsive to the gate signal on the gate line can accurately charge the pixel data signal on the corresponding data line. Thereby, the image displayed on the liquid crystal panel 10 will not deteriorate. As a result, the liquid crystal panel according to the present invention can display high quality images.

As described above, the present invention has been described with reference to the liquid crystal panel shown in FIG. 2, but a person having ordinary knowledge in the technical field to which the present invention belongs does not depart from the spirit and scope of the present invention. It will be apparent that other variations and equivalent embodiments are possible. For example, the present invention may be applied to an EL display panel including an EL pixel formed in each of pixel regions divided by a plurality of gate lines (or scan lines) and a plurality of data lines (or source lines). . Accordingly, the technical scope and features of the present invention should not be limited to the description of the embodiments, but should be set by the matters set forth in the appended claims.

Claims (4)

Pixels formed to be connected to the corresponding gate line and the corresponding data line in each of the regions divided by the gate lines and the data lines. Antistatic wiring First mute cells connected to either one of the one or the other of the gate lines, the first mute cells having at least one first transistor to mute the static electricity on a corresponding gate line; and Second mute cells having at least one second transistor connected to either one of the one or the other of the data lines, respectively, to mute the static electricity on the corresponding data line, And the first transistor has a channel having a smaller size than that of the second transistor. The method of claim 1, The channel of the first transistor is a flat panel of the anti-static function, characterized in that formed in about 5/30 in the ratio of width / length. The method of claim 2, The channel of the second transistor is formed of about 10/20 in the width / length ratio of the anti-static flat panel panel. The method of claim 3, wherein And each of the pixels comprises a liquid crystal cell.

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