KR20080060397A - Liquid crystal display device - Google Patents

Abstract

An LCD is provided to contact a part of a lower surface of a sealant with a passivation layer and contact the rest part with an insulating layer, thereby preventing bonding faults between upper and lower substrates. An LCD(Liquid Crystal Display) comprises a lower substrate(10), an upper substrate(50), a sealant(60) and LC(70). The lower substrate comprises the followings. A TFT(Thin Film Transistor)(20) is arranged in a screen display area in a matrix form. An insulating layer(22,24) covers from the screen display area to a peripheral area surrounding the screen display area. A passivation layer(30) is formed from the screen display area to a partial part of the peripheral area and covers the TFT. A pixel electrode(40) is disposed on the passivation layer and electrically connected with the TFT. The upper substrate includes a color filter(54) disposed in correspondence with each pixel, and disposed so as to face the lower substrate. A part of the sealant is contacted with the passivation layer. The rest part of the sealant is disposed in the peripheral area so as to be contacted with the insulating layer. The sealant bonds the lower and upper substrates. The LC is injected between the lower and upper substrates.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a cross-sectional view of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the lower substrate shown in FIG. 1.

3 is a cross-sectional view of a liquid crystal display device according to a second embodiment of the present invention.

The present invention relates to a liquid crystal display device. More specifically, the present invention relates to a liquid crystal display device which prevents poor bonding between the upper substrate and the lower substrate and uneven cell gap.

Recently, with the rapid development of the information society, the necessity of a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption has emerged.

Examples of the representative display device include a liquid crystal display device, an organic light generating device, a plasma display device, and the like. Dual liquid crystal display devices are being actively applied to notebooks and desktop monitors because of their excellent resolution, color display, and image quality.

The liquid crystal display includes a thin film transistor as a switching element, a lower substrate on which a pixel electrode is formed, a lower substrate, and an upper substrate on which a color filter and a common electrode are formed, and a liquid crystal injected between the lower substrate and the upper substrate.

The thin film transistor and the pixel electrode are formed in each pixel arranged in a matrix in the active area of the lower substrate. The thin film transistor used as the switching element includes a gate electrode, an insulating film, an active and a source / drain electrode, and the pixel electrode is electrically connected to the drain electrode. A protective film is formed on the pixel electrode including the thin film transistor to cover and protect the pixel.

Meanwhile, the color filters formed on the upper substrate include red, green, and blue color filters, each color filter corresponding to the pixel, and a common electrode formed on the entire upper substrate.

In order to inject the liquid crystal between the lower substrate and the upper substrate configured as described above, they are attached to each other. First, a sealant cured by light is applied to a peripheral region provided at an edge of the lower substrate so as to surround the screen display area. Then, the surface on which the common electrode and the color filter are formed on the upper substrate is positioned to face the surface on which the thin film transistor and the pixel electrode of the lower substrate are formed, and then the sealant is cured to attach the lower substrate and the upper substrate to each other.

However, in the related art, since the bonding force between the protective film formed of the photoacryl containing photosensitive material and the sealant is low, the protective film is formed only in the screen display area, and the sealant is formed in the peripheral area spaced apart from the protective film. As a result, a gap is generated between the sealant and the passivation layer. When the temperature of the liquid crystal increases due to the driving of the liquid crystal display, an absolute amount of liquid crystal increases in a portion where the gap is generated, thereby causing a stain.

In order to solve this problem, when the protective film is formed to extend to the peripheral region, a low bonding force between the protective film and the sealant may cause a poor bonding between the upper and lower substrates, and in some cases, the upper and lower substrates may be peeled off. have.

One object of the present invention is to provide a liquid crystal display device which prevents a poor bonding between the upper substrate and the lower substrate and prevents cell gap staining between screen display filtration and peripheral regions.

A liquid crystal display substrate for implementing one object of the present invention includes a thin film transistor arranged in a matrix form on the screen display area, an insulating film covering the screen display area from a peripheral area surrounding the screen display area, and the screen display area. A lower layer including a passivation layer formed from a portion of the peripheral region to cover the thin film transistor, a lower substrate including a pixel electrode disposed on the passivation layer and electrically connected to the thin film transistor, and a color filter disposed corresponding to each pixel. An upper substrate disposed to face the lower substrate, a portion of the upper substrate which is in contact with the protective layer, and a portion of which is disposed in the peripheral region so as to contact the insulating layer, and a sealant and the lower substrate which bond the lower substrate and the upper substrate; Injection between the upper substrate It comprises a liquid crystal.

Hereinafter, a liquid crystal display according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments. The present invention may be embodied in various other forms without departing from the spirit of the invention.

LCD Display

Example  One

FIG. 1 is a cross-sectional view of a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a plan view of the lower substrate shown in FIG.

Referring to FIG. 1, the liquid crystal display device 100 includes a lower substrate 10, an upper substrate 50, a sealant 60, and a liquid crystal layer 70.

Referring to FIG. 2, the lower substrate 10 is disposed on the screen display area 12 on which an image is displayed and on an outer side of the screen display area 12, surrounding the screen display area 12, and the peripheral area where the screen is not displayed. 114, the sealant forming region 16 formed in the peripheral region 14 and the sealant forming region 16 in which the sealant 250 is disposed and extending from the screen display region 12 to a part of the sealant forming region 16 inwardly. ). The sealant formation region 16 is formed at a predetermined width toward the edge of the lower substrate 10 at the boundary between the screen display region 12 and the peripheral region 14.

The thin film transistor 20, the passivation layer 30, and the pixel electrode 40 connected to the signal line (not shown) are formed on the upper surface of the lower substrate 10 divided as described above.

Although not shown, the signal lines include, for example, gate signal lines formed to extend in the horizontal direction of the lower substrate 10 so as to intersect the entire screen display area 12 from the peripheral region 14, and data signal lines formed to intersect the gate signal lines. Include. In the present exemplary embodiment, when the resolution of the liquid crystal display device is 1,024 × 768, 768 gate signal lines are arranged on the lower substrate 10 in parallel, and 1,024 × 3 second signal lines are arranged in parallel.

Pixels are provided in an area where the gate signal line intersects the data signal line. In the present embodiment, when the resolution of the liquid crystal display device is 1,024 × 768, 1,024 × 3 pixels are arranged in a matrix form in the screen display area.

The thin film transistor 20 and the pixel electrode 40 are formed in each pixel formed as described above. The thin film transistor 20 includes a channel layer 21, a first insulating film 22, a gate electrode 23, and a second insulating film. 24 and source and drain electrodes 25 and 26.

The channel layer 21 is divided into an impurity region 21a and an active region 21b and is formed on the upper surface of the lower substrate 10. The impurity region is formed by implanting ions into the channel layer and is formed at both edges of the channel layer. The active region is formed between the impurity regions, that is, in the central portion of the channel layer.

The first insulating layer 22 is disposed on the channel layer 21. The first insulating layer 22 covers the entire screen display area 12 including the channel layer 21 and the entire peripheral area 14. A first contact hole for exposing the impurity region 21a to the outside of the first insulating layer 22 is formed in a portion of the first insulating layer 22 corresponding to each impurity region 21a. In this embodiment, examples of the material used as the first insulating film 22 include silicon oxide, silicon nitride, and the like.

The gate electrode 23 is disposed to correspond to the active region 21b of the channel layer 21 of the upper surface of the first insulating layer 22.

The second insulating layer 24 is disposed on the gate electrode 23, and covers the entire screen display area 12 including the gate electrode 23 and the entire peripheral area 14. A second contact hole exposing the impurity region 21a is formed in a portion of the second insulating layer 24 corresponding to the first contact hole. In this embodiment, examples of the material used as the second insulating film 24 include silicon oxide, silicon nitride, and the like.

The source and drain electrodes 25 and 26 are formed spaced apart from each other on the upper surface of the second insulating film 24. The source electrode 25 is formed from a data signal line to a portion corresponding to one end of the gate electrode 23 and is connected to the impurity region 21a of the channel layer 21 through the first and second contact holes. The drain electrode 26 overlaps the other end of the gate electrode 23 and is connected to the impurity region 21a of the channel layer 21 through the first and second contact holes.

The passivation layer 210 is formed on the source and drain electrodes 25 and 26 to cover the thin film transistor 200. The passivation layer 210 extends from the screen display area 12 to a predetermined portion of the sealant formation area 16. It is formed to cover the entire formation region 18.

A contact hole is formed in a portion of the passivation layer 30 covering the entire passivation layer formation region 18 corresponding to the drain electrode 26. In this embodiment, an example of the material used as the protective film 30 may be photo acrylic including a photosensitive material.

The pixel electrode 40 is disposed on the passivation layer 30 and electrically connected to the drain electrode 26 through a contact hole formed in the passivation layer 30.

Examples of the material that can be used for the pixel electrode 40 include tin indium oxide (ITO), zinc indium oxide (IZO), amorphous tin indium oxide (a-ITO), and the like.

The manufacturing process of the thin film transistor 20, the passivation layer 30, and the pixel electrode 40 will be briefly described. First, the channel layer 21 made of polysilicon on the upper surface of the lower substrate 10 is described. ).

The first insulating layer 22 covering the channel layer 21 is formed over the entire upper surface of the lower substrate 10, and the gate corresponds to the center of the channel layer 21 among the upper surfaces of the gate insulating layer 22. The electrode 23 is formed.

Subsequently, impurity ions are implanted into the entire lower substrate 10 using the gate electrode 23 as an ion implantation mask. Then, impurity regions 21a implanted with impurity ions are formed at both edges of the channel layer 21 exposed to the outside of the gate electrode 23, and correspond to the impurity regions 21a, that is, the gate electrode 23. The active area 22a is formed in the part to become.

Thereafter, a second insulating film 24 covering the gate electrode 23 is formed on the entire surface of the lower substrate 10, and the first insulating film 22 and the second insulating film 24 are patterned to form impurities in the channel layer 21. First and second contact holes exposing the impurity region 21a are formed in a portion corresponding to the region 21a.

When the first and second contact holes are formed, the source / drain metal is deposited on the second insulating layer 24, and the source / drain metal is patterned to form impurities in the channel layer 21 through the first and second contact holes. The thin film transistor 20 is manufactured by forming the source and drain electrodes 25 and 26 in contact with the region 21a.

Thereafter, a passivation layer 30 that protects the thin film transistor 20 is formed on the source and drain electrodes 25 and 26, and the passivation layer 30 is formed on the screen display area 12 of the sealant forming region 16. It is formed to cover the entire protective film forming region 18 extending inwardly to a predetermined portion. When the passivation layer 30 is formed, the passivation layer 30 is patterned to form contact holes in portions corresponding to the drain electrodes 26.

Next, a transparent metal is deposited on the upper surface of the passivation layer 30, and the transparent metal is patterned to form a pixel electrode 40 connected to the drain electrode 26 through a contact hole in each pixel.

Referring back to FIG. 1, one surface of the upper substrate 50, that is, the surface facing the upper substrate, corresponds to a portion corresponding to the data and gate signal lines, a portion corresponding to the thin film transistor 20, and a peripheral region 14. Between the black matrix pattern 52 and the black matrix pattern 52 formed at the portion to block light, that is, the red, green and red color filters 54 and the upper substrate 50 formed at the portion corresponding to each pixel. The common electrode 56 is formed to cover the entire surface and apply a voltage to the liquid crystal layer 70 together with the pixel electrode 20.

The upper substrate 50 is disposed to face the lower substrate 10, and one surface on which the black matrix pattern 52, the color filter 54, and the common electrode 56 are formed is disposed on the thin film transistor 20 on the lower substrate 10. And an upper surface of the pixel electrode 40 formed thereon.

The sealant 60 is disposed between the upper substrate 50 and the lower substrate 10 to bond the upper substrate 50 and the lower substrate 10. The sealant 60 is disposed in the sealant formation region 16 located in the peripheral region 14 in the lower substrate 10. Accordingly, the lower surface of the sealant 60, which is in contact with the lower substrate 10, is partially in contact with the passivation layer 30, and the other portion of the sealant 60 is in contact with the second insulating layer 24.

When a portion of the lower surface of the sealant 60 comes into contact with the passivation layer 30 as in the present embodiment, no gap is generated between the sealant 60 and the passivation layer 10. Even if the temperature of the layer 70 increases, staining does not occur at the boundary between the screen display area 12 and the peripheral area 14.

In addition, the lower surface of the sealant 60 is formed of photo acryl to contact only the portion of the sealant 60 and the protective layer 30 having weak adhesion, and the second portion of the second insulating layer formed of silicon nitride having excellent adhesion to the sealant 60. The contact force of the upper substrate 50 and the lower substrate 10 is also increased because of contact with the (24).

According to the present exemplary embodiment, the bonding area between the upper substrate 50 and the lower substrate 10 is increased as the area of the lower surface of the sealant 60 in contact with the second insulating layer 202 is larger than the area in contact with the protective film 30. Can be. Therefore, it is most preferable that the protective film 30 formed inward of the sealant formation region 16 does not exceed 50% of the area of the sealant formation region 16.

Referring to FIG. 1, the liquid crystal layer 70 is disposed between the upper substrate 50 and the lower substrate 10 bonded by the sealant 60.

Example  2

3 is a cross-sectional view of a liquid crystal display device according to a second embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display 300 includes a lower substrate 10, an upper substrate 250, a sealant 260, and a liquid crystal 270.

Referring to FIG. 2, the lower substrate 10 is disposed outside the screen display area 12 and the screen display area 12 where an image is displayed, and surrounds the screen display area 12 and the peripheral area where the screen is not displayed. 114, a sealant forming region 16 formed in the peripheral region 14 and extending from the screen display region 12 to a portion of the sealant forming region 16 to the inside of the sealant forming region 16. 18). The sealant formation region 16 is formed at a predetermined width toward the edge of the lower substrate 10 at the boundary between the screen display region 12 and the peripheral region 14.

The thin film transistor 200, the passivation layer 210, and the pixel electrode 220 connected to the signal line (not shown) are formed on the upper surface of the lower substrate 10 divided as described above.

Although not shown, the signal lines include, for example, gate signal lines formed to extend in the horizontal direction of the lower substrate 10 so as to intersect the entire screen display area 12 from the peripheral region 14, and data signal lines formed to intersect the gate signal lines. Include. In the present embodiment, when the resolution of the liquid crystal display device is 1,024 × 768, 768 gate signal lines are arranged in parallel on the lower substrate 10, and 1,024 × 3 are arranged in parallel in the second signal line.

Pixels are provided in an area where the gate signal line intersects the data signal line. In the present embodiment, when the resolution of the liquid crystal display device is 1,024 × 768, 1,024 × 3 pixels are arranged in a matrix form in the screen display area.

The thin film transistor 200 and the pixel electrode 220 are formed in each pixel formed as described above. The thin film transistor includes a gate electrode 201, a gate insulating film 202, a channel layer 203, a source and a drain electrode 204. 205).

The gate electrode 201 is formed on the upper surface of the lower substrate 10 and is connected to the gate signal line. The gate insulating layer 202 is disposed on the gate electrode 201 and the gate signal line, and covers the entire screen display area 12 and the peripheral area 14 including the gate electrode 201 and the gate signal line.

In this embodiment, examples of the material used as the gate insulating film 202 include silicon oxide, silicon nitride, and the like.

The channel layer 203 is disposed on the gate insulating film 202. Referring to FIG. 3, the channel layer 203 includes an amorphous silicon layer 203a and an n + amorphous silicon layer 203b formed on an upper surface of the amorphous silicon layer 203a. The amorphous silicon layer 203a is patterned to have a larger area than the gate electrode 201 on the gate insulating film 202 to cover the gate electrode 201. The n + amorphous silicon layer 203b is formed with the same area as the area of the amorphous silicon layer 203a, and an opening for exposing the amorphous silicon layer 203a is formed in the center portion.

The source and drain electrodes 204 and 205 are formed on the top surface of the n + amorphous silicon layer 203b, for example, when the n + amorphous silicon layer 203b is patterned, the source and drain electrodes 204 and 205 together. Patterned to have the same shape as the n + amorphous silicon layer 203b. That is, the source electrode 204 is overlapped with one end of the gate electrode 201 based on the opening formed between the source and drain electrodes 204 and 205 and connected to the data electrode, and the gate electrode (based on the opening) The portion overlapping the other end of the 201 and connected to the pixel electrode 220 becomes the drain electrode 205.

The passivation layer 210 is formed on the top surfaces of the source and drain electrodes 204 and 205 to cover the thin film transistor 200, and extends from the screen display area 12 to a predetermined portion inward of the sealant formation area 16. The protective film forming region 18 is formed so as to cover the whole.

A contact hole is formed in a portion of the passivation layer 210 covering the entire passivation layer formation region 18 corresponding to the drain electrode 205. In this embodiment, an example of the material used as the protective film 210 may be photo acrylic including a photosensitive material.

The pixel electrode 220 is disposed on the passivation layer 210 and electrically connected to the drain electrode 205 through a contact hole formed in the passivation layer 210.

Examples of the material that can be used for the pixel electrode 220 include tin indium oxide (ITO), zinc indium oxide (IZO), amorphous tin indium oxide (a-ITO), and the like.

The manufacturing process of the thin film transistor 200, the passivation layer 210, and the pixel electrode 220 will be described in detail. First, a gate metal is deposited on the entire upper surface of the lower substrate, and the gate metal is patterned to form a gate signal line and a screen. A gate electrode branched from the gate signal line is formed in the display area 12.

Thereafter, a gate insulating film 202 covering the gate signal line and the gate electrode 201 is formed over the entire upper surface of the lower substrate.

Subsequently, amorphous silicon, n + amorphous silicon and source / drain metal are sequentially deposited on the gate insulating film 202, and the amorphous silicon, n + amorphous silicon and source / drain metal are patterned at a time. Then, a channel layer 203 including an amorphous silicon layer 203a and an n + amorphous silicon layer 203b having an opening formed in the center is formed on the gate insulating layer 202, and a source and an upper portion of the channel layer 203 are formed. Drain electrodes 204 and 205 are formed to manufacture thin film transistor 200.

Thereafter, a passivation layer 210 that protects the thin film transistor 200 is formed on the source and drain electrodes 204 and 205, and the passivation layer 210 is formed inside the sealant formation region 16 in the screen display area 12. It is formed so as to cover the entire protective film forming region 18 extending to a predetermined portion. When the passivation layer 210 is formed, the passivation layer 210 is patterned to form contact holes in portions corresponding to the drain electrodes 205.

Next, a transparent metal is deposited on the upper surface of the passivation layer 210, and the transparent metal is patterned to form a pixel electrode 220 connected to the drain electrode 205 through a contact hole in each pixel.

Referring back to FIG. 3, one surface of the upper substrate 250, that is, the surface facing the upper substrate 250, corresponds to a portion corresponding to the data and gate signal lines, a portion corresponding to the thin film transistor 200, and a peripheral region 14. Between the black matrix pattern 252 and the black matrix pattern 252 formed at the portion to block light, that is, the red, green, red color filter 254 and the upper substrate 250 formed at the portion corresponding to each pixel. The common electrode 256 is formed to cover the entire surface and apply a voltage to the liquid crystal 270 together with the pixel electrode 220.

The upper substrate 250 is disposed to face the lower substrate 10, and one surface on which the black matrix pattern 252, the color filter 254, and the common electrode 256 are formed is the thin film transistor 200 on the lower substrate 10. And face the upper surface on which the pixel electrode 220 is formed.

The sealant 260 is disposed between the upper substrate 250 and the lower substrate 10 to bond the upper substrate 250 and the lower substrate 10. The sealant 260 is disposed in the sealant formation region 16 located in the peripheral region 14 of the lower substrate 10. Accordingly, the lower surface of the sealant 260, which is in contact with the lower substrate 10, is partially in contact with the passivation layer 210, and the other portion of the sealant 260 is in contact with the gate insulating layer 202.

When a portion of the lower surface of the sealant 260 is in contact with the passivation layer 210 as in the present embodiment, no gap is generated between the sealant 260 and the passivation layer 210, so that the liquid crystal display device 300 operates when the liquid crystal display device 300 is driven. Even if the temperature of 270 increases, spots do not occur at the boundary between the screen display area 12 and the peripheral area 14.

In addition, the lower surface of the sealant 260 is formed of photo acryl to contact only the portion of the sealant 260 and the protective layer 210 having low adhesion, and the remaining portion of the gate insulating layer formed of silicon nitride having excellent adhesion with the sealant 260 ( The contact force between the upper substrate 250 and the lower substrate 10 is also increased because of contact with the 202.

According to the present exemplary embodiment, the bonding area between the upper substrate 250 and the lower substrate 10 may be increased as the area of the lower surface of the sealant 260 in contact with the gate insulating layer 202 is larger than the area in contact with the protective film 210. have. Therefore, it is most preferable that the protective film 210 formed inside the sealant formation region 16 does not exceed 50% of the area of the sealant formation region 16.

Referring to FIG. 3, the liquid crystal 270 is disposed between the upper substrate 250 and the lower substrate 10 bonded by the sealant 260.

Referring to the process of attaching the lower substrate and the upper substrate produced through Example 1 and Example 2 are as follows.

First, a viscous liquid sealant material is applied to the sealant formation region 16 of the upper surface of the lower substrate 10 on which the thin film transistors 20 and 200, the passivation layers 30 and 210, and the pixel electrodes 40 and 220 are formed. do. Sealant materials include photocurable materials that are cured by light, ie ultraviolet light.

When the sealant material is applied to the sealant forming region 16, a portion of the sealant material contacts the passivation layers 30 and 210 and the other part contacts the insulating layers 24 and 202.

When the sealant material is applied to the sealant forming region 16 of the lower substrate 10, the upper substrate 50 having the black matrix patterns 25 and 252, the color filters 54 and 254, and the common electrodes 26 and 256 may be formed. The upper substrates 50 and 250 are placed on the sealant material with one surface of the substrate 250 facing the upper surface of the lower substrate 10. Subsequently, the sealant material applied to the sealant forming region 16 is irradiated with ultraviolet rays to cure the sealant material, thereby forming sealants 60 and 260 which bond the lower substrate 10 to the upper substrates 50 and 250.

As described above, the lower surfaces of the sealants 60 and 260 in contact with the lower substrate 10 may be silicon nitride having a part of contact with the protective films 30 and 210 and the remaining parts of the sealants 60 and 260 having excellent adhesion to the sealants 60 and 260. The sealants 60 and 260 are firmly attached to the lower substrate 10 because they are in contact with the formed insulating layers 24 and 202. Therefore, a poor bonding between the upper substrates 50 and 250 and the lower substrate 10 can be prevented.

When the lower substrate 10 and the upper substrates 50 and 250 are attached to each other by the sealants 60 and 260, the lower substrate 10 and the upper substrates 50 and 250 through the liquid crystal injection holes provided in the sealant formation region 16. Liquid crystals (70, 270) are injected between the two, and the liquid crystal injection port is sealed to manufacture a liquid crystal display panel.

As described in detail above, a portion of the lower surface of the sealant in contact with the lower substrate is in contact with the passivation layer, and the remaining portion is in contact with an insulating film formed of silicon nitride having excellent adhesion to the sealant, thereby preventing a poor bonding between the upper substrate and the lower substrate. It works.

In addition, since gaps are not generated between the sealant and the passivation layer, it is possible to prevent cell gap staining from occurring at the boundary between the screen display area and the peripheral area, thereby improving the display quality of the image.

Although the detailed description of the present invention has been described with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art will have the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (5)

A thin film transistor arranged in a matrix form in the screen display area, an insulating film covering the screen display area from a peripheral area surrounding the screen display area, a protective film formed from the screen display area to a portion of the peripheral area to cover the thin film transistor, and A lower substrate on the passivation layer and including a pixel electrode electrically connected to the thin film transistor; An upper substrate including a color filter disposed corresponding to each of the pixels and disposed to face the lower substrate; A sealant disposed in the peripheral area such that a portion is in contact with the passivation layer and a remaining portion is in contact with the insulating layer, and the sealant bonds the lower substrate and the upper substrate; And And a liquid crystal injected between the lower substrate and the upper substrate. The method of claim 1, wherein the thin film transistor A channel layer formed on an upper surface of the lower substrate; A first insulating layer formed on an entire surface of the lower substrate including the screen display area and a peripheral area to cover the channel layer and having first contact holes exposing the channel layer at both edges of the channel layer; A gate electrode formed between the first contact hole among upper surfaces of the first insulating layer; A second insulating layer formed on an entire surface of the lower substrate including the screen display area and the peripheral area to cover the gate electrode and have a second contact hole corresponding to the first contact hole; A source electrode formed on the second insulating layer to overlap the gate electrode and one end of the channel layer and connected to the channel layer through the first and second contact holes; And Formed on the second insulating layer so as to be spaced apart from the source electrode and overlap the other ends of the gate electrode and the channel layer, and to be connected to the channel layer through the first and second contact holes, and formed in the passivation layer. And a drain electrode connected to the pixel electrode through a contact hole. The thin film transistor of claim 1, wherein the thin film transistor A gate electrode formed on an upper surface of the lower substrate; A gate insulating layer formed on an entire surface of the lower substrate including the screen display area and the peripheral area to cover the gate electrode; A channel layer formed on a portion of the gate insulating layer corresponding to the gate electrode; A source electrode formed on the upper surface of the channel layer to overlap one end of the gate electrode; And, And a drain electrode formed on the channel layer so as to be spaced apart from the source electrode and overlapping with the other end of the gate electrode and connected to the pixel electrode through the contact hole formed in the passivation layer. Device. The liquid crystal display of claim 1, wherein the insulating layer includes any one selected from the group consisting of silicon nitride and silicon oxide. The liquid crystal display device of claim 1, wherein the passivation layer comprises photoacryl including a photosensitive material.

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