KR20080059437A - Driving method of plasma display panel and plasma display - Google Patents

Abstract

A technology of a PDP having a four electrode structure of (X,Y,Z,A) in which a delay in discharge timing due to a voltage applied to a Z electrode can be prevented. In the voltage waveform applied from the drive circuit side to each electrode (e.g. X1, Zo, Y1, Ze, X2, Zo, Y2) for a PDP where rows are formed on the opposite sides of the four electrode structure of (X,Y,Z,A) and a Y electrode, the voltage (Vt) of a positive polarity trigger pulse (65) having a narrow width and applied to the Z electrode is set higher than the voltage (Vs) of sustain pulses (45, 46, 55, 56) of X and Y.

Description

Plasma display panel driving method and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel (PDP) and a technology of a display device (plasma display device: PDP device) for displaying a moving image on the PDP. In particular, the present invention relates to the driving of a PDP having a four-electrode structure.

A conventional PDP device is a general configuration in which a row (display line) is formed of a first (X) electrode and a second (Y) electrode in a PDP, but the X and Y electrodes are alternately arranged to intersect all adjacent electrodes. There is a configuration in which rows are formed (so-called ALIS configurations).

In the PDP, address discharge is performed between the address electrodes A and Y electrodes, and sustain discharge for display is performed between the X and Y electrodes. In addition, there exists a PDP having a structure in which a third (Z) electrode is formed between the X-Y electrodes. The voltage applied to the Z electrode of the PDP causes a preliminary discharge (called a trigger discharge, etc.) for sustain discharge between XY between the Z electrode and the adjacent electrode (ZX / Y), that is, between ZX or ZY. to be.

<Start of invention>

Problems to be Solved by the Invention

In the case of the PDP driving method and the PDP device of the four-electrode structure in which the (X, Y, Z, A) electrodes are formed, the sustain discharge becomes unstable due to the discharge delay of the trigger discharge. The timing needs to be controlled with high precision. That is, it is necessary to prevent the delay of the timing of trigger discharge.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of preventing a delay in discharge timing due to a voltage applied to a third (Z) electrode in the technique of the PDP having the four-electrode structure. To provide.

Means for solving the problem

Among the inventions disclosed herein, an outline of representative ones will be briefly described as follows. MEANS TO SOLVE THE PROBLEM In order to achieve the said objective, this invention is a technique of the PDP of the structure provided with the (X, Y, Z, A) electrode, It is characterized by including the technical means described below.

The PDP extends in the first (horizontal) direction on the first substrate, and a plurality of the PDPs are disposed substantially parallel to each other so that the discharge group for the display discharges between the first (X) and second (Y) electrode groups and the XY electrodes. It has a 3rd (Z) electrode group arrange | positioned at the clearance gap (discharge gap) to which discharge is performed, and the 1st dielectric layer and protective layer which cover X-Z electrode group. On the second substrate facing the first substrate, a fourth electrode (address (A) electrode) group extending in the second (vertical) direction substantially perpendicular to the horizontal direction and arranged in a plurality of substantially parallel, and the A electrode group And a second dielectric layer to cover, a partition wall disposed on both sides of the A electrode, and a phosphor layer formed between the partition wall and on the second dielectric layer. The display cells are formed by regions where the X, Z, Y, and A electrodes cross each other.

According to the driving method of the PDP of the present invention, when the sustain discharge (repetitive discharge) is performed between XY electrodes (main discharge gap) by applying a voltage waveform to the electrode group of the PDP, the sustain discharge is performed between the XY electrodes. Prior to producing a potential difference (first potential difference), the potential difference (second potential difference) between the X or Y electrode and the Z electrode (ZX / Y, the trigger discharge gap) is made larger than the first potential difference at the Z electrode. Configuration. In other words, near the rise of the sustain pulse applied to the X and Y electrodes, a trigger pulse with a voltage larger than the voltage of the sustain pulse is applied to the Z electrode. Thereby, the delay of the timing of the voltage waveform in Z-X / Y is prevented.

Further, the PDP apparatus of the present invention, when performing sustain discharge between the XY electrodes, applies the first positive power source (voltage Vt, Vs2) applied to the Z electrode group by the Z driving circuit to the X and Y driving circuits. This configuration is higher than the positive second power supplies (voltages Vs and Vs1) applied to the X and Y electrode groups.

Effect of the Invention

Among the inventions disclosed herein, the effects obtained by the representative ones are briefly described as follows. According to the present invention, the delay of the timing of the trigger discharge for sustain discharge due to the voltage applied to the third (Z) electrode can be prevented, whereby the sustain discharge can be stabilized and the display quality can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the structure of the PDP module and PDP apparatus which are one Embodiment of this invention.

FIG. 2 is a perspective view showing a partially disassembled configuration of a PDP in the PDP device according to one embodiment of the present invention. FIG.

3 is a longitudinal cross-sectional view showing a partial configuration of a PDP in the PDP device according to one embodiment of the present invention.

4 is a plan view showing a display cell structure in the PDP device according to one embodiment of the present invention;

5 is a diagram illustrating a field configuration concept in the PDP apparatus according to the embodiment of the present invention.

Fig. 6 is a diagram showing voltage waveforms applied to an electrode group from each driving circuit side in the PDP apparatus and PDP driving method according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a schematic configuration of a Z driving circuit in the PDP apparatus according to the first embodiment of the present invention. FIG.

Fig. 8 is a diagram showing timing of Z electrode driving in the PDP apparatus according to the first embodiment of the present invention.

Fig. 9 is a diagram showing a schematic configuration of an X (Y) driving circuit in the PDP device according to the first embodiment of the present invention.

Fig. 10 is a diagram showing the timing of X (Y) electrode driving in the PDP apparatus according to the first embodiment of the present invention.

Fig. 11 is a diagram showing a schematic configuration of a Z driving circuit in the PDP device according to the second embodiment of the present invention.

Fig. 12 is a diagram showing the timing of Z electrode driving in the PDP apparatus according to the second embodiment of the present invention.

Fig. 13 is a diagram showing a schematic configuration of a Z driving circuit in the PDP apparatus according to the third embodiment of the present invention.

Fig. 14 is a diagram showing timing of Z electrode driving in the PDP apparatus according to the third embodiment of the present invention.

Fig. 15 is a diagram showing a schematic configuration of a Z driving circuit in the PDP apparatus according to the fourth embodiment of the present invention.

Fig. 16 is a diagram showing timing of Z electrode driving in the PDP apparatus according to the fourth embodiment of the present invention.

17 is a diagram showing a schematic configuration of a Z driving circuit in the PDP apparatus according to the fifth embodiment of the present invention.

Fig. 18 is a diagram showing timing of Z electrode driving in the PDP apparatus according to the fifth embodiment of the present invention.

Fig. 19 is a perspective view showing a partially disassembled configuration of a PDP in the PDP apparatus according to the sixth embodiment of the present invention.

20 is a diagram showing voltage waveforms applied to an electrode group from each driving circuit side in the PDP apparatus and PDP driving method according to Embodiment 6 of the present invention.

<Best Mode for Carrying Out the Invention>

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on drawing. In addition, in the whole figure for demonstrating embodiment, the same code | symbol is attached | subjected in principle to the same part, and the repeated description is abbreviate | omitted.

Embodiment 1

Embodiment 1 is demonstrated with reference to FIGS. In Embodiment 1, as a driving method for the PDP 3 (Figs. 1 to 4) of the four-electrode structure having (X, Y, Z, A) as a feature, the delay of the timing of the trigger discharge between ZX / Y is delayed. To prevent. For that purpose, as shown in FIG. 6 and the like, the voltage Vt of the narrow pulse applied to Z for the trigger discharge preceding the sustain discharge (main discharge) of (X, Y) in the sustain period Ts, The voltage is larger than the voltage Vs of the sustain pulses of (X, Y).

<PDP Device>

Fig. 1 shows a block structure of a PDP module, which is an example of the structure of an AC type PDP device having a four-electrode structure in Embodiment 1 of the present invention. The PDP module includes an X drive circuit 4, a Y drive circuit 5, a first Z drive circuit 9, and a PDP 3, a power supply circuit 8, a control circuit 7, and a drive circuit. 2 Z driving circuit 10 and address driving circuit 6. For example, the PDP module has a structure in which the PDP 3, the substrate portion on which the respective circuits, etc. are mounted, the chassis, and the like are fixed. The corresponding drive circuits are electrically connected to various electrode groups of the PDP 3. The PDP device product (set) is constructed by accommodating the PDP module in an external case.

The power supply circuit 8 supplies power to the control circuit 7 and the like. The control circuit 7 controls each drive circuit 4, 5, 9, 10, 6. Moreover, the form which integrated the control circuit 7 and each drive circuit is also possible. Each drive circuit generates and supplies a voltage of the drive waveform for the corresponding electrode based on the control from the control circuit 7. Moreover, the output terminal of a drive circuit and the electrode of a PDP are electrically connected through the wiring etc. in a flexible board | substrate.

The X driving circuit 4 includes a plurality of X electrodes (sustain electrodes) of the PDP 3 (X1, X2,...). }, A predetermined voltage is supplied. X electrodes {X1, X2,... } Or their generic names are represented by X. The Y drive circuit 5 includes a plurality of scan electrodes (Y electrodes) {Y1, Y2,..., PDP 3. }, A predetermined voltage is supplied. Y electrodes {Y1, Y2,... } Or their generic names are represented by Y. The first Z driving circuit 9 supplies a predetermined voltage to the odd o-th Z electrode (trigger electrode) {Zo} of the PDP 3. The second Z driving circuit 10 supplies a predetermined voltage to the even (e) th Z electrode (trigger electrode) {Ze} of the PDP 3. Each of Z electrodes (Zo, Ze) or their generic name is represented by Z (Zo, Ze). The address driving circuit 6 includes a plurality of address electrodes A1, A2,... Of the PDP 3. }, A predetermined voltage is supplied. Address electrodes A1, A2,... } Or their generic names are denoted by A.

That is, the PDP 3 of this four-electrode structure has an address electrode A, an X electrode X, a Y electrode Y, and a Z electrode Z. As shown in FIG. The Z electrode Z is formed to be located in the gap (discharge gap) between the X electrode X and the Y electrode Y. The regions intersected by (X-Zo-Y, A) and (Y-Ze-X, A) correspond to the display cells C, respectively.

In the PDP 3, (X, Z, Y) extends in the horizontal (first) direction in parallel to form a row (display line), and the address electrode A extends in the vertical (second) direction to form a column. To form. The address electrode A is disposed to intersect X-Z-Y. The plurality of (X, Y, Z) are alternately from the top in the second direction, from {X1, Zo, Y1, Ze, X2, Zo, Y2,... } Is placed as follows. The i Y electrodes Yi and the j address electrodes Aj form a two-dimensional matrix of i row j columns. For example, display cell C11 is formed by the intersection of Y1 and A1, and Zo and X1 adjacent to it. Such display cells are associated with the pixels. By this two-dimensional matrix, the PDP 3 can display a two-dimensional image. Zo is an electrode for assisting the discharge between X1 and Y1, for example, and Ze is an electrode for assisting the discharge between Y1 and X2, for example.

<PDP>

2 shows a structural example of the PDP 3 according to the present embodiment. On the front glass substrate 1, the electrodes 11-18 of X, Y, and Z are formed. On it, a dielectric layer 21 for insulating the discharge space S is deposited. Moreover, the protective layer 20 by MgO (magnesium oxide) is deposited on it, for example.

The X electrode is composed of, for example, an X transparent electrode 11 and an X bus electrode 12. The Y electrode is comprised by the Y transparent electrode 13 and the Y bus electrode 14, for example. The odd-numbered Z electrode Zo is composed of, for example, a Z transparent electrode 15 and a Z bus electrode 16. The even-numbered Z electrode Ze is comprised by the Z transparent electrode 17 and the Z bus electrode 18, for example. In the type of the electrode, the metal bus electrode has a lower electrical resistance value than the transparent electrode (also called a display electrode).

On the other hand, an address electrode (A) 25 is formed on the back glass substrate 2 which is disposed to face the front glass substrate 1. On it, a dielectric layer 23 is deposited. Further, on the dielectric layer 23, partition walls (ribs) 26 extending in a stripe shape in the vertical direction are formed so as to partition the discharge space S in correspondence with the display cells. The phosphors 24 of each color of R (red), G (green), and B (blue) are formed in the area partitioned by the partition wall (rib) 26, that is, on each side surface of the partition wall 26 and the upper surface of the dielectric layer 23. ) Is arranged in a stripe shape and applied. Each color emits light when the phosphors 24 of each color are excited by sustain discharge between the X electrode (particularly, reference numeral 12) and the Y electrode (particularly, reference numeral 14). Ne + Xe penning gas (discharge gas) or the like is enclosed in the discharge space S between the front glass substrate 1 and the back glass substrate 2. Various electrode groups X, Y, Z and A are formed by the same process. Moreover, as a rib structure, the lattice rib structure etc. which formed not only the partition 26 in a vertical direction but also the partition extended in a horizontal direction are possible.

<PDP single sided>

FIG. 3 shows a partial cross section in the second direction along the address electrode 25 of the PDP 3, corresponding to FIG. 2. For example, two adjacent rows L1 and L2 in X1 to X2 are shown. Y1 serving as the scan electrode (display electrode to which the scan pulse is applied) is shared by X1 and X2 serving as sustain electrodes (display electrodes to which the scan pulse is not applied) on both sides thereof. L1 is formed by X1-Y1 and L2 is formed by Y1-X2. L1 becomes an odd-numbered row and L2 becomes an even-numbered row. In each row, Z (Zo, Ze) serving as a trigger discharge electrode (trigger electrode) is disposed between Y-X. Zo is disposed at Y1-X1 and Ze is disposed at Y1-X2.

<Display cell>

4 shows an example of the structure of the display cell C of the PDP 3 and shows a partial plane viewed from the vertical direction of the PDP 3 plane, corresponding to FIGS. 1 to 3. As an example, parts corresponding to X1 to Y1 (rows L1 to L3) are shown.

An area partitioned by the partition wall 26 and the X and Y bus electrodes 12 and 14 may correspond to the display cell C. The address electrode 25 (for example, A1) is disposed between the partition walls 26.

The X bus electrode 12 constituting X1 is connected to the X driving circuit 4 side, and an X voltage waveform is applied. The Y bus electrode 14 constituting Y1 is connected to the Y drive circuit 5 side, and a Y voltage waveform is applied. The Z bus electrode 16 constituting Zo is connected to the Zo drive circuit 9 side, and a Zo voltage waveform is applied. The Z bus electrode 18 constituting Ze is connected to the Ze drive circuit 10 side and a Ze voltage waveform is applied.

The X transparent electrode 11 constituting X1 is electrically connected to the X bus electrode 12. The Y transparent electrode 13 constituting Y1 is electrically connected to the Y bus electrode 14. The Z transparent electrode 15 constituting Zo is electrically connected to the Z bus electrode 16. The Z transparent electrode 17 constituting Ze is electrically connected to the Z bus electrode 18. In the present example, the X and Y transparent electrodes 11 and 13 are shaped to protrude in a T-shape both vertically and vertically. Correspondingly, in the present example, the Z transparent electrodes 15 and 17 of Zo and Ze are slightly protruded in a rectangular shape in both vertical directions. In addition, the shape etc. of each transparent electrode are an example, and deformation | transformation is possible.

Between XY, a discharge gap g0 for sustain discharge (main discharge) is formed between the X transparent electrode 11 and the Y transparent electrode 13 with their edges facing each other and illustrated by arrows. . Moreover, between Z-X and Z-Y, between the adjacent transparent electrodes, their edges oppose, and the discharge gaps g1 and g2 for the trigger discharge of sustain discharge as shown by the arrow are formed.

<Field>

5 shows an example of the configuration of the field F 100 corresponding to the display image of the PDP 3 in the present PDP apparatus. Each F 100 includes a plurality of subfields (SF) 110, for example, ten SFs 110 ("SF1", "SF2",...). , "SFl0"}. Each SF 110 is given different weights for the gray scale representation. The number of SFs corresponds to the number of gradation bits. The gray level value can be determined by the combination of the SFs 110 to be lit and displayed at the F 100. Each F 100 can display one image and is displayed at 60 F / sec.

Each SF 110 is composed of a reset period Tr 111, an address period Ta 112, and a sustain period Ts 113. The Tr 111 is a period for performing the initialization (or addressing preparation) operation of the display cell C. FIG. In Ta 112, light emission (lighting) / non-light emission (non-lighting) of each display cell C can be selected (addressed) by the address discharge between A and Y. Specifically, Y electrodes {Y1, Y2, Y3, Y4,... } And the like, sequentially apply a scanning pulse, apply an address pulse to the address electrode 25 in response to the scanning pulse, and set the potential of X to be a potential capable of discharging between Y and AY. The discharge / non-emission of the desired display cell C can be selected by discharging between XY with the discharge of the liver as a trigger. In Ts 113, sustain discharge is performed between X and Y of the display cell C selected in the previous Ta (l12) using X, Y, and Z to emit light of the display cell C. Each of the SFs 110 differs in the number of times of light emission (the length of the Ts 113) due to the sustain pulses applied to the X and Y in the Ts 113.

<Voltage waveform>

FIG. 6 shows an example of a voltage waveform (drive waveform) applied to each electrode in the PDP driving method of the first embodiment. Examples of voltage waveforms corresponding to Tr 111, Ta 112, and Ts 113 of the SF 110 in X1 to Y2 and A are shown. Vx1 is the voltage waveform of X1. Vx2 is the voltage waveform of X2. Vy1 is a voltage waveform of Y1. Vzo is the voltage waveform of Zo. Vze is the voltage waveform of Ze. Va is the voltage waveform of the address electrode A (25). The same voltage waveform is also applied to the other electrode.

Shown in FIG. 6 are voltage waveforms during discharge (display) between X1-Y1 and X2-Y2, that is, Zo and odd-numbered sides. For that purpose, the ground (GND) potential 81 may be always maintained on the other side, on the Y1-X2 side, that is, Vze on the Ze and even-numbered sides. On the contrary, in the voltage waveform during discharge between Y1-X2, that is, Ze and even-numbered sides, the ground potential 81 is held at Vzo on the other side.

Hereinafter, the waveform of each period is demonstrated. First, in Tr 111, the write voltage 41 and the adjustment voltage 42 are applied as Vx1. The same applies to Vx2. As Vy1, the write obtuse wave voltage 51 and the adjusted obtuse wave voltage 52 are applied. As a result, write discharge and regulated discharge for reset are generated between X1-Y1 and X2-Y1. As Vzo, the write voltage 61 and the adjustment voltage 62 are applied in the same manner as the write voltage 41 and the adjustment voltage 42 of Vx1 to cause discharge similar to X1. The same applies to Vx2 to Vy2.

Next, in Ta 112, as Vx1, a voltage 43 during scanning is applied. As Vx2, a voltage 43 is applied during scanning. In addition, the voltage 43 at the time of scanning is divided into the first half and the second half of Ta 112, and is applied. In addition, as Vy1, a scan pulse 53 is applied. Specifically, Y electrodes {Y1, Y3, Y5, Y7,... , Y2, Y4, Y6, Y8,... } The scan pulses 53 are sequentially applied to every other one. In addition, as Va, an address pulse 74 is applied to the display cell C to be selected in synchronization with the scan pulse 53 of each row.

In the first half of Ta 112, when the address pulse 74 is applied in response to the scan pulse 53, a discharge occurs between Y1-A. Using the discharge as an ember, discharge occurs between X1 and Y1, and wall charge is generated in the vicinity of X1 and Y1. At this time, no discharge occurs between X2-Y1. This is done between each Xi-Yi (i is odd). In the second half of Ta 112, when the address pulse 74 is applied in response to the scan pulse 53, a discharge occurs between Y2-A. Using the discharge as an ember, discharge occurs between X2-Y2, and wall charge is generated in the vicinity of X2 and Y2. At this time, no discharge occurs between X3-Y2. This is done between each Xj-Yj (j is even). At Vzo for Zo, the same voltage at scan 63 as adjacent X (X1, X3) is applied.

Next, in Ts 113, the repetitive sustain pulses 45 and 46 and the erase pulse 47 are applied as Vx1. The repetitive sustain pulses 45 and 46 are repeatedly applied pulses whose polarities are reversed alternately (minus sustain pulses 45 and positive sustain pulses 46). As Vy, repetitive sustain pulses 55 and 56 and an erase pulse 57 are applied similarly to Vx. Repetitive sustain pulses 55 and 56 are pulses whose polarities are reversed alternately (plus sustain pulse 55 and negative sustain pulse 56) repeatedly applied, and repeat sustain pulse 45 of Vx. , 46) is a pulse whose polarity is reversed. In addition, the voltage of the repeating sustain pulse 45, 46, 55, 56 in this example is +/- Vs, and Vs = 85 [V] as an example. In addition, the erase pulses 47 and 67 applied at the end of the Ts 113 serve to reduce wall charges. This is not limited to this example, but there are many methods such as a thin line erasing method, a wide width erasing method, and a magnetic erasing method. None of them completely erases wall charges, but reduces the amount.

As Vzo, a trigger pulse 64 on the coin is applied in accordance with the first sustain pulse 45 of Vx1. Subsequently, in advance of the positive sustain pulse 46 (and the negative sustain pulse 56), the positive trigger pulse 65 is applied, and at the same time as the sustain discharge of XY is started, the negative trigger pulse ( 66) is applied. The negative trigger pulse 66 is the same voltage -Vs as the sustain pulse, but the positive trigger pulse 65 is, unlike the prior art, a voltage higher than the voltage Vs of the sustain pulse (indicated by Vt). As a result, the discharge delay of the trigger discharge preceding the sustain discharge can be reduced. The same applies to each subsequent trigger pulse 65 and 66. Thereafter, the same erase pulse 67 as the erase pulse 47 of Vx1 is applied.

At Vx2, the repetitive sustain pulses 85 and 86 (negative sustain pulse 85 and positive sustain pulse) are synchronized with the negative sustain pulse 56 of Vy1 so as to not discharge between Vy1. (86)) is applied. In this case, at Vx2 and Vy1, except for the first (sustain pulse 55 and GND potential) and the last (GND potential and positive sustain pulse 96), it is coincident and no discharge occurs at X2-Y1. In addition, in order to match the number of discharges in each row (display line), a positive sustain pulse 96 is applied last (in this example, six sustain pulses in total). In Vy2, reverse pulse sustain pulses 95 and 96 (plus sustain pulse 95 and negative sustain pulse 96) are applied correspondingly to Vx2. Vzo between X2-Y2 is the same as Vzo between X1-Y1.

<Z driving circuit>

7 shows a schematic configuration of a circuit (corresponding to the Z drive circuits 9 and 10) for applying a voltage to the Z electrode Z. As shown in FIG. This circuit consists of a coil L1, switches Zsw1 to Zsw4, diodes D1 to D4, a Vs2 power supply 701, a -Vs1 power supply 702, and the like.

The Vs2 power supply 701 supplies the voltage Vs2 corresponding to the voltage Vt of the positive trigger pulse 65 shown in FIG. The -Vs1 power supply 702 supplies the voltage -Vs1 corresponding to the voltage -Vs of the negative trigger pulse 66 shown in FIG.

The switches Zsw1 to Zsw4 each consist of a MOSFET element and a diode is connected between the source and the drain. Between the drain of the switch Zsw1 and the source of the switch Zsw2 (potential 703), it is set to become substantially intermediate potential of Vs2 and -Vs1. The source of the switch Zsw1 is connected to one end of the coil L1 through the diode D1 of the forward connection. One end of the coil L1 is connected to the drain of the switch Zsw2 through the diode D2 of the forward connection.

The drain of the switch Zsw3 is connected to the Vs2 power supply 701. The source of the switch Zsw4 is connected to the -Vs1 power supply 702. The source of the switch Zsw3 and the drain of the switch Zsw4 are commonly connected to the other end of the coil L1, and this common connection point is an output terminal of a Z pulse (voltage waveform applied to the Z electrode). The diode D3 is connected in the reverse direction from the Vs2 power supply 701 to one end of the coil L1. The diode D4 is connected in the reverse direction from the one end of the coil L1 to the -Vs1 power supply 702.

In particular, this Z drive circuit is conventionally comprised only of switches Zsw3 and Zsw4. On the other hand, in the first embodiment, the coil L1 and the switches Zsw1 to Zsw4 using the LC resonance operation with the capacitance of the PDP 3 (the capacitance between ZX / Y of the display cell C) are generated and Z pulses are generated. Is applied to the PDP 3. The switches Zsw1 and Zsw2 are Z power recovery switches, and MOSFET elements are arranged in parallel. The coil L1 is a resonant coil, in which charge and discharge paths for the charge of the PDP 3 are arranged in a common one series.

<Z driving timing>

Next, FIG. 8 shows details of the on / off timing of each element of the Z drive circuit of FIG. 7, the voltage waveform of each electrode, and the timing of discharge. "X (Y)" and "Y (X)" in FIG. 8 represent the details of the pulses corresponding to the sustain pulses 45, 46, 55 and 56 in FIG. 6, and "Z" represents FIG. The details of the pulses corresponding to the trigger pulses 64, 65, and 66 in FIG. "Zsw1" to "Zsw4" in FIG. 8 correspond to the operation of the switches Zsw1 to Zsw4 in FIG. Each T represents a timing.

The Z pulse is applied prior to the sustain pulse of X (Y), and the trigger discharge by the Z pulse is set to overlap with the rise T1-T4 of the sustain pulse of X (Y). The sustain pulse of X (Y) becomes voltage -Vs1 before rising and voltage Vs1 after rising. The pulse of Z becomes the voltage -Vs1 before rise and the voltage Vs2 after rise. The period in which Z is Vs2 and the period in which X (Y) is Vs1 are set so as not to overlap. The condition is Vs2> Vs1.

Prior to raising the sustain pulse of X (Y), first, the switch Zsw1 is turned on (T1), and the voltage of the Z pulse is raised (T1-T2). Subsequently, the switch Zsw3 is turned on (T2), and the voltage applied to the Z electrode is raised to Vs2 (T2-T3). At this time, the switch Zsw1 and the switch Zsw3 may be turned on at the same time. Next, the switch Zsw3 is turned off (T2-T3), and the switch Zsw2 is turned on (T3). At this time, the switch Zsw1 is Off. As a result, the voltage applied to the Z electrode is lowered (T3-T4). After that, the switch Zsw4 is turned on (T4), and the voltage applied to the Z electrode is lowered to the original voltage -Vs1. Thereby, the positive Z pulse (trigger pulse 65) of a narrow pulse width can be produced | generated.

In order to realize high speed, the Z pulse of the narrow pulse width has a pulse width of the time before the discharge light emission starting from the sustain pulse of X (Y) (T5-T6) (T3-T4). Is set to end at As an example, the pulse width is about 100 Hz to 1000 Hz. The charging of the capacity of the PDP 3 is performed by the rise of this Z pulse, and the discharge from the capacity of the PDP 3 is performed by the falling.

<X (Y) driving circuit>

9 shows a schematic configuration of a circuit (corresponding to the X drive circuit 4 (Y drive circuit 5)) for applying a voltage to the X (Y) electrode. It is the same structure in X and Y. This circuit is composed of coils L1, switches Xsw1 to Xsw4, diodes D1 to D4, Vs power supply 901, -Vs power supply 902, capacitors C1 and C2, and the like.

The Vs power supply 901 supplies a voltage (Vs1 in FIG. 7) corresponding to the voltage Vs of the sustain pulse of FIG. 6. The -Vs power supply 902 supplies a voltage (-Vs1 in FIG. 7) corresponding to the voltage -Vs of the sustain pulse of FIG. 6.

The switches Xsw1 to Xsw4 each consist of a MOSFET element and a diode is connected between the source and the drain. Between the drain of the switch Xsw1 and the source of the switch Xsw2 (potential 903), it is set to become substantially intermediate potential of Vs and -Vs. The source of the switch Xsw1 is connected to one end of the coil L1 through the diode D1 of the forward connection. One end of the coil L1 is connected to the drain of the switch Xsw2 through the diode D2 of the forward connection.

The drain of the switch Xsw3 is connected to the Vs power supply 901 and the capacitor C1 arranged in parallel with the ground. The source of the switch Xsw4 is connected to the -Vs power supply 902 and the capacitor C2 arranged in parallel with the ground. The source of the switch Xsw3 and the drain of the switch Xsw4 are commonly connected to the other end of the coil L1, and this common connection point serves as an output terminal of an X (Y) pulse (voltage waveform). The diode D3 is connected in a reverse direction from the Vs power supply 901 to one end of the coil L1. The diode D4 is connected in the reverse direction from the one end of the coil L1 to the -Vs power supply 902.

<X (Y) drive timing>

Next, similarly to FIG. 8, in FIG. 10, the detail of the on / off timing of each element of the said X (Y) drive circuit, the voltage waveform of each electrode, and the timing of discharge are shown. Each t represents a timing.

First, the switch Xsw1 is turned on (t1), and the voltage of the X (Y) pulse is raised (t1-t2). Subsequently, the switch Xsw3 is turned on (t2), and the voltage applied to the X (Y) electrode is raised to Vs. At this time, the switch Xsw1 and the switch Xsw3 may be turned on at the same time. Next, after the switch Xsw3 is turned off, the switch Xsw2 is turned on (t3). At this time, the switch Xsw1 is Off. As a result, the voltage applied to the X (Y) electrode is lowered (t3-t4). After that, the switch Xsw4 is turned on (t4), and the voltage applied to the X (Y) electrode is lowered to the original voltage -Vs. As a result, a positive sustain pulse is formed. The same applies to the Y driving circuit side.

By the above drive circuits, the voltages applied to the Ts 113 to the X (Y) and Z electrodes satisfy the condition of Vs 2> Vs. Also, -Vs1 = -Vs. As a result, when a positive Z pulse (trigger pulse 65) is applied, a potential difference larger than that at the time of sustain discharge of X-Y is generated between the electrode Y (X) electrode which becomes the negative (negative) electrode. Therefore, the deviation or fluctuation of the generation timing of the conventional trigger discharge, in particular, the trigger discharge delay (delay in the right direction in Fig. 8) can be reduced. That is, the sustain discharge caused by the X (Y) sustain pulse can be stabilized.

Embodiment 2

Next, another embodiment will be described as a modification of the first embodiment. FIG. 11 shows a Z driving circuit in Embodiment 2. FIG. 12 shows Z drive timing and the like in the second embodiment. In FIG. 11, the structure of Embodiment 2 is an example which added the Vz1 power supply 1101 to the structure of FIG. The Vz1 power supply 1101 is connected between the drain of the switch Zsw1 and the source of the switch Zsw2. The Vz1 power supply 1101 supplies the voltage Vz1. That is, the PDP 3 has a Vz1 power supply 1101 which charges the capacitance of the PDP 3 and increases its resonance point by the LC resonance characteristic of the circuit. With this structure, the voltage of Z can be raised to near Vs2 by LC resonance of the capacitances of L1 and PDP 3. By the voltage Vz1, the voltage applied to L1 can be made high, thereby increasing the voltage of the LC resonance. In FIG. 12, by the switch operation similar to Embodiment 1, as shown by the rise of the pulse of Z, the voltage is pulled from -Vs1 to Vs2 at the timing of T1-T2.

Embodiment 3

Fig. 13 shows the Z driving circuit in the third embodiment. 14 shows the Z drive timing and the like in the third embodiment. 13 and 14, the configuration of Embodiment 3 is an example in which the sustain pulse is composed of 0 V (GND) to Vs 3. The Z pulse is composed of 0 V (GND) to Vs 4 (Vs 4> Vs 3). In Fig. 13, instead of the Vs2 power source 701 and the -Vs power source 702, a Vs4 power source 1301 and a ground 1302 are provided. The capacitor Z3 is grounded between the drain of the switch Zsw1 and the source of the switch Zsw2 (potential 1303). In Fig. 14, according to the switch operation similar to that in the first embodiment, the sustain pulse of X (Y) becomes GND before the rise and Vs3 after the rise. The Z pulse becomes GND before the rise and Vs4 after the rise. As a condition, Vs4> Vs3.

Embodiment 4

15 shows the Z driving circuit in the fourth embodiment. 16 shows the Z drive timing and the like in the fourth embodiment. In FIG. 15, the fourth embodiment is an example in which the Vz2 power supply 1501 is applied to the configuration of the third embodiment in the same manner as in the second embodiment. In Fig. 15, the Vz2 power supply 1501 is connected between the drain of the switch Zsw1 and the source of the switch Zsw2 (potential 1503), and is grounded through the capacitor C3. In Fig. 16, the sustain pulse is composed of 0V (GND) to Vs3, and the Z pulse is composed of 0V (CND) to Vs4 (Vs4 > Vs3). With this configuration, the voltage of Z can be raised to near Vs4 by LC resonance of the capacitances of L1 and PDP 3 by the same switch operation and action as in the second embodiment (T1-T2).

Embodiment 5

17 shows the Z drive circuit in the fifth embodiment. 18 shows Z drive timing and the like in the fifth embodiment. In FIG. 17, the structure of Embodiment 5 has the two types of coils L1 and L2 connected to Z, Comprising: It divides two path | routes for charging and discharging correspondingly. That is, in the Z drive circuit for applying the Z pulse, the first path (L1 side) 1701 and the PDP to charge the capacitance of the PDP 3 by the LC resonance characteristic of the PDP 3-the circuit in question. It has a 2nd path (L2 side) 1702 which discharges from the capacitance of (3). In Fig. 18, the present configuration can be designed with different power recovery characteristics in the charge (T1-T2) and the discharge (T3-T4) of the Z pulse.

Embodiment 6

Next, Embodiment 6, which is a modified example in which the PDP and the driving method are different, will be described. The technique of the first embodiment and the modifications thereof can be applied in addition to the structure of the PDP 3 (so-called ALIS configuration) capable of discharging at both sides (plus reverse slit) of the Y electrode as shown in FIG. The structure of Embodiment 6 is the structure of the PDP 3B of the general four-electrode structure as shown in FIG. As for the structure, the above-described characteristic configuration of the Z pulse is applied.

In FIG. 19, in the PDP 3B, an electrode group constituting a row with (X, Z, Y) as a set is formed on the front glass substrate 1 repeatedly in the vertical direction. The back glass substrate 2 side is similar to the above. The X electrode is composed of the X transparent electrode 11 and the X bus electrode 12, and the Y electrode is composed of the Y transparent electrode 13 and the Y bus electrode 14, and Z is disposed in the discharge gap of XY. The electrode is composed of a Z transparent electrode 19 and a Z bus electrode 20. X and Y can be comprised by 1 type, respectively.

The PDP apparatus of Embodiment 6 has an X drive circuit, a Y drive circuit, a Z drive circuit, and an address drive circuit which are electrically connected to the various electrodes of the PDP 3B to apply voltage waveforms for driving. The configurations of the Z driving circuit and the X (Y) driving circuit can be similarly applied to the configurations (FIGS. 7 and 9, etc.) of the first to fifth embodiments.

In FIG. 20, voltage waveforms Vx, Vz, Vy, and Va for driving the electrode group of the PDP 3B are shown. The operation of the Tr 111 and Ta 112 is similar to that of FIG. 6. In Ts 113, in Vx and Vy, sustain pulses 45, 46, 55, 56 of alternating repetitions of opposite polarities are applied to X-Y similarly to FIG. The voltage of this sustain pulse is -Vs to Vs. In Vz, similarly to Figs. 6 and 8, trigger pulses 65 and 66 are applied as Z pulses for trigger discharge of Z-X / Y at the timing preceding the sustain pulse. The voltage of this Z pulse is -Vs-Vt.

According to the sixth embodiment, similarly to the first embodiment and the like, the deviation and fluctuation of the timing of generating the trigger discharge can be reduced, and the sustain discharge caused by the X (Y) sustain pulse can be stabilized.

According to each embodiment described above, the delay of the trigger discharge can be reduced, the sustain discharge can be stabilized, and the display quality of the PDP can be improved.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on embodiment, it is a matter of course that this invention is not limited to the said embodiment and can be variously changed in the range which does not deviate from the summary.

Claims (5)

A third arranged in the gap between the first and second electrode groups for discharging the plurality of first and second electrodes extending in the first direction and arranged in substantially parallel to the first substrate; A plurality of electrode groups, a first dielectric layer and a protective layer covering the first to third electrode groups, extending in a second direction substantially perpendicular to the first direction on a second substrate facing the first substrate; Is a fourth electrode group having substantially parallel to each other, a second dielectric layer covering the fourth electrode group, barrier ribs disposed on both sides of the fourth electrode, and a phosphor layer formed between the barrier ribs and on the second dielectric layer. A driving method of a plasma display panel having When performing sustain discharge between the first and second electrodes, prior to generating a potential difference of sustain discharge between the first and second electrodes, in the third electrode, the first or second electrode and the first electrode are formed. A method of driving a plasma display panel, wherein the potential difference between the three electrodes is made larger than the potential difference of the sustain discharge generated between the first and second electrodes. A third arranged in the gap between the first and second electrode groups for discharging the plurality of first and second electrodes extending in the first direction and arranged in substantially parallel to the first substrate; A plurality of electrode groups, a first dielectric layer and a protective layer covering the first to third electrode groups, extending in a second direction substantially perpendicular to the first direction on a second substrate facing the first substrate; Is a fourth electrode group having substantially parallel to each other, a second dielectric layer covering the fourth electrode group, barrier ribs disposed on both sides of the fourth electrode, and a phosphor layer formed between the barrier ribs and on the second dielectric layer. Having a plasma display panel, A first driving circuit for applying a voltage to the first electrode group, a second driving circuit for applying a voltage to the second electrode group, a third driving circuit for applying a voltage to the third electrode group, and the first driving circuit A plasma display device having a fourth driving circuit for applying a voltage to a group of four electrodes, By application of a voltage waveform to the first to fourth electrode groups of the plasma display panel from the first to fourth driving circuits, When performing sustain discharge between the first and second electrodes, prior to generating a potential difference of sustain discharge between the first and second electrodes, in the third electrode, the first or second electrode and the first electrode are formed. And a potential difference between the three electrodes is greater than a potential difference of the sustain discharge generated between the first and second electrodes. The method of claim 2, When performing sustain discharge between the first and second electrodes, the first and second drive circuits supply a first positive polarity power source applied to the third electrode group by the third drive circuit. And a second power supply having a positive polarity applied to the second electrode group. The method of claim 2, In the third drive circuit, a circuit for applying a positive potential to the third electrode group when performing sustain discharge between the first and second electrodes, And a third power source which charges the capacitance of the plasma display panel by the LC resonance characteristic of the plasma display panel and the corresponding circuit and increases the resonance point thereof. The method of claim 2, In the third drive circuit, a circuit for applying a positive potential to the third electrode group when performing sustain discharge between the first and second electrodes, And a second path for charging the capacitance of the plasma display panel by the LC resonance characteristic of the plasma display panel and the corresponding circuit, and a second path for discharging from the capacitance of the plasma display panel.

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