KR20080057415A - Thin film transistor, array substrate having the transistor and display panel having the transistor - Google Patents

Abstract

A thin film transistor, an array substrate having the same, and a display panel having the same are provided to realize stable property by preventing the property change according to a grain boundary forming location even if positions of semiconductor patterns are changed. The plural semiconductor patterns(142) are formed with polysilicon. The semiconductor patterns having the same shape extended toward a first direction are disposed to the parallel along a second direction which is vertical to the first direction, of which each one end corresponding to each other is separated by the same length along the first direction, and on which the plural grain boundaries are formed toward the second direction. A gate electrode(144) is formed toward the second direction so as to be overlapped with the center of the semiconductor patterns. A source electrode(146) is separated from the gate electrode to the one side, and connected with the semiconductor patterns electrically. A grain electrode(148) is separated from the gate electrode to the other side, and connected with the semiconductor patterns electrically.

Description

Thin film transistor, array substrate having same, and display panel having the same {THIN FILM TRANSISTOR, ARRAY SUBSTRATE HAVING THE TRANSISTOR AND DISPLAY PANEL HAVING THE TRANSISTOR}

1 is a plan view illustrating unit pixels of an array substrate in a display panel according to an exemplary embodiment of the present invention.

FIG. 2 is an enlarged plan view of portion A of FIG. 1.

3 is a plan view illustrating another embodiment of FIG. 2.

4 is a cross-sectional view taken along line II ′ of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

100: array substrate 110: base substrate

IL1: 1st insulating film IL2: 2nd insulating film

IL3: third insulating film 120: gate wiring

130: data wiring 140: thin film transistor

142 semiconductor pattern 144 gate electrode

146 source electrode 148 drain electrode

CH: Channel part LD1, LD2: Low concentration doping part

HD1, HD2: high concentration doping unit 150: pixel electrode

The present invention relates to a thin film transistor, an array substrate having the same, and a manufacturing method thereof, and more particularly, to a thin film transistor having improved electrical characteristics, an array substrate having the same, and a manufacturing method thereof.

Amorphous silicon (a-Si) thin film transistors are mainly used as switching elements of liquid crystal displays, but recently, in order to reduce costs and achieve high definition by integrating circuits on a substrate. BACKGROUND ART Liquid crystal displays for devices employ many poly-silicon thin film transistors with high operating speed. In particular, the polycrystalline silicon thin film transistor is mainly employed in an organic light emitting display having an organic light emitting diode (OLED) driven by a current.

In general, a polycrystalline silicon thin film used in the polycrystalline silicon thin film transistor is formed by crystallizing an amorphous silicon thin film by irradiating a laser beam. Here, when the laser beam is irradiated with the amorphous silicon thin film, a portion of the amorphous silicon thin film is irradiated via a mask having a plurality of slits.

Recently, a sequential lateral solidification (SLS) crystallization method is widely used as a method of forming the polycrystalline silicon thin film. The SLS crystallization method refers to crystallizing the entire region of the amorphous silicon thin film by irradiating the laser beam while moving the mask in one direction. In this case, when the polycrystalline silicon thin film is formed by the SLS crystallization method, grain boundaries are formed in the polycrystalline silicon thin film in one direction.

The polycrystalline silicon thin film transistor is formed by patterning a portion of the polycrystalline silicon thin film to form a semiconductor pattern and forming a source electrode and a drain electrode.

However, the grain boundaries exist in the semiconductor pattern, thereby deteriorating electrical characteristics such as electrical mobility. In particular, when the patterned position is changed little by little depending on the manufacturing process, the semiconductor pattern has a problem in that the position or number of grain boundaries in the channel are changed due to the error of the patterning, thereby changing the electrical characteristics.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a thin film transistor having improved electrical characteristics by preventing adverse effects due to patterning errors.

Another object of the present invention is to provide an array substrate having the thin film transistor described above.

Another object of the present invention is to provide a display panel having the above-described array substrate.

A thin film transistor according to an exemplary embodiment for achieving the above object of the present invention includes semiconductor patterns, a gate electrode, a source electrode, and a drain electrode.

The semiconductor patterns all have the same shape extending in the first direction and are arranged in parallel in a second direction perpendicular to the first direction, and one end corresponding to each other has the same length along the first direction. It is spaced apart and made of poly-Si (poly-Si) formed with a plurality of grain boundaries in the second direction.

The gate electrode is formed in the second direction to overlap the center of the semiconductor patterns. The source electrode is spaced apart from one side of the gate electrode to be electrically connected to the semiconductor patterns. The thin film transistor is spaced apart from the gate electrode to the other side opposite to the one side and electrically connected to the semiconductor patterns.

Here, each of the semiconductor patterns preferably includes a channel portion, a lightly doped portion and a highly doped portion. The channel portion overlaps the gate electrode. The lightly doped portions are formed on both sides of the channel portion, and are ion-doped at a low concentration. The high concentration doping portion is formed at both outer peripheries of the low concentration doping portion to be electrically connected to the source electrode and the drain electrode, and is ion-doped at a high concentration.

On the other hand, it is preferable that each of the semiconductor patterns have substantially the same rectangular shape when viewed in plan view, wherein the semiconductor patterns have a minimum distance between the grain boundaries and a length in the first direction of the lightly doped portion. It is desirable to have as many as the common multiple.

According to another aspect of the present invention, an array substrate includes a gate wiring, a data wiring crossing the gate wiring, a thin film transistor electrically connected to the gate and the data wiring, and an electrical connection with the thin film transistor. It includes a pixel electrode.

The thin film transistors all have the same shape extending in the first direction and are arranged in parallel along a second direction perpendicular to the first direction, and one end of each thin film transistor having the same length along the first direction has the same length. Semiconductor patterns formed of poly-Si, spaced apart from each other, and having a plurality of grain boundaries formed in the second direction, and a gate electrode protruding from the gate wiring in the second direction so as to overlap a center of the semiconductor patterns; And a source electrode spaced apart from the data line to be electrically connected to the semiconductor patterns, and spaced apart from one side of the gate electrode to one side, and spaced apart from the gate electrode to another side opposite to the one side, and electrically connected to the semiconductor patterns. And extend to overlap the pixel electrode and electrically connect the pixel electrode. A drain electrode.

Here, the gate, source and drain electrodes are preferably formed so as to overlap the upper side of the semiconductor patterns.

According to another aspect of the present invention, there is provided a display panel including a gate wiring, a data wiring crossing the gate wiring, a thin film transistor electrically connected to the gate and the data wiring, and an electrical connection with the thin film transistor. An array substrate having connected pixel electrodes, an opposing substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the opposing substrate.

The thin film transistors all have the same shape extending in the first direction and are arranged in parallel along a second direction perpendicular to the first direction, and one end of each thin film transistor having the same length along the first direction has the same length. Semiconductor patterns formed of poly-Si, spaced apart from each other, and having a plurality of grain boundaries formed in the second direction, and a gate electrode protruding from the gate wiring in the second direction so as to overlap a center of the semiconductor patterns; And a source electrode spaced apart from the data line to be electrically connected to the semiconductor patterns, and spaced apart from one side of the gate electrode to one side, and spaced apart from the gate electrode to another side opposite to the one side, and electrically connected to the semiconductor patterns. And extend to overlap the pixel electrode and electrically connect the pixel electrode. A drain electrode.

According to the present invention, the semiconductor patterns formed by dividing into a plurality of all have the same shape extending in the first direction and are arranged in parallel along the second direction, and each one end corresponding to each other is the same along the first direction. As they are spaced apart in length, the adverse effects of the location of the grain boundaries can be further reduced to further improve the electrical characteristics.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating unit pixels of an array substrate in a display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display panel according to the present exemplary embodiment includes an array substrate 100, an opposing substrate (not shown), and a liquid crystal layer (not shown). Here, after briefly explaining the components of the display panel, the array substrate will be described in more detail.

The array substrate 100 includes a plurality of pixel electrodes 150 arranged in a matrix, thin film transistors 140 for applying a driving voltage to each pixel electrode 150, and signal lines for driving the thin film transistors 140, respectively. (120, 130).

The opposite substrate is disposed to face the array substrate 100. The opposing substrate may include color filters disposed on the front surface of the substrate and disposed to face the transparent and conductive common electrode and the pixel electrodes 150. The color filters include, for example, red color filters, green color filters, and blue color filters.

The liquid crystal layer is interposed between the array substrate 100 and the counter substrate, and rearranged by an electric field formed between the pixel electrodes 150 and the common electrode. The rearranged liquid crystal layer adjusts the light transmittance of the light applied from the outside, and the light having the light transmittance adjusted passes through the color filters to display the image to the outside.

Referring back to FIG. 1, the array substrate 100 includes a gate wiring 120, a data wiring 130, a thin film transistor 140, and a pixel electrode 150.

The gate lines 120 are formed long in the first direction, and the plurality of gate lines 120 are spaced apart from each other at regular intervals.

The data lines 130 are elongated in a second direction crossing the first direction, and the data lines 130 are spaced apart from each other at regular intervals. In this case, the second direction is preferably perpendicular to the first direction. Meanwhile, as the gate lines 120 and the data lines 130 cross each other, a plurality of unit pixels are defined in the array substrate 100.

The thin film transistor 140 is formed in the unit pixel and is electrically connected to the gate line 120 and the data line 130.

The pixel electrode 150 is formed in the unit pixel and is electrically connected to the thin film transistor 140. In this case, the pixel electrode 150 is preferably made of a transparent conductive material. The pixel electrode 150 is charged by receiving a driving voltage from the thin film transistor 140 and generates an electric field between the common electrode of the opposing substrate.

FIG. 2 is an enlarged plan view of portion A of FIG. 1, FIG. 3 is a plan view illustrating an embodiment different from FIG. 2, and FIG. 4 is a cross-sectional view taken along line II ′ of FIG. 3. 2 is a plan view showing a conventional thin film transistor, and FIG. 3 is a plan view showing a thin film transistor according to the present embodiment.

2, 3, and 4, the array substrate 100 according to the present embodiment may include a base substrate 110, a first insulating film IL1, a second insulating film IL2, a third insulating film IL3, The gate wiring 120, the data wiring 130, the thin film transistor 140, and the pixel electrode 150 are included.

The base substrate 110 has a plate shape and is made of a transparent material such as glass, quartz, transparent synthetic resin, or the like.

The base substrate 110 is stacked in the order of the first insulating film IL1, the second insulating film IL2, and the third insulating film IL3. In this case, the first insulating film IL1 and the second insulating film IL2 are preferably inorganic insulating films, and the third insulating film IL3 is preferably an organic insulating film.

The gate line 120 is formed in the first direction on the first insulating layer IL1. That is, the gate wiring 120 is formed on the first insulating film IL1 and covered by the second insulating film IL2.

The data line 130 is formed in the second direction on the second insulating layer IL2. That is, the data line 130 is formed on the second insulating film IL2 and covered by the third insulating film IL3.

The thin film transistor 140 includes semiconductor patterns 142, a gate electrode 144, a source electrode 146, and a drain electrode 148.

The semiconductor patterns 142 are formed on the base substrate 110, covered by the first insulating layer IL1, and made of poly-Si. A plurality of grain boundaries 10 are formed in the semiconductor patterns 142 in the first direction. Here, the plurality of grain boundaries 10 are formed with protrusions protruding at a predetermined height.

The gate electrode 144 protrudes in the second direction from the gate wiring 120 to overlap the center of the semiconductor patterns 142.

The source electrode 146 protrudes from the data line 130 in the first direction to overlap a portion of the semiconductor patterns 142. The source electrode 146 is in electrical contact with the semiconductor patterns 142 by the first contact hole CT1 formed in the first and second insulating layers IL1 and IL2. In this case, the source electrode 146 is formed at a position spaced apart from the gate electrode 144 to one side.

The drain electrode 148 is spaced apart from the gate electrode 144 to the other side opposite to the one side and overlaps a portion of the semiconductor patterns 142. The drain electrode 148 is in electrical contact with the semiconductor patterns 142 by the second contact hole CT2 formed in the first and second insulating layers IL1 and IL2. The drain electrode 148 extends in the first direction and overlaps the pixel electrode 150.

The pixel electrode 150 is formed on the third insulating film IL3 and is in electrical contact with the drain electrode 148 through the third contact hole formed in the third insulating film IL3.

Referring to FIGS. 2 and 3 again, the thin film transistor 140 according to the present embodiment will be described in more detail. In particular, the semiconductor patterns 142 of the thin film transistor 140 will be described in detail.

First, the semiconductor patterns 142 are integrated into one in FIG. 2, but are separated from each other in FIG. 3.

Specifically, all of the semiconductor patterns 142 according to the present exemplary embodiment have the same shape extending in the first direction, and are arranged in parallel in a second direction perpendicular to the first direction. Here, it is preferable that each of the semiconductor patterns 142 have substantially the same rectangular shape when viewed in plan.

One end of each of the semiconductor patterns 142 corresponding to each other is spaced apart by the same length along the first direction. That is, when the semiconductor patterns 142 include, for example, the first semiconductor pattern 142a, the second semiconductor pattern 142b, and the third semiconductor pattern 142c, one side end of the second semiconductor pattern 142b is used. Is spaced apart from one end of the first semiconductor pattern 142a in the first direction by a pattern separation distance d, and one end of the third semiconductor pattern 142c is formed from one end of the second semiconductor pattern 142b. The pattern spaced distance d is equally spaced in one direction.

A plurality of grain boundaries 10 are formed in the semiconductor patterns 142 in the second direction. The grain boundaries 10 are formed by a sequential lateral solidification (SLS) crystallization method by a laser, and protrude from the surface of the semiconductor pattern 142 to a predetermined height due to lateral growth of a plurality of grains. At this time, the grain boundaries 10 are formed to be spaced apart by the grain separation distance L1.

Meanwhile, each of the semiconductor patterns 142 includes a channel portion CH, low concentration doped portions LD1 and LD2, and high concentration doped portions HD1 and HD2.

The channel portion CH overlaps with the gate electrode 144. That is, the portion of the semiconductor pattern 142 overlapping with the gate electrode 144 is called a channel portion CH.

The lightly doped portions LD1 and LD2 are formed on both sides of the channel portion CH in the first direction. The lightly doped portions LD1 and LD2 include the first lightly doped portion LD1 formed on one side of the channel portion CH and the second lightly doped portion LD2 formed on the other side of the channel portion CH. The lightly doped portions LD1 and LD2 are formed by implanting impurity ions at low concentration into polysilicon. Here, the first lightly doped part LD1 and the second lightly doped part LD2 have a doping length L2 in the first direction.

The high concentration doping parts HD1 and HD2 are formed at both outer sides of the low concentration doping parts LD1 and LD2 in the first direction to be electrically connected to the source electrode 146 and the drain electrode 148. That is, the high concentration doping units HD1 and HD2 are formed at one outer side of the first low concentration doping unit LD1 and electrically connected to the source electrode 146 through the first contact hole CT1. And a second high concentration doping part HD2 formed at the outer side of the second low concentration doping part LD2 and electrically connected to the drain electrode 148 through the second contact hole CT2. . The highly doped portions HD1 and HD2 are formed by implanting impurity ions into polysilicon at a high concentration. For this reason, it is preferable that the high concentration doping portions HD1 and HD2 have an electric mobility almost similar to that of the metal.

Meanwhile, the gate electrode 144 protrudes from the gate wiring 120 in the second direction, and a plurality of steps are formed at both ends in the first direction to correspond to each channel portion CH of the semiconductor patterns 142. Have In addition, a plurality of steps may be formed at one end of the source electrode 146 and one end of the drain electrode facing the source electrode 146.

Hereinafter, the main features according to the present embodiment will be described with reference to FIGS. 2 and 3.

First, it is preferable that the semiconductor patterns 142 have the number of grain separation distances L1 of the grain boundaries 10 and the minimum common multiple K of the doping lengths L2 of the lightly doped portions LD1 and LD2. As a result, the width in the second direction of each of the semiconductor patterns 142 has a value obtained by dividing the entire width W of the integrated semiconductor pattern 142 in FIG. 2 by the least common multiple K. K is a natural number greater than 1)

For example, in detail, if the grain separation distance L1 is 3um and the doping length L2 is 2um, the number of the semiconductor patterns 142 is preferably six. As a result, the width in the second direction of each of the semiconductor patterns 142 has a value of 1/6 um when the entire width W of the semiconductor pattern 142 of FIG. 2 is 1 um.

On the other hand, more preferably, the grain separation distance L1 is N times the doping length L2, and as a result, the number of the semiconductor patterns 142 is N (where N is a natural number greater than 1).

For example, in detail, if the grain separation distance L1 is 6um and the doping length L2 is 2um, the number of the semiconductor patterns 142 is preferably three. As a result, the width in the second direction of each of the semiconductor patterns 142 has a value of 1/3 um when the width W of the entire semiconductor pattern 142 of FIG. 2 is 1 um.

Finally, the pattern spacing d between the one end of each of the semiconductor patterns 142 is preferably equal to the doping length L2 of the lightly doped portions LD1 and LD2.

Specifically, for example, when the doping length L2 is 2um, each one end of the semiconductor patterns 142 may be spaced apart by 2um in the first direction.

As described above, all of the semiconductor patterns 142 formed by dividing into a plurality of parts have the same shape extending in the first direction and are arranged in parallel along the second direction, and one end of each side corresponding to each other is the first. As spaced apart by the same length along the direction, has the following effects.

First, referring to FIG. 2, when the semiconductor patterns 142 are not separated and integrated as in the related art, electrical characteristics of the thin film transistor 140 are changed according to the formation positions of the grain boundaries 10.

Specifically, in FIG. 2, grain boundaries are formed in the first lightly doped portion LD1, whereas grain boundaries 10 are not formed in the second lightly doped portion LD2. That is, the electrical mobility of the first low concentration doped part LD1 and the electrical mobility of the second low concentration doped part LD2 are different from each other, and thus the electrical characteristics of the thin film transistor 140 may be degraded.

However, when the semiconductor patterns 142 are separately formed as shown in FIG. 3, the formation area of the grain boundary 10 in each of the first low concentration doping portions LD1 and the second low concentration doping portions LD2 are formed. The formation area of the grain boundaries 10 becomes equal.

Specifically, in FIG. 3, grain boundaries 10 are formed only in the first lightly doped portion LD1 of the first semiconductor pattern 142a, and the second and third semiconductor patterns 142b and 142c are formed. The grain boundary 10 was not formed in the 1st low concentration doping part LD1.

On the other hand, the grain boundary 10 is formed only in the second lightly doped portion LD2 of the second semiconductor pattern 142b, and the second lightly doped portion LD2 of the first and third semiconductor patterns 142a and 142c is formed. The grain boundary 10 was not formed.

Accordingly, the area of formation of the grain boundary 10 in each of the first low concentration doping portions LD1 and the grain boundary of each of the second low concentration doping portions LD2 when the entire thin film transistor 140 is viewed as a reference. The formation areas of (10) become the same, and moreover, even if the patterning position of the semiconductor patterns 142 is changed with respect to the grain boundary 10.

That is, even if the patterning position of the semiconductor patterns 142 is changed with respect to the grain boundary 10, the electrical characteristics of the thin film transistor 140 are not changed.

According to the present invention, the semiconductor patterns formed by dividing into a plurality of all have the same shape extending in the first direction and are arranged in parallel along the second direction, and one end corresponding to each other along the first direction. As the same length is spaced apart, the characteristics of the thin film transistor according to the formation position of the grain boundary can be prevented, and as a result, the characteristics of the stable thin film transistor can be realized even if the patterning position of the semiconductor patterns is changed.

In the detailed description of the present invention described above with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (9)

They all have the same shape extending in the first direction and are arranged in parallel along a second direction perpendicular to the first direction, and one end corresponding to each other is spaced apart by the same length along the first direction. Semiconductor patterns formed of poly-Si having a plurality of grain boundaries in a second direction; A gate electrode formed in the second direction so as to overlap a center of the semiconductor patterns; A source electrode spaced apart from one side of the gate electrode and electrically connected to the semiconductor patterns; And And a drain electrode spaced apart from the gate electrode to the other side opposite to the one side and electrically connected to the semiconductor patterns. The method of claim 1, wherein each of the semiconductor patterns A channel portion overlapping the gate electrode; Low concentration doping portions formed on both sides of the channel portion and doped with low concentration ions; And And a high concentration doping portion formed on both outer edges of the low concentration doping portion, electrically connected to the source electrode and the drain electrode, and heavily doped with ions. The thin film transistor of claim 2, wherein each of the semiconductor patterns has substantially the same rectangular shape when viewed in plan view. 4. The thin film transistor of claim 3, wherein the semiconductor patterns have a minimum common multiple of a distance between the grain boundaries and a length in the first direction of the lightly doped portion. The thin film transistor of claim 4, wherein the distance between the grain boundaries is N times the length of the lightly doped portion, and the number of the semiconductor patterns is N, where N is a natural number greater than one. The thin film transistor of claim 4, wherein one end of each of the semiconductor patterns is spaced apart by the length of the lightly doped portion. An array substrate comprising a gate wiring, a data wiring crossing the gate wiring, a thin film transistor electrically connected to the gate and the data wiring, and a pixel electrode electrically connected to the thin film transistor. The thin film transistor is They all have the same shape extending in the first direction and are arranged in parallel in a second direction perpendicular to the first direction, and one end corresponding to each other is spaced apart by the same length along the first direction, Semiconductor patterns made of poly-Si having a plurality of grain boundaries formed in the second direction; A gate electrode protruding from the gate wiring in the second direction so as to overlap a center of the semiconductor patterns; A source electrode protruding from the data line and electrically connected to the semiconductor patterns and spaced apart from one side of the gate electrode; And And a drain electrode spaced apart from the gate electrode to the other side, the drain electrode being electrically connected to the semiconductor patterns and extending to overlap with the pixel electrode and electrically connected to the pixel electrode. The array substrate of claim 7, wherein the gate, source, and drain electrodes are formed to overlap each other on the semiconductor patterns. An array substrate having a gate wiring, a data wiring crossing the gate wiring, a thin film transistor electrically connected to the gate and the data wiring, and a pixel electrode electrically connected to the thin film transistor; An opposing substrate facing the array substrate; And A liquid crystal layer interposed between the array substrate and the counter substrate, The thin film transistor is They all have the same shape extending in the first direction and are arranged in parallel along a second direction perpendicular to the first direction, and one end corresponding to each other is spaced apart by the same length along the first direction. Semiconductor patterns formed of poly-Si having a plurality of grain boundaries in a second direction; A gate electrode protruding from the gate wiring in the second direction so as to overlap a center of the semiconductor patterns; A source electrode protruding from the data line and electrically connected to the semiconductor patterns and spaced apart from one side of the gate electrode; And And a drain electrode spaced apart from the gate electrode to the other side, the drain electrode being electrically connected to the semiconductor patterns and extending to overlap the pixel electrode, the drain electrode being electrically connected to the pixel electrode.

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