KR20080054550A - Liquid crystal display - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to enhance the adhesive strength of a gate driver and a sealant to securely combine two substrates of the LCD. An LCD includes a substrate(110), a display area, a plurality of gate lines, a plurality of data lines, a gate driver, a passivation layer(180), and a sealant(310). The display area includes a plurality of pixels which are arranged in a matrix on the substrate and respectively include switching elements. The gate lines are respectively connected to the switching elements and extended in a row direction. The data lines are respectively connected to the switching elements and intersect the gate lines. The gate driver includes a plurality of lines formed on the substrate. The passivation layer is formed on the lines and the data lines. The sealant envelops the edge of the display area and covers at least part of the gate driver. The passivation layer has a plurality of contact holes(186,187) which expose portions where the lines are not formed.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

4 and 5 are cross-sectional views of the liquid crystal panel assembly shown in FIG. 3 taken along lines IV-IV and V-V, respectively.

6 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of the liquid crystal display shown in FIG. 6 taken along the line VIII-VIII. FIG.

FIG. 8 is a plan view showing a part of the liquid crystal display shown in FIG. 6 in detail; FIG.

FIG. 9 is a cross-sectional view of the liquid crystal display shown in FIG. 8 taken along the line VIII-VIII. FIG.

<Description of Drawing>

3: liquid crystal layer 110, 210: substrate

100: lower panel 191: pixel electrode

200: upper display panel 220: light blocking member

270: common electrode 300: liquid crystal panel assembly

310: sealing material 400: gate drive unit

500: data driver 600: signal controller

700: driving chip 800: gray voltage generator

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the flat panel display devices most widely used. The liquid crystal display includes two display panels on which field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode. The gate line generates a gate signal generated by the gate driving circuit, the data line transfers the data voltage generated by the data driving circuit, and the switching element transfers the data voltage to the pixel electrode according to the gate signal.

The gate driver and the data driver are formed in a chip form and mounted on the display panel. However, in recent years, in order to increase productivity while reducing the overall size of the display device, a structure for integrating the gate driver into the display panel has been developed.

In such a liquid crystal display, two display panels are attached with a sealing material. However, in the gate driver part integrated in the display panel, the adhesive force with the sealing material may decrease, so that the two display panels may not be smoothly attached.

Therefore, the technical problem to be achieved of the present invention is to increase the adhesion between the gate driver and the sealing material to secure the reliability of the combination of the two display panels.

A liquid crystal display according to an exemplary embodiment of the present invention has a substrate, a display area including a plurality of pixels arranged in a matrix form on the substrate, each pixel including a switching element, and connected to the switching element, in a row direction. A gate driver including a plurality of extending gate lines, a plurality of data lines connected to the switch element and intersecting the gate lines, and a plurality of wirings integrated with the gate lines and the data lines and formed on the substrate; A plurality of openings including a passivation layer formed on the interconnection line and the data line, and a sealing material surrounding at least a portion of the gate driver and surrounding the display area, wherein the passivation layer exposes a portion where the interconnection line is not formed. Is formed.

The sealing member and the gate driver may contact each other through the opening.

The protective film may include an organic film.

The wiring may include first and second wirings having different layers, and an insulating film formed between the first and second wirings, and the sealing material and the insulating film may contact each other through the opening.

The passivation layer may include an organic layer and an inorganic layer, and the opening may be formed only in the organic layer.

The sealant may contact the inorganic layer through the opening.

The opening may be formed around four corners of the substrate.

The gate driver may include a first gate driver and a second gate driver facing each other with the display area therebetween.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver connected thereto. The gray voltage generator 800 connected to the 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines G ₁ -G _n transmitting a gate signal (also referred to as a “scan signal”) and a plurality of data lines D ₁ -D _m transmitting a data signal. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a switching element Q connected to a signal line, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100. The control terminal is connected to the gate line Gi, and the input terminal is connected to the data line Dj. The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. . Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ). The gate driver 400 includes a plurality of stages substantially arranged in a row as a shift register, and together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. In the same process, the liquid crystal panel assembly 300 is formed and integrated.

The gate driver 400 may include a first gate driver (not shown) and a second gate driver (not shown) facing each other with the plurality of pixels PX interposed therebetween. As a result, gate signals may be applied to the gate lines G ₁ -G _n at both sides of the liquid crystal panel assembly 300, thereby preventing the gate signals from being delayed at one side of the gate lines G ₁ -G _n . Therefore, the gate signal can be more effectively transmitted over the entire gate line G ₁ -G _n .

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). And attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. . In addition, the driving apparatuses 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixel PX in one row and corresponds to each digital image signal DAT. The gradation voltage is selected to convert the digital image signal DAT into an analog data signal and then apply it to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

3 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIGS. 4 and 5 are cross-sectional views of the liquid crystal panel assembly illustrated in FIG. 3 taken along a line IV-IV and V-V, respectively. .

3 to 4, the liquid crystal display according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 interposed therebetween.

First, the lower panel 100 will be described.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding upward and end portions 129 having a large area for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110. , May be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the gate line 121 and a plurality of pairs of storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line is closer to the bottom of the two gate lines. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of one sustain electrode 133b has a large area, and its free end is divided into two parts, a straight part and a bent part. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, or molybdenum ( It may be made of molybdenum-based metals such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. On the other hand, other conductive films are made of other materials, especially materials having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum, and the like. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the storage electrode line 131 may be made of various other metals or conductors.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (hereinafter referred to as a-Si), polycrystalline silicon, an organic semiconductor, or the like are formed on the gate insulating layer 140. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of projections 154 extending toward the gate electrode 124. The linear semiconductor 151 has a wider width in the vicinity of the gate line 121 and the storage electrode line 131 and covers them widely.

A plurality of linear and island ohmic contacts 161 and 165 are formed on the semiconductor 151. The ohmic contacts 161 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductors 151 and 154 and the ohmic contacts 161, 163 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161, 163, and 165 and the gate insulating layer 140.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and runs between adjacent sets of storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and an end portion 179 having a large area for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with respect to the gate electrode 124. Each drain electrode 175 has one wide end portion 177 and the other end having a rod shape. The wide end portion 177 overlaps the extension 137 of the storage electrode line 131, and the rod-shaped end portion is partially surrounded by the source electrode 173 bent in a J shape.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175. When the semiconductor 151 is an organic semiconductor, the thin film transistor is an organic thin film transistor.

The data line 171 and the drain electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film. It may have a multilayer structure including (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data line 171 and the drain electrode 175 may be made of various metals or conductors.

The side of the data line 171 and the drain electrode 175 may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161, 163, and 165 exist only between the semiconductors 151 and 154 below and the data line 171 and the drain electrode 175 thereon, thereby lowering the contact resistance therebetween. In most places, the width of the linear semiconductor 151 is smaller than the width of the data line 171. However, as described above, the width of the linear semiconductor 151 becomes wider at the portion where it meets the gate line 121, thereby smoothing the profile of the surface. Prevents disconnection. The semiconductors 151 and 154 have portions exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed portions of the semiconductors 151 and 154. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and the dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 151 while maintaining excellent insulating properties of the organic layer.

In the passivation layer 180, a plurality of contact holes 182 and 185 exposing the end portion 179 and the drain electrode 175 of the data line 171 are formed, respectively, and the passivation layer 180 and the gate insulating layer are formed. 140, a plurality of contact holes 181 exposing the end portion 129 of the gate line 121, a plurality of contact holes 183a exposing a part of the storage electrode line 131 near the fixed end of the storage electrode 133b, A plurality of contact holes 183b exposing the straight portions of the free ends of the sustain electrodes 133a are formed.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied has a liquid crystal layer between the two electrodes by generating an electric field together with a common electrode (not shown) of the common electrode display panel 200 to which a common voltage is applied. The direction of liquid crystal molecules (not shown) is determined. The polarization of light passing through the liquid crystal layer varies according to the direction of the liquid crystal molecules determined as described above. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor in which the pixel electrode 191 and the drain electrode 175 electrically connected thereto overlap with the storage electrode line 131 is called a "storage capacitor", and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor. .

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 and the external device.

The connecting leg 83 crosses the gate line 121, and exposes the exposed portion of the storage electrode line 131 and the free end of the storage electrode 133b through a contact hole positioned on the opposite side with the gate line 121 interposed therebetween. It is connected to the exposed end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

Next, the upper panel 200 will be described.

A light blocking member 220 is formed on an insulating substrate 210 made of glass, plastic, or the like. The light blocking member 220 is also referred to as a black matrix and defines a plurality of opening regions facing the pixel electrode 191, and prevents light leakage between the pixel electrodes 191.

A plurality of color filters 230 are also formed on the substrate 210 and are arranged to almost fit into the opening region surrounded by the light blocking member 220. The color filter 230 may extend in the vertical direction along the pixel electrode 190 to form a stripe. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an insulator and protects the color filter 230, prevents the color filter 230 from being exposed, and provides a flat surface.

The common electrode 270 is formed on the overcoat 250. The common electrode 270 is preferably made of a transparent conductive conductor such as ITO or IZO.

An alignment layer (not shown) for aligning the liquid crystal layer 3 is coated on the inner surfaces of the display panels 100 and 200, and one or more polarizers are disposed on the outer surfaces of the display panels 100 and 200. (Not shown) is provided.

A detailed description of a liquid crystal display according to an exemplary embodiment of the present invention will now be given with reference to FIGS. 6 to 9.

FIG. 6 is a plan view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line VII-VII. 6 is a plan view showing a part of the liquid crystal display device shown in detail in FIG. 6, and FIG. 9 is a cross-sectional view of the liquid crystal display device shown in FIG. 8 taken along the line VII-VII.

6 and 7, a liquid crystal panel assembly according to an exemplary embodiment of the present invention may include a lower panel 100, an upper panel 200, and a liquid crystal layer 3 interposed between the two panels 100 and 200. And a sealing material 310 for sealing the liquid crystal layer 3.

The liquid crystal panel assembly 300 is divided into a display area DA displaying an image and a peripheral area PA surrounding the display area DA.

The substrate 110 of the display area DA is connected to a data line (not shown) that intersects a gate line (not shown), a thin film transistor (not shown) connected to the gate line and the data line, and a thin film transistor. Pixel electrodes 191 and the like are formed. In FIG. 7, thin film layers such as gate lines, data lines, and thin film transistors are represented by PP.

A portion of the peripheral area PA is mounted with the driving chip 700 connected to the data line of the display area DA. The driving chip 700 may include a data driver 500, a signal controller 600, a gray voltage generator 800, and the like.

The gate driver 400 is integrated with another part of the peripheral area PA. In more detail, the first and second gate drivers 400L and 400R are formed in both peripheral areas PA of the display area DA, and the third peripheral area PA is disposed in the lower peripheral area PA of the display area DA. The gate driver 400D is formed.

The first and second gate drivers 400R and 400L are connected to gate lines formed in the display area DA to substantially apply a gate signal to the gate lines. The third gate driver 400D is a dummy driver for compensating for a step with the peripheral area PA in which the first and second gate drivers 400R and 400L are formed. Therefore, the third gate driver 400D is not connected to the gate line of the display area DA. The third gate driver 400D may be omitted.

In FIG. 6, the driving chip 700 is attached to the upper peripheral area PA of the display area DA, and the third gate driver 400D is positioned in the lower peripheral area PA of the display area DA. Their hierarchical relationship can be interchanged.

The first and second gate drivers 400L and 400R are connected to the third gate driver 400D, respectively.

The gate driver 400 includes a plurality of stages (not shown) substantially arranged in a row as a shift register, and includes a plurality of wires (not shown) connected to each stage. The plurality of stages and the plurality of wirings may be made of the same material as the gate line and the data line.

A sealing material 310 is formed around the display area DA, and the sealing material 310 covers a part of the gate driver 400. The lower panel 100 and the upper panel 200 are combined with the sealing material 310.

8 and 9, in the gate driver 400 of the liquid crystal display according to the exemplary embodiment, a gate conductor wire formed of the same material on the same layer as the gate line 121 is formed on the substrate 110. 120a and 120b are formed.

The gate insulating layer 140 is formed on the gate conductor wirings 120a and 120b.

The data conductor wires 170a and 170b made of the same material are formed on the same layer as the data line 171 on the gate insulating layer 140.

The passivation layer 180 is formed on the data conductor wirings 170a and 170b. As described above, the passivation layer 180 may be formed of an organic layer, and may be a double layer formed of an organic layer and an inorganic layer.

A plurality of openings 186 and 187 exposing the gate insulating layer 140 are formed in the passivation layer 180. The openings 186 and 187 are formed in portions where the gate conductor wirings 120a and 120b and the data conductor wirings 170a and 170b are not formed. In addition, the openings 186 and 187 may be formed around four corners of the liquid crystal panel assembly 300.

The encapsulant 310 is formed on the passivation layer 180. The sealing material 310 contacts the gate insulating layer 140 through the openings 186 and 187.

If the passivation layer 180 includes the upper organic layer and the lower inorganic layer, the openings 186 and 187 are formed only in the upper organic layer, and the sealing material 310 contacts the lower inorganic layer through the openings 186 and 187. can do.

At the portion where the organic layer and the sealant 310 of the passivation layer 180 attach, the adhesive force of the sealant 310 is inferior. As in an exemplary embodiment of the present invention, when the organic film of the portion where the gate conductor wirings 120a and 120b and the data conductor wirings 170a and 170b of the gate driver 400 are not formed is removed, the sealing material 310 and the organic film are removed. The area of contact of the membrane can be reduced. As a result, the adhesive force of the sealing material 310 may be prevented from being reduced as a whole, and thus the bonding state of the lower panel 100 and the upper panel 200 may be more firmly maintained.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, the adhesion between the gate driver and the sealing material may be increased to ensure reliability of the coupling state between the two display panels.

Claims (8)

Board, A display area arranged on the substrate in a matrix form and including a plurality of pixels, each pixel including a switching element; A plurality of gate lines connected to the switching element and extending in a row direction, A plurality of data lines connected to the switch element and intersecting the gate lines, and A gate driver including a plurality of wires integrally formed on the substrate together with the gate line and the data line; A protective film formed on the wiring and the data line, and A sealing material surrounding the display area and covering at least a portion of the gate driver; Including, And a plurality of openings for exposing portions where the wirings are not formed in the protective film. In claim 1, And a liquid crystal display in contact with the sealing member and the gate driver through the opening. In claim 1, The protective layer includes an organic layer. In claim 3, The wiring includes a first wiring and a second wiring having different layers, and An insulating film formed between the first and second wirings Including, And a liquid crystal display in contact with the sealing material through the opening. In claim 1, The protective film includes an organic film and an inorganic film, And the opening is formed only in the organic layer. In claim 5, And the sealing material contacts the inorganic layer through the opening. In claim 1, The opening is formed around four corners of the substrate. In claim 1, The gate driver includes a first gate driver and a second gate driver facing each other with the display area therebetween.

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