KR20080054109A - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method for forming the same are provided to improve a coupling ratio by increasing a contact area between a dielectric layer and a polysilicon pattern. An active pattern has a first line width. A tunnel insulating layer pattern(108) is formed on the active pattern. The tunnel insulating layer pattern has a second line width wider than the first line width. A polysilicon pattern(118) is formed on the tunnel insulating layer pattern. The polysilicon pattern includes an upper part having the second line width and a lower part having a third line width smaller than the second line width. A plurality of spacers(114) are formed at the tunnel oxide layer pattern and a lower sidewall of the polysilicon pattern. A plurality of isolation patterns(126) are formed to define the active patterns.

Description

Semiconductor device and method of forming the same

1 is a schematic cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

2 through 9 are schematic cross-sectional views illustrating a method of forming the semiconductor device illustrated in FIG. 1.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 108 tunnel insulating film pattern

114: spacer 118: polysilicon pattern

126: device isolation pattern 128: dielectric film

130: control gate

The present invention relates to a semiconductor device and a method of forming the same. More particularly, the present invention relates to a nonvolatile memory device including a floating gate and a method of forming the same.

Nonvolatile memory devices have the advantage of being able to preserve digital data semi-permanently even in the absence of power, and both write and erase electrically. Therefore, it is widely used for data storage of portable electronic products. Moreover, in recent years, application fields have been expanded to digital, MP3 players, mobile phone memories and the like.

The gate of the memory cell of the nonvolatile memory device has a structure in which a tunnel oxide layer pattern, a floating gate, a dielectric layer, and a control gate are stacked.

As the design rule of the memory cell becomes smaller, the interference between adjacent gates increases as the width between the gates decreases. When mutual interference between the gates occurs, the reliability of the nonvolatile memory device including the gates is degraded.

In addition, the design rule of the memory cell is reduced, and the floating gate and the dielectric film of the memory cell are stacked to reduce the contact area between the floating gate and the dielectric film. As described above, the reduction of the area occupied by the dielectric film causes a reduction in the coupling ratio.

An object of the present invention for solving the above problems is to provide a semiconductor device to reduce the mutual interference between the gates, the coupling ratio is increased.

Another object of the present invention for solving the above problems is to provide a method of forming the semiconductor device.

According to an aspect of the present invention for achieving the above object, a semiconductor device, an active pattern having a first line width, and a tunnel insulating film pattern provided on the active pattern and having a second line width wider than the first line width; And a polysilicon pattern including a lower portion having a second line width and an upper portion having a third line width smaller than the second line width on the tunnel insulating layer pattern.

In example embodiments, the semiconductor device may further include spacers disposed on lower sidewalls of the tunnel oxide layer pattern and the polysilicon pattern, and device isolation patterns defining the active patterns. The spacers may include oxides.

According to another embodiment of the present invention, the lower sidewall of the polysilicon pattern may have a curved surface.

According to another aspect of the present invention for achieving the above another object, in the method of manufacturing a semiconductor device, a tunnel oxide film pattern having a first line width is formed on a substrate. A polysilicon pattern is formed on the tunnel oxide layer pattern including a lower portion having the first line width and an upper portion having a second line width smaller than the first line width. An active pattern having a third line width smaller than the first line width is formed under the tunnel oxide layer pattern.

According to another embodiment of the present invention, after the tunnel oxide layer pattern is formed, a preliminary polysilicon pattern and a mask pattern having the first line width are further formed on the tunnel oxide layer pattern, and the preliminary polysilicon pattern and the mask Spacers may be further formed on the pattern sidewalls, and the trench may be further formed by etching the substrate using the mask pattern and the spacers as an etch mask. A portion of the upper portion of the spacers may be removed to form the trench to cover a lower portion of the preliminary polysilicon pattern and a sidewall of the tunnel insulation pattern. In addition, a portion of the inside of the trench may be removed while the polysilicon pattern is formed. In the method of forming the semiconductor device, an isolation pattern for filling the trench may be further formed.

According to the present invention as described above, the upper portion of the polysilicon pattern has a line width smaller than the lower portion, spacers are provided on the lower sidewall, it is possible to suppress mutual interference between adjacent polysilicon patterns. In addition, the area of the dielectric layer in contact with the polysilicon pattern of the structure may be increased to increase the coupling ratio.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate the technical spirit of the present invention. The present invention may be embodied in various other forms without departing from the scope of the present invention. In the accompanying drawings, the dimensions of the substrate, film, region, pad or patterns are shown to be larger than the actual for clarity of the invention. In the present invention, when each film, region, pad or pattern is referred to as being formed "on", "upper" or "top surface" of a substrate, each film, region or pad, each film, region, Meaning that the pad or patterns are formed directly on the substrate, each film, region, pad or patterns, or another film, another region, another pad or other patterns may be additionally formed on the substrate. In addition, where each film, region, pad, region or pattern is referred to as "first," "second," "third," and / or "preliminary," it is not intended to limit these members, but only the cornea, To distinguish between areas, pads, regions or patterns. Thus, "first", "second", "third" and / or "preparation" may be used selectively or interchangeably for each film, region, pad, site or pattern, respectively.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail.

1 is a schematic cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device includes an active pattern having a first line width, device isolation patterns 126 defining the active pattern, a tunnel insulation pattern 108 provided on the active pattern, The polysilicon pattern 118 provided on the tunnel insulation layer pattern 108 and the spacers 114 provided on a portion of the tunnel insulation layer pattern 108 and the polysilicon pattern 118 are included. In addition, when the semiconductor device is a nonvolatile memory device, a dielectric layer 128 and a control gate 130 may be further provided on the polysilicon pattern 118.

The substrate 100 uses a semiconductor substrate 100 containing silicon (Si). The semiconductor substrate 100 may be doped with impurities. For example, the semiconductor substrate 100 may be doped with P-type impurities.

The substrate 100 includes active patterns and device isolation patterns 126. The active patterns are defined by the device isolation patterns 126. An upper portion of the active pattern has a first line width.

The device isolation pattern 126 may extend from the inside of the substrate 100 to the surface of the substrate 100 and protrude more than the surface of the substrate 100. The device isolation pattern 126 may include an oxide, for example, silicon oxide.

The tunnel insulating layer pattern 108 is provided on the active pattern. The tunnel insulation layer pattern 108 has a second line width wider than the first line width. The tunnel insulation layer pattern 108 may include an oxide, for example, silicon oxide.

The polysilicon pattern 118 is provided on the tunnel insulating layer pattern 108. The polysilicon pattern 118 includes a lower portion having the second line width and an upper portion having a third line width smaller than the second line width. The polysilicon pattern 118 may be doped with impurities.

Meanwhile, the upper sidewall of the polysilicon pattern 118 may have a vertical surface or a curved surface.

The polysilicon pattern 118 may function as a floating gate of the nonvolatile memory device. Therefore, as described above, the line width of the upper portion of the polysilicon pattern 118 is smaller than the line width of the lower portion, thereby reducing mutual interference between adjacent floating gates. In addition, the area in contact with the dielectric layer 128 is increased by the upper structure of the polysilicon pattern 118 as described above, thereby increasing the coupling ratio of the nonvolatile memory device.

Spacers 114 are provided on the lower sidewalls of the tunnel insulation pattern 108 and the polysilicon pattern 118. The spacers 114 may include an oxide, for example, silicon oxide.

Since the spacers 114 are provided on the lower sidewall of the polysilicon pattern 118, mutual interference between adjacent polysilicon patterns 118 may be suppressed.

In this case, as illustrated, the spacers 114 may be covered by the device isolation patterns 126. Thus, an upper portion of the device isolation patterns 126 may have a shape corresponding to an outer profile of the spacers 114 and the tunnel insulation layer pattern 108, and a lower portion of the device isolation patterns 126 may define the active patterns. The line width becomes smaller as.

The dielectric layer 128 is provided on the polysilicon pattern 118. In this case, the polysilicon pattern 118 provided under the dielectric layer 128 is isolated by the dielectric layer 128. The lower portion of the polysilicon pattern 118 has a rectangular shape, and the dielectric layer 128 extends in one direction.

The dielectric layer 128 may be formed along the outer wall of the upper portion of the polysilicon pattern 118 and the surface and the side surface of the lower portion of the polysilicon pattern 118 so that the dielectric layer 128 may be in contact with the polysilicon pattern 118 more widely. have. As a result, the coupling ratio is increased.

Examples of the dielectric film 128 may include a silicon oxide film, a composite dielectric film made of oxide / nitride / oxide (ONO), or a high dielectric constant material film. The high dielectric constant material film may include Y ₂ O ₃ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , BaTiO ₃ , SrTiO ₃ , and the like.

The control gate 130 is provided on the dielectric layer 128. In addition, the control gate 130 extends in the same direction as the dielectric layer 128. The control gate 130 may include polysilicon, metal or metal nitride.

Hereinafter, a method of forming the semiconductor device described above will be described in detail.

2 to 9 are cross-sectional views illustrating a method of forming the semiconductor device illustrated in FIG. 1.

Referring to FIG. 2, a tunnel insulating film 102, a polysilicon film 104, and a mask film (not shown) are sequentially formed on the semiconductor substrate 100.

The semiconductor substrate 100 may include silicon and may be doped with impurities.

The tunnel insulating layer 102 may be formed by performing a thermal oxidation or chemical vapor deposition (CVD) process on the semiconductor substrate 100. The tunnel insulating layer 102 may include an oxide, for example, may include silicon oxide.

A chemical vapor deposition process is performed on the tunnel insulating layer 102 to form a polysilicon layer 104. The polysilicon layer 104 may be doped with impurities.

A mask film is formed on the polysilicon film 104, and the mask film may include nitride, and for example, silicon nitride.

A photoresist pattern (not shown) is formed on the mask film to partially expose the mask film. The mask layer is etched using the photoresist pattern as an etching mask to form a mask pattern 106. After the mask pattern 106 is formed, the photoresist pattern may be removed by an ashing or strip process.

Referring to FIG. 3, the polysilicon layer 104 and the tunnel insulation layer 102 are sequentially etched using the mask pattern 106 as an etch mask to form the preliminary polysilicon pattern 110 and the tunnel insulation layer pattern 108. To form.

The tunnel insulation pattern 108 has a first line width, and the preliminary polysilicon pattern 110 also has a first line width that is the same as that of the tunnel insulation pattern 108.

The etching process is an anisotropic etching process, for example, may be a plasma dry etching process. Although not shown in detail, the mask pattern 106 may have an upper line width smaller than a lower line width due to the characteristics of the anisotropic etching process, and the lower line width may be the same as that of the tunnel insulation pattern 108. It can have a line width.

Referring to FIG. 4, preliminary spacers 112 are formed on sidewalls of the mask pattern 106, the preliminary polysilicon pattern 110, and the tunnel insulating layer pattern 108.

In more detail, the thin film is continuously formed along the top and side surfaces of the mask pattern 106, the side surfaces of the preliminary polysilicon pattern 110, the side surfaces of the tunnel insulating film pattern 108, and the surface of the substrate 100. Not formed). The thin film may include an oxide, for example, may include silicon oxide.

Subsequently, an entire anisotropic etching process is performed on the thin film until the surface of the mask pattern 106 is exposed. While the thin film formed on the surface of the mask pattern 106 is removed, the thin film formed on the substrate 100 is also removed, and the mask pattern 106, the preliminary polysilicon pattern 110, and the tunnel insulation pattern 108 are removed. The thin film formed on the side is hardly etched.

Accordingly, preliminary spacers 112 may be formed on side surfaces of the mask pattern 106, the preliminary polysilicon pattern 110, and the tunnel insulating layer pattern 108.

Referring to FIG. 5, the preliminary spacers 112 and the exposed substrate 100 are etched to form the spacers 114 and the preliminary trench 116.

The spacers 114 are formed on the lower sidewall of the preliminary polysilicon pattern 110, and the preliminary trench 116 extends downward along the sidewall profile of the preliminary spacers 112.

In more detail, the preliminary trench 116 is formed by etching the substrate 100 using the preliminary spacers 112 and the mask pattern 106 as an etch mask. In this case, a full anisotropic etching process is used as the etching process, for example, a plasma etching process. During the etching process, the upper and side portions of the preliminary spacers 112 may be etched together, and the upper surface of the mask pattern 106 may be partially etched.

Subsequently, an etching process is performed to etch upper portions of the preliminary spacers 112 to form spacers 114. The etching process may be, for example, wet etching as an isotropic etching process.

Due to the etching process, spacers 114 may be formed under the preliminary polysilicon pattern 110, and preliminary trenches 116 may be formed on the substrate 100.

Referring to FIG. 6, the upper portion of the preliminary polysilicon pattern 110 exposed by the spacers 114 and the preliminary trench 116 are etched to form a polysilicon pattern 118 and a trench 120.

The polysilicon pattern 118 includes a lower portion having the first line width and an upper portion having a second line width smaller than the first line width. The trench 120 is larger than the preliminary trench 116 and exposes a portion of the sidewall and the bottom of the tunnel insulating layer pattern 108.

In more detail, the upper portion of the polysilicon pattern 118 exposed by the spacers 114 and the mask pattern 106 is etched. The etching process uses wet etching using an etching solution. The etching solution has a very high etching rate for silicon.

While etching the exposed polysilicon pattern 118, an inner wall of the preliminary trench 116 is also etched. This is because the preliminary trench 116 includes silicon, and the inner wall of the preliminary trench 116 is etched by the etching solution. As a result, a trench 120 larger than the preliminary trench 116 is formed.

Due to the etching process, a polysilicon pattern 118 including a lower portion having a first line width and an upper portion having a second line width smaller than the first line width may be formed on the tunnel insulating layer pattern 108. In addition, spacers 114 are formed under the polysilicon pattern 118. The polysilicon pattern 118 as described above may function as a floating gate in the nonvolatile memory device. When the polysilicon pattern 118 functions as a floating gate, mutual interference between adjacent polysilicon patterns 118 may be suppressed due to the structure of the polysilicon pattern 118. More specifically, the upper portion of the polysilicon patterns 118 has a narrow line width, thereby increasing the separation distance between adjacent polysilicon patterns 118. The lower portions of the polysilicon patterns 118 have a wider line width than the upper portions, but may suppress mutual interference between adjacent polysilicon patterns 118 by the spacers 114.

Referring to FIG. 7, an isolation layer 122 may be formed on the mask pattern 106 to fill the trench 120. The device isolation layer 122 may include an oxide, and the oxide may include USG, O ₃ -TEOS USG, or HDP oxide having excellent gap filling properties.

Preferably, a high density plasma oxide film is formed by generating high density plasma using SiH ₄ , O ₂ and Ar gases as plasma sources. At this time, the trench 120 is embedded by improving the gap filling capability of the high density plasma oxide film so that cracks or voids inside the trench 120 are not generated.

Subsequently, the top surface of the device isolation layer 122 is removed by an etch back or chemical mechanical polishing process so that the top surface of the mask pattern 106 is exposed.

Referring to FIG. 8, the device isolation layer 122 is removed to expose the sidewall of the mask pattern 106 to form a device isolation pattern 126.

The device isolation layer 122 may be partially removed by wet etching or dry etching.

Referring to FIG. 9, the mask pattern 106 is removed to expose the top surface of the polysilicon pattern 118. The mask pattern 106 may be removed by wet etching or dry etching.

In this case, the upper portion of the device isolation pattern 126 may be removed while the mask pattern 106 is removed.

The substrate isolation layer is provided with an active region and a field region by the device isolation pattern 126 formed as described above. That is, the device isolation pattern 126 becomes a field region, and an active region is defined by the field region. The line width of the active region has a third line width smaller than the first line width of the tunnel insulation pattern 108.

Referring back to FIG. 1, a dielectric film 128 is continuously formed on the device isolation pattern 126 and the polysilicon pattern 118.

The dielectric layer 128 is continuously formed on the upper surface of the side and the upper side of the upper portion of the polysilicon pattern 118, thereby improving the contact area between the polysilicon pattern 118 and the dielectric layer 128. Can be. Thus, the coupling ratio of the dielectric layer 128 may be improved.

The dielectric layer 128 insulates the polysilicon pattern 118 from the control gate 130 formed thereafter. Examples of the dielectric film 128 include a composite dielectric film 128 formed of an oxide film / nitride film / oxide film, or a high dielectric material film made of a high dielectric constant material.

The composite dielectric film may be formed by an LPCVD process, and the high-k material film may be formed of Y ₂ O ₃ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , BaTiO ₃ , SrTiO ₃ , and the like, and may be atomic layer deposited. It may be formed by a layer deposition (ALD) process or a chemical vapor deposition process.

Subsequently, a conductive film for a control gate is formed on the dielectric layer 128. The conductive layer is formed by sequentially stacking thin films including metal silicides such as tungsten silicide (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), and tantalum silicide (TaSix) on the polysilicon layer 104 doped with impurities. It may have a structure.

Subsequently, the control gate conductive film, the dielectric film 128, the polysilicon pattern 118, and the tunnel insulating film pattern 108 are patterned to control the control gate 130, the dielectric film 128, the floating gate, and the tunnel oxide film pattern. Complete the gate structure of the nonvolatile memory device including a.

As described above, according to a preferred embodiment of the present invention, the polysilicon pattern used as the floating gate has a lower portion having a first line width and an upper portion having a second line width smaller than the first line width, thereby adjoining the floating gate. Mutual interference between them can be suppressed.

In addition, the coupling ratio can be improved by increasing the contact area between the dielectric film formed later and the polysilicon pattern.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (9)

An active pattern having a first line width; A tunnel dielectric layer pattern provided on the active pattern and having a second line width wider than the first line width; And And a polysilicon pattern including an upper portion having the second line width and a lower portion having a third line width smaller than the second line width on the tunnel insulating layer pattern. The semiconductor device of claim 1, further comprising: spacers disposed on lower sidewalls of the tunnel oxide layer pattern and the polysilicon pattern; And And device isolation patterns defining the active patterns. The semiconductor device of claim 2, wherein the spacers comprise an oxide. The semiconductor device of claim 1, wherein the lower sidewall of the polysilicon pattern has a curved surface. Forming a tunnel oxide pattern having a first line width on the substrate; A polysilicon pattern including an upper portion having the first line width and a lower portion having a second line width smaller than the first line width on the tunnel oxide film pattern; And And forming an active pattern having a third line width smaller than the first line width under the tunnel oxide film pattern. The method of claim 5, wherein after the tunnel oxide film pattern is formed, Forming a preliminary polysilicon pattern and a mask pattern having the first line width on the tunnel oxide film pattern; Forming spacers on sidewalls of the preliminary polysilicon pattern and the mask pattern; And And forming a trench by etching the substrate by using the mask pattern and the spacers as an etch mask. The method of claim 6, wherein a portion of the upper portion of the spacers is removed while the trench is formed to cover a lower portion of the preliminary polysilicon pattern and a sidewall of the tunnel insulation pattern. The method of claim 7, wherein a portion of the inner side of the trench is removed while the polysilicon pattern is formed. The method of claim 8, further comprising forming a device isolation pattern filling the trench.

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