KR20080053563A - Timing control module and display apparatus having the same - Google Patents

Abstract

A display apparatus is provided to monitor an operating state of various functions in a timing controller by implementing a watchdog routine in the timing controller. A display apparatus includes a timing controller(100), data and gate drivers, and a display panel(700). The timing controller outputs data and gate control signals in response to a main data signal and a main clock signal, which are inputted from the outside, and includes a watchdog routine that automatically recovers an erroneous operation by executing the reset. The data and gate drivers output data and gate signals in response to data and gate control signals, respectively. The display panel displays images by receiving the data and gate signals.

Description

TIMING CONTROL MODULE AND DISPLAY APPARATUS HAVING THE SAME}

1 is a block diagram conceptually illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a conceptual view illustrating a process of resetting a timing controller by a watchdog routine in FIG. 1.

3 is a block diagram illustrating in detail the timing control module of FIG. 1.

FIG. 4A is a block diagram illustrating a data comparator in the dynamic capacitance compensation (DCC) processor of FIG. 3.

4B is a waveform diagram illustrating signals in the clock comparator of FIG. 4A.

FIG. 5A is a block diagram illustrating a clock comparison unit in the signal input unit of FIG. 3.

5B is a waveform diagram illustrating signals in the clock comparator of FIG. 5A.

<Explanation of symbols for the main parts of the drawings>

100: timing control unit 110: signal input unit

120: signal processing unit 130: signal output unit

140: timing reset unit 200: memory unit

300: external clock generator 400: timing control module

500: data driver 600: gate driver

700: display panel 800: display device

The present invention relates to a display device, and more particularly to a display device having an automatic recovery function.

In general, a liquid crystal display device has a thin thickness, light weight, and low power consumption, and thus is mainly used for a monitor, a notebook, a mobile phone, and the like. The liquid crystal display includes a liquid crystal display panel displaying an image using a light transmittance of liquid crystal, and a driving unit electrically connected to the liquid crystal display panel to control the liquid crystal display panel.

The driving unit includes a timing controller, a data driver, and a gate driver. The timing controller outputs a data control signal and a gate control signal in response to an external control signal input from the outside. The data driver outputs a data signal to the liquid crystal display panel in response to the data control signal, and the gate driver outputs a gate signal to the liquid crystal display panel in response to the gate control signal.

On the other hand, the liquid crystal display may malfunction due to an electrical shock, that is, a momentarily strong voltage is applied, thereby degrading the display quality of the image. In detail, when a momentarily strong voltage is applied to the timing controller, the circuit in the timing controller may be affected, causing the timing controller to malfunction, thereby degrading the display quality of the image.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display device having an automatic recovery function to prevent a malfunction.

A display device according to an exemplary embodiment of the present invention includes a timing controller, a data driver, a gate driver, and a display panel.

The timing controller outputs a data control signal and a gate control signal in response to a main data signal and a main clock signal input from the outside, and resets a watchdog routine that can be automatically recovered by resetting in case of malfunction. Have The data driver outputs a data signal in response to the data control signal. The gate driver outputs a gate signal in response to the gate control signal. The display panel receives the data signal and the gate signal and displays an image.

The timing controller may include a signal input unit configured to receive the main data signal and the main clock signal and output an input internal signal, a signal processor configured to receive the input internal signal, process a signal, and output an output internal signal; A signal output part which is input to the output internal signal and outputs the data control signal and the gate control signal, and a timing reset part which resets the signal input part, the signal processing part and the signal output part in response to an external reset signal. It is desirable to.

According to the present invention, as the timing controller is reset when a malfunction is performed, the timing controller is automatically restored to prevent the display quality from being degraded.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram conceptually illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display device 800 according to the present exemplary embodiment includes a timing control module 400, a data driver 500, a gate driver 600, and a display panel 700.

The timing control module 400 receives the main data signal MDAT and the main clock signal MCLK from an external graphic controller (not shown), and in response thereto receives the data control signal DCON and the gate control signal GCON. Output

The timing control module 400 may include a timing controller 100, and may further include a memory unit 200 and an external clock generator 300.

The timing controller 100 outputs the data control signal DCON and the gate control signal GCON in response to the main data signal MDAT and the main clock signal MCLK. The timing controller 100 outputs an input memory signal SDAT1 having the current frame data currently being input to the memory unit 200.

The memory unit 200 receives the input memory signal SDAT1 from the timing controller 100, stores the current frame data, and outputs the output memory signal SDAT2 having the previous frame data that has already been stored. )

The external clock generator 300 generates an external clock signal OSC and outputs the external clock signal OSC to the timing controller 100.

On the other hand, a more detailed description of the timing control module 400 will be described later using a separate drawing.

The data driver 500 receives the data control signal DCON from the timing control module 400 and outputs the data signal DS to the display panel 700 in response to the data control signal DCON.

The gate driver 600 receives the gate control signal GCON from the timing control module 400 and outputs the gate signal GS to the display panel 700 in response thereto.

The display panel 700 receives the data signal DS and the gate signal GS from the data driver 500 and the gate driver 600, and displays an image in response thereto.

The display panel 400 includes an array substrate, an opposing substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the opposing substrate.

Specifically, for example, the array substrate may include a gate line GL formed in a first direction, a data line DL formed in a second direction perpendicular to the first direction, a gate line GL, and data. The thin film transistor TFT may be electrically connected to the wiring DL and the pixel electrode PE may be electrically connected to the thin film transistor. In this case, the pixel electrode PE is made of a transparent conductive material.

The opposing substrate includes a color filter expressing color, a common electrode made of a transparent conductive material, and a light shielding film covering the gate line GL, the data line DL, the thin film transistor TFT, and the like. In this case, the color filter may include a red color filter, a green color filter, and a blue color filter.

The liquid crystal layer is interposed between the array substrate and the counter substrate, the arrangement is changed by an electric field formed between the pixel electrode PE and the common electrode, thereby changing the light transmittance.

FIG. 2 is a conceptual view illustrating a process of resetting a timing controller by a watchdog routine in FIG. 1.

A process of resetting the timing controller 100 with reference to FIGS. 1 and 2 will be briefly described as follows.

The monitoring routine in the timing controller 100 determines whether input signals are normally input, output signals are normally output, and whether the main clock signal MCLK is normally input, between the timing controller 100 and the memory unit 200. It monitors in real time whether the signal transmission is normally performed, and whether various functions in the timing controller 100 are normally performed. As a result of the monitoring, if it is determined that a malfunction is being performed in the timing controller 100, the monitoring routine resets the timing controller 100 to restore normal operation automatically.

Hereinafter, the structural features of the monitoring routine in the timing controller 100 in each case will be described in detail.

3 is a block diagram illustrating in detail the timing control module of FIG. 1.

1 and 3, the timing control module 400 according to the present embodiment includes a timing controller 100, a memory unit 200, and an external clock generator 300.

The timing controller 100 includes, for example, a signal input unit 110, a signal processor 120, a signal output unit 130, and a timing reset unit 140.

The signal input unit 110 receives the main data signal MDAT and the main clock signal MCLK from the outside, and outputs the input internal signal DAT1 to the signal processor 120 in response thereto. In addition, the signal input unit 110 receives an external clock signal OSC from the external clock generator 300.

The signal processor 120 includes, for example, a dynamic capacitance compensation (DCC) processor 122 and an internal controller 124.

The DCC processor 122 receives the input internal signal DAT1 from the signal input unit 110. In this case, the input internal signal DAT1 includes image data and various other control signals.

The DCC processing unit 122 outputs the input memory signal SDAT1 including the current frame data currently being input to the memory unit 200 and output memory including previous frame data already stored in the memory unit 200. The signal SDAT2 is applied from the memory unit 200.

The DCC processing unit 122 compares the current frame data with the previous frame data, converts them through a built-in look-up table (LUT) according to a result of the comparison, and then provides a response speed of the display panel 700. Outputs an intermediate internal signal DAT2 that can improve.

The internal controller 124 receives the intermediate internal signal DAT2 from the DCC processing unit 122 to perform other internal signal processing functions, and outputs an output internal signal DAT3. The internal signal processing function includes color compensation processing according to red, green, and blue gamma curves.

Meanwhile, in the present exemplary embodiment, the signals are processed in the order of the DCC processing unit 122 and the internal control unit 124. Alternatively, the signals may be processed in the order of the internal control unit 124 and the DCC processing unit 122.

The signal output unit 130 receives the intermediate internal signal DAT2 from the internal controller 124, and outputs a data control signal DS and a gate control signal GS in response. The signal output unit 130 may change the signal level to output the data control signal DS and the gate control signal GS.

The timing reset unit 140 receives the first reset signal RST1 from the signal input unit 110, receives the second reset signal RST2 and the third reset signal RST3 from the signal processing unit 120, and receives a signal. The fourth reset signal RST4 is input from the output unit 130. The timing reset unit 140 may respond to the first to fourth reset signals RST1, RST2, RST3, and RST4, and may include the entire timing controller 100, that is, the signal input unit 110, the signal processor 120, and the signal output unit. (130) Reset all.

Meanwhile, the memory unit 200 receives the input memory signal SDAT1 from the DCC processing unit 122 of the signal processing unit 120, stores the current frame data, and outputs an output memory signal including the previously stored frame data ( The SDAT2 is output to the timing controller 100.

The external clock generator 300 generates an external clock signal OSC and outputs the external clock signal OSC to the timing controller 100.

Hereinafter, how the monitoring routine is configured and operated in the timing controller 100 will be described.

4A is a block diagram illustrating a data comparator in the DCC processor of FIG. 3, and FIG. 4B is a waveform diagram illustrating signals in the clock comparator of FIG. 4A.

First, referring to FIGS. 3, 4A, and 4B, the DCC processing unit 122 applies the input memory signal SDAT1 to the memory unit 200, and applies the output memory signal SDAT2 from the memory unit 200. Receive.

The input memory signal SDAT1 is applied to and stored in the memory unit 200 and includes current frame data and a first signature code 10. That is, the DCC processing unit 122 adds the first signature code 10 to the current frame data that is currently being input to create an input memory signal SDAT1 and applies it to the memory unit 200.

The output memory signal SDAT2 includes previous frame data and the second signature code 20 previously stored in the memory unit 200, and is applied from the memory unit 200 to the DCC processing unit 122.

That is, the first signature code 10 is any data to be transmitted and stored in the current memory unit 200, and the second signature code 20 is already stored in the memory unit 200 and transferred to the DCC processing unit 122. Since it is any data to be transmitted, it is preferable that they are identical to each other, and that the data is about 1 Kbit.

Further, the first and second signature codes 10, 20 are preferably transmitted during the vertical blank area so as not to affect the image data. That is, the first and second signature codes 10 and 20 are preferably transmitted while the data enable signal DE has a low level between the frames.

Meanwhile, the DCC processing unit 122 determines whether the first and second signature codes 10 and 20 are identical to each other, and outputs the second reset signal RST2 to the timing reset unit 140. 126 may include.

Specifically, the signature code monitoring unit 126 receives the first and second signature codes 10 and 20 and determines whether they are the same, and when the first and second signature codes 10 and 20 are the same. When the second reset signal RST2 having a high level is continuously output, and the first and second signature codes 10 and 20 are not identical to each other, the second reset signal RST2 has a low level for a while and then has a high level again. The second reset signal RST2 is output.

In this case, when a strong voltage or the like is applied to the display device 800, the current frame data and the previous frame data may be changed, or signal transmission between the DCC processing unit 122 and the memory unit 200 may not be normally performed. have.

Accordingly, by comparing the first and second signature codes 10 and 20 with each other, whether the current frame data and the previous frame data are normal data or a signal transfer between the DCC processing unit 122 and the memory unit 200. It can be determined whether this is normally done. That is, when the first and second signature codes 10 and 20 are not equal to each other by comparing the first and second signature codes 10 and 20, the timing controller 100 may be reset to automatically recover the timing controller 100.

Secondly, the internal control unit 124 of the signal processing unit 120 determines whether various other internal signal processing functions are normally performed, and outputs the third reset signal RST3 to the timing reset unit 140. It may include a signal processing monitor (not shown).

In detail, the internal signal processing monitor determines whether the internal signal processing function is normally performed, and when the internal signal processing function is normally performed, outputs a third reset signal RST3 having a high level, and When the internal signal processing function is not normally performed, the third reset signal RST3 takes a low level and outputs a high level again.

Accordingly, when the internal signal processing function is not normally performed due to an external strong voltage, the timing controller 100 may be automatically restored by resetting the timing controller 100.

5A is a block diagram illustrating a clock comparator in the signal input unit of FIG. 3, and FIG. 5B is a waveform diagram illustrating signals in the clock comparator of FIG. 5A.

3, 5A, and 5B, the signal input unit 110 determines whether the main clock signal MCKL is normally input by comparing the main clock signal MCLK and the external clock signal OSC. And a clock monitoring unit 112 for outputting one reset signal RST1 to the timing reset unit 140.

Specifically, for example, the clock monitor 112 receives the main clock signal MCLK and the external clock signal OSC to synchronize the main clock signal MCLK and the external clock signal OSC with each other, and the external clock. When the main clock signal MCLK is normally input based on the signal OSC, the first reset signal RST1 having a high level is continuously output, and the main clock signal MCLK based on the external clock signal OSC. When is not normally input, the low level is briefly output and the first reset signal RST1 having the high level is output again. Here, the external clock signal OSC is preferably not changed by an external strong voltage or the like.

Therefore, when the main clock signal MCLK is not normally input to the signal input unit 110, the timing controller 100 may be reset and automatically restored.

Meanwhile, referring to FIG. 3, the signal input unit 110 determines whether the main data signal MDAT is normally input and outputs the first reset signal RST1 to the timing reset unit 140. Not shown) may be further included.

Specifically, the input data monitoring unit receives the main data signal MDAT, and when the main data signal MDAT is normally input, outputs the first reset signal RST1 having a high level, and the main data signal. When the MDAT is not normally input, the first reset signal RST1 having a low level and outputting a high level is output again.

Therefore, when the main data signal MDAT is not normally input to the signal input unit 110, the timing controller 100 may be reset and automatically restored.

Finally, referring back to FIG. 3, the signal output unit 130 determines whether the data control signal DS and the gate control signal GS are normally output, and then supplies the fourth reset signal RST4 to the timing reset unit ( It may include an output data monitoring unit (not shown) output to the 140.

In detail, the output data monitoring unit receives the data control signal DS and the gate control signal GS and has a high level when the data control signal DS and the gate control signal GS are normally output. When the fourth reset signal RST4 is output and the data control signal DS and the gate control signal GS are not normally output, the fourth reset signal RST4 has a low level for a while and then has a high level again. Outputs

Therefore, when the data control signal DS and the gate control signal GS are not normally output from the signal output unit 130, the timing control unit 100 may be reset and automatically restored.

According to the present invention, a monitoring routine is formed in the timing controller so that the input signals are normally input, the output signals are normally output, the main clock signal is normally input, and the signal is transferred between the timing controller and the memory unit. May monitor in real time whether the functions are normally performed or other functions in the timing controller are normally performed.

Therefore, if it is determined that a malfunction is being performed in the timing controller by the monitoring routine in the timing controller, the monitoring routine can reset the timing controller to automatically restore normal operation, and as a result, display quality of the image is further improved. Can be.

In the detailed description of the present invention described above with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (12)

A timing controller having a watchdog routine capable of outputting a data control signal and a gate control signal in response to a main data signal and a main clock signal input from an external source, and resetting and automatically recovering in case of malfunction; And A data driver outputting a data signal in response to the data control signal; A gate driver configured to output a gate signal in response to the gate control signal; And And a display panel configured to receive the data signal and the gate signal and display an image. The method of claim 1, wherein the timing controller A signal input unit which receives the main data signal and the main clock signal and outputs an input internal signal; A signal processor configured to receive the input internal signal and process a signal to output an output internal signal; A signal output unit which receives the output internal signal and outputs the data control signal and the gate control signal; And And a timing reset unit for resetting the signal input unit, the signal processing unit, and the signal output unit in response to an external reset signal. The display device of claim 2, wherein the signal input unit comprises an input data monitor configured to determine whether the main data signal is normally input and output the reset signal to the timing reset unit. The display device of claim 2, further comprising an external clock generator configured to generate an external clock signal and apply the external clock signal to the signal input unit. The signal input unit of claim 4, wherein the signal input unit comprises a clock monitor configured to determine whether the main clock signal is normally input by comparing the main clock signal and the external clock signal, and output the reset signal to the timing reset unit. Display device characterized in that. The display apparatus of claim 2, wherein the signal output unit comprises an output data monitor configured to determine whether the data control signal and the gate control signal are normally output and to output the reset signal to the timing reset unit. . The method of claim 2, wherein the signal processing unit A DCC processor configured to receive and process the input internal signal and output an intermediate internal signal for improving a response speed of the display panel; And And an internal controller configured to receive the intermediate internal signal and perform an internal signal processing function to output the output internal signal. The display device according to claim 7, wherein the internal control unit includes an internal signal processing monitoring unit for determining whether the other internal signal processing function is normally performed and outputting the reset signal to the timing reset unit. The display device of claim 7, further comprising a memory unit configured to receive current data currently input from the DCC processing unit, and output previously stored data to the DCC processing unit. 10. The method of claim 9, wherein the DCC processing unit outputs an input memory signal to which the first signature code is added to the current data to the memory unit, And an output memory signal having the previous data and the second signature code from the memory unit. The display apparatus according to claim 10, wherein the DCC processing unit comprises a signature code monitoring unit which determines whether the first and second signature codes are the same and outputs the reset signal to the timing reset unit. 11. The display device of claim 10, wherein the first and second signature codes are transmitted during a vertical blank area.

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