KR20080052920A - Manufacturing method of thin film transistor array panel - Google Patents

Abstract

A method for manufacturing a TFT(Thin Film Transistor) display plate is provided to manufacture a TFT display plate stably having a new pixel electrode which doesn't contain indium. Gate electrodes are formed on a substrate. Source and drain electrodes, which are insulated from the gate electrodes, are formed. Pixel electrodes, connected to the drain electrodes, are formed. In forming the pixel electrodes, a transparent conductive oxidation film which doesn't contain indium is deposited. A photosensitive layer is formed on the transparent conductive oxidation film. Using the photosensitive layer as a mask, etching for the transparent conductive oxidation film is performed. Using a stripper, the photosensitive layer is removed.

Description

Manufacturing method of thin film transistor array panel {MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor array panel formed by a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines II-II and III-III.

4, 7, 7, 10, 13, and 16 are layout views sequentially illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

5 and 6 are cross-sectional views of the thin film transistor array panel of FIG. 4 taken along lines V-V and VI-VI.

8 and 9 are cross-sectional views illustrating the thin film transistor array panel of FIG. 7 taken along the line VII-VII and VII-VII.

11 and 12 are cross-sectional views of the thin film transistor array panel of FIG. 10 taken along lines XI-XI and XII-XII.

14 and 15 are cross-sectional views of the thin film transistor array panel of FIG. 13 taken along lines XIV-XIV and XV-XV.

17 and 18 are cross-sectional views of the thin film transistor array panel of FIG. 16 taken along lines X′-X ′ and X′-X ′.

19 is a view showing an etching result using an etchant according to an embodiment of the present invention and the profile of the transparent conductive oxide film after removing the photosensitive film using a stripper.

<Description of Drawing>

81, 82 ... contact aid member 110 ... substrate

131, 132 ... hold electrode wires 133a, 133b ... hold electrode

121, 129 ... gate line 124 ... gate electrode

140 Gate insulating film 151, 154 Semiconductor

161, 163, 165 ... resistive contact layers 171, 179 ... data lines

173 Source electrode 175 Drain electrode

180 ... shield 181, 182, 185 ... contact hole

191 ... pixel electrode

The present invention relates to a method of manufacturing a thin film transistor array panel.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic light emitting diode display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) for transmitting a scan signal to the thin film transistor and a data line for transmitting a data signal, in addition to the thin film transistor and the pixel electrode connected thereto.

The thin film transistor is formed of a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a semiconductor layer facing the gate electrode with an insulating layer therebetween. The data signal from the data line is transferred to the pixel electrode in accordance with the scanning signal of.

The pixel electrode is mainly formed using a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, as the price of indium used for the pixel electrode increases, the manufacturing cost of the thin film transistor array panel increases. Therefore, researches on new pixel electrodes containing no indium have been actively conducted.

Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor array panel including a pixel electrode that does not contain an indium component.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming a gate electrode on a substrate, forming a source electrode and a drain electrode insulated from the gate electrode, and a pixel electrode connected to the drain electrode. The forming of the pixel electrode may include depositing a transparent conductive oxide film, forming a photoresist film on the transparent conductive oxide film, and etching the transparent conductive oxide film using an etching solution using the photosensitive film as a mask. And removing the photosensitive film using a stripper.

The transparent conductive oxide film may be made of ZAO or ZGO.

The etchant may include 5% to 40% of hydrogen peroxide (H ₂ O ₂ ).

The stripper may comprise 1% to 30% of diethanolamine (DEA).

The etchant may include 1% to 20% citric acid, 5% to 40% hydrogen peroxide (H ₂ O ₂ ), 0.001% to 5% hydrofluoric acid (HF), 60% to 95% ultrapure water. .

The stripper may comprise 1% to 30% of diethanolamine (DEA), 10% to 50% of N-methyl pyrrolidone (NMP), and 30% to 90% of butyl diglycol. have.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, the thin film transistor array panel manufactured by the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a layout view of a thin film transistor array panel formed by a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 show the thin film transistor array panel of FIG. It is sectional drawing cut along the line.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding downward and a wide end portion 129 for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110, It may be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may be extended to be directly connected thereto.

The storage electrode line 131 receives a predetermined voltage and includes a stem line 132 extending substantially in parallel with the gate line 121 and a plurality of pairs of first and second storage electrodes 133a and 133b separated therefrom. . Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line 132 is close to the bottom of the two gate lines 121. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line 132 and a free end opposite thereto. The fixed end of the first sustain electrode 133a has a large area, and its free end is divided into two parts, a straight portion and a bent portion. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, or molybdenum ( It may be made of molybdenum-based metals such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film and an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the storage electrode line 131 may be made of various other metals or conductors.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131.

On the gate insulating layer 140, a plurality of semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polycrystalline silicon, or the like are formed. The semiconductor 151 mainly extends in the vertical direction and includes a plurality of projections 154 extending toward the gate electrode 124. The semiconductor 151 has a wider width in the vicinity of the gate line 121 and the storage electrode line 131 and covers them widely.

A plurality of linear and island ohmic contacts 161 and 165 are formed on the semiconductor 151. The ohmic contacts 161 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and runs between adjacent sets of storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and bent in a J-shape and a wide end portion 179 for connection with another layer or an external driving circuit. do. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with respect to the gate electrode 124. Each drain electrode 175 includes one wide end and the other end having a rod shape. The wide end portion overlaps the storage electrode line 131, and the rod-shaped end portion is partially surrounded by the source electrode 173.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film. It may have a multilayer structure including (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data line 171 and the drain electrode 175 may be made of various metals or conductors.

The side of the data line 171 and the drain electrode 175 may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 thereon, and lower the contact resistance therebetween. In most places, the semiconductor 151 is narrower than the data line 171, but as described above, the width of the semiconductor 151 is widened at the portion meeting the gate line 121 to smooth the profile of the surface to prevent the data line 171 from being disconnected. do. The semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed semiconductor 151. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and the dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 151 while maintaining excellent insulating properties of the organic layer.

In the passivation layer 180, a plurality of contact holes 182 and 185 exposing the end portion 179 and the drain electrode 175 of the data line 171 are formed, respectively, and the passivation layer 180 and the gate insulating layer are formed. In the 140, a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 and a plurality of contact holes 183a exposing a part of the storage electrode line 131 near the fixed end of the first storage electrode 133a. And a plurality of contact holes 183b exposing the free end protrusion of the first sustain electrode 133a.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. The pixel electrode 191 may be made of a transparent conductive oxide film such as Al doped ZnO (ZAO) or Ga doped ZnO (ZGO).

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied has a liquid crystal between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. The direction of liquid crystal molecules (not shown) of the layer (not shown) is determined. The polarization of light passing through the liquid crystal layer varies according to the direction of the liquid crystal molecules determined as described above. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 and the drain electrode 175 connected to the pixel electrode 191 overlap with the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor formed by the pixel electrode 191 and the drain electrode 175 electrically connected to the pixel electrode 191 overlapping the storage electrode line 131 is called a storage capacitor, and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor.

The connecting leg 83 crosses the gate line 121 and exposes the exposed portion of the storage electrode line 131 and the storage electrode through contact holes 183a and 183b positioned on opposite sides with the gate line 121 interposed therebetween. 133b) is connected to the exposed end of the free end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 to 3 will be described in detail with reference to FIGS. 4 to 18.

4, 7, 10, 13, and 16 are layout views sequentially illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 5 and 6 respectively illustrate the thin film transistor array panel of FIG. 4. 8 and 9 are cross-sectional views of the thin film transistor array panel of FIG. 7 taken along lines VIII-VIII and IX-IX, and FIGS. 11 and 12. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along lines XI-XI and XII-XII, and FIGS. 14 and 15 are cut along the XIV-XIV line and XV-XV lines of FIG. 13. 17 and 18 are cross-sectional views of the thin film transistor array panel of FIG. 16 taken along lines XVII-XVII and XVIII-XVIII.

4 to 6, a plurality of gate lines 121 and sustain electrodes 133a and 133b including a gate electrode 124 and an end portion 129 on an insulating substrate 110 made of transparent glass or plastic. A plurality of storage electrode lines 131 including the plurality of electrodes are formed.

As shown in FIGS. 7 to 9, an intrinsic semiconductor including a protrusion 154 may be formed by stacking a gate insulating layer 140 on the entire surface of the substrate 110, and then stacking a semiconductor layer and patterning the same through a photolithography process. A plurality of impurity semiconductors 161 including 151 and a plurality of impurity semiconductor patterns 164 are formed.

The data metal layer is formed on the impurity semiconductor 161.

10 to 12, a plurality of data lines 171 and a plurality of drain electrodes including a source electrode 173 and an end portion 179 are patterned by patterning the stacked data metal layer 170 through a photolithography process. 175 is formed.

Subsequently, the portions of the impurity semiconductor 164 that are not covered by the data line 171 and the drain electrode 175 are removed to remove the exposed portions, and the plurality of linear ohmic contacts 161 including the protrusions 163 and the plurality of island resistive electrodes. While completing the contact member 165, the portion of the intrinsic semiconductor 154 beneath it is exposed.

As shown in FIGS. 13 to 15, the passivation layer 180 is stacked and patterned together with the gate insulating layer 140, so that the end portion 129 of the gate line 121 is formed on the passivation layer 180 and the gate insulating layer 140. , An end portion 179 of the data line 171, a portion of the storage electrode line 131 near the fixed end of the first storage electrode 133a, a portion of the free end protrusion of the first storage electrode 133a, and a drain electrode 175. A plurality of contact holes 181, 182, 183a, 183b, and 185, respectively, are formed.

16 to 18, a transparent conductive oxide film such as ZAO (Al doped ZnO) or ZGO (Ga doped ZnO) is formed on the entire surface of the substrate, and a plurality of pixel electrodes 191 through a photolithography process. A plurality of contact assisting members 81 and 82 and a plurality of connecting legs 83 are formed.

The etching solution for etching the transparent conductive oxide film in this photolithography process is 1% to 20% citric acid, 5% to 40% hydrogen peroxide (H 2 O 2), 0.001% to 5% hydrofluoric acid (HF), 60% to 95 It is preferred to include ultrapure water in%.

In addition, the stripper for removing the photoresist in the photolithography process is 1% to 30% diethanolamine (DEA), 10% to 50% N-methyl pyrrolidone (NMP), 30% to 90% It is preferable to include the butyl diglycol (Butyl diglycol).

Next, an etching result using the etchant according to an embodiment of the present invention and a profile of the transparent conductive oxide film after removing the photosensitive film using the stripper will be described with reference to FIG. 19.

In the present experimental example, the ZAO film was formed to a thickness of 900Å on the substrate, and the etching degree of the ZAO film was etched using a photosensitive film as a mask.

Referring to FIG. 19, an etching solution containing 1% to 20% citric acid, 5% to 40% hydrogen peroxide (H 2 O 2), 0.001% to 5% hydrofluoric acid (HF), and 60% to 95% ultrapure water After 5 seconds, the side skew becomes about 0.658μm, and after 10 seconds, the side skew becomes about 0.803μm, and after 20 seconds, the side skew becomes 1.071μm. It is about.

Thus, to etch the ZAO film comprising 1% to 20% citric acid, 5% to 40% hydrogen peroxide (H2O2), 0.001% to 5% hydrofluoric acid (HF), 60% to 95% ultrapure water Using an etchant can obtain a proper etching rate.

In addition, referring to FIG. 19, 1% to 30% diethanolamine (DEA), 10% to 50% N-methyl pyrrolidone (NMP), and 30% to 90% butyl diglycol Removing the photoresist using a stripper containing a ZAO film thickness of 900Å regardless of time can be obtained a stable profile.

Therefore, when the etching solution and the stripper according to the embodiment of the present invention are used, the pixel electrode using the ZAO film can be stably manufactured.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the thin film transistor array panel including the new pixel electrode containing no indium component can be stably manufactured.

Claims (6)

Forming a gate electrode on the substrate, Forming a source electrode and a drain electrode insulated from the gate electrode, and Forming a pixel electrode connected to the drain electrode Including; The forming of the pixel electrode may include depositing a transparent conductive oxide film not including indium; Forming a photoresist film on the transparent conductive oxide film, Etching the transparent conductive oxide film using an etching solution using the photosensitive film as a mask, and And removing the photosensitive film using a stripper. In claim 1, The transparent conductive oxide film is a manufacturing method of a thin film transistor array panel made of ZAO or ZGO. In claim 1, The etchant comprises 5% to 40% of hydrogen peroxide (H ₂ O ₂ ) manufacturing method of a thin film transistor array panel. In claim 1, The stripper is a manufacturing method of a thin film transistor array panel comprising 1% to 30% of diethanolamine (DEA). In claim 1, The etchant comprises 1% to 20% citric acid, 5% to 40% hydrogen peroxide (H ₂ O ₂ ), 0.001% to 5% hydrofluoric acid (HF), 60% to 95% ultrapure water The manufacturing method of a display panel. In claim 1, The stripper is a thin film comprising 1% to 30% of diethanolamine (DEA), 10% to 50% of N-methyl pyrrolidone (NMP), and 30% to 90% of butyl diglycol Method for manufacturing a transistor display panel.

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