KR20080050033A - Display apparatus and method of manufacturing the same - Google Patents

Abstract

A display device and a manufacturing method thereof are provided to enable a barrier to prevent impurities, present between first and second substrates, from moving between neighboring pixel areas, thereby preventing afterimages in the display device. In a first substrate(100), pixel areas(PA) are formed. A second substrate(200) faces the first substrate to be coupled with the first substrate. A spacer(S) is interposed between the first and second substrates, and spaces the first substrate from the second substrate. A barrier(B) is made from the same material as the spacer, and installed between the pixel areas. The barrier prevents impurities from moving between the pixel areas.

Description

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME}

1A-1C are diagrams illustrating the principle of operation of the present invention.

2A is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along the cutting line II ′ of FIG. 2A.

3A is a plan view illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

3B is a cross-sectional view taken along the line II-II ′ of FIG. 3A.

4A is a plan view illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

4B is a cross-sectional view taken along the cutting line III-III ′ of FIG. 4A.

5 is a cross-sectional view illustrating a process of manufacturing a spacer and a barrier according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100, 300-array board 200, 400-color filter board

170, 370-Pixel electrode 331-First color filter layer

332-Second Color Filter Layer B-Barrier

DL-data line GL-gate line

PA-Pixel Area S-Spacer

T1, T2-first and second thin film transistors

The present invention relates to a display device and a method for manufacturing the same, and more particularly, to a display device and a method for manufacturing the same that can improve the display quality.

In the display device for displaying an image, the most recent problem is afterimage. An afterimage is a residual image or an afterimage, depending on whether the previous image remains in the currently displayed image.

Such afterimages are generated not only in most display devices such as TVs, computers, and laptops, but also in liquid crystal display devices of a PID (Public Information Display) system that continuously display the same screen.

Although the afterimage is caused by various causes, in particular, it is known to be caused by impurities present in the display device. In general, the display device includes two substrates spaced apart at regular intervals to face each other, and an image is displayed by the interaction of the two substrates. A constant space is formed between the two substrates. When impurities exist in the spaces between the substrates, line or surface afterimages are caused by the impurities. In particular, the residual afterimage is caused by impurities moving and accumulating on the interface of patterns driven in different grays.

Accordingly, there is a need for a method for improving display quality of a display device by preventing impurities in the display device from moving and accumulating on the interface of the pattern.

Accordingly, it is an object of the present invention to provide a display device which can improve the display quality of a display device by preventing impurities from moving in the display device.

Another object of the present invention is to provide a method of manufacturing the display device.

A display device according to the present invention for achieving the above object includes a first substrate, a second substrate, a spacer and a barrier.

Pixel regions are formed in the first substrate, and the second substrate is coupled to face the first substrate. The spacer is interposed between the first substrate and the second substrate to space the first substrate and the second substrate. The barrier is formed of the same material as the spacer and is provided between the pixel areas to block impurities from moving between the pixel areas. The barrier is formed on one of the first substrate and the second substrate and spaced apart from the other substrate.

The first substrate may include gate lines disposed adjacent to each of the pixel regions and extending in one direction, data lines crossing the gate lines to be insulated from each other, and pixel electrodes formed to correspond to the pixel regions. It includes more. The second substrate includes a first color filter layer formed corresponding to the pixel electrodes, and a second color filter layer formed between the spacer and the second substrate.

Specifically, the barrier has a closed loop shape formed along a boundary between the pixel electrodes. Alternatively, the barrier may have an opening formed along a boundary between the pixel electrodes and a portion of which is removed. The barrier may include protrusions formed along a boundary of the pixel regions and spaced apart from each other, and the spaced protrusions are alternately disposed.

A method of manufacturing a display device according to the present invention is as follows. A first substrate having pixel regions is formed, and a second substrate is formed to be opposed to the first substrate. A spacer spaced apart from the first substrate and the second substrate is formed on one of the first substrate and the second substrate. A barrier is formed of the same material as the spacer and provided between the pixel regions to block impurities from moving between the pixel regions. The barrier is formed on one of the first substrate and the second substrate, and is formed spaced apart from the other substrate.

According to such a display device and a method of manufacturing the same, it is possible to prevent impurities between the first substrate and the second substrate from moving between pixel regions to prevent afterimages caused by the movement and accumulation of the impurities.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be applied and modified in various forms. Rather, the following embodiments are provided to clarify the technical spirit disclosed by the present invention, and furthermore, to fully convey the technical spirit of the present invention to those skilled in the art having an average knowledge in the field to which the present invention belongs. Therefore, the scope of the present invention should not be construed as limited by the embodiments described below. In addition, in the drawings presented in conjunction with the following examples, the sizes of the respective areas are simplified or somewhat exaggerated in order to emphasize clear explanations, and like reference numerals in the drawings denote like elements.

1A-1C are diagrams illustrating the principle of operation of the present invention.

FIG. 1A illustrates a predetermined image displayed on a screen of a display device, for example, a liquid crystal display using liquid crystal. Referring to FIG. 1A, an image having a predetermined pattern P is displayed by pixels of a rectangular pixel in the form of a matrix. When the pattern P is displayed for a long time, line afterimage occurs on the boundary portion of the pattern P. FIG.

1B illustrates the cause of the above-mentioned afterimage. Referring to FIG. 1B, the liquid crystal display includes two substrates 1 and 4. The two substrates 1 and 4 are divided into an upper substrate 4 and a lower substrate 1 for convenience. The upper substrate 4 and the lower substrate 1 are provided with an upper electrode 3 and a lower electrode 2 to which a voltage is applied, respectively. When a voltage is applied to the upper electrode 3 and the lower electrode 2, an electric field is applied between the upper substrate 4 and the lower substrate 1 due to the difference in the applied voltage.

The liquid crystal LC is arranged between the upper substrate 3 and the lower substrate 2. The electric field acts in a direction perpendicular to the upper substrate 4 and the lower substrate 1, and the liquid crystal LC has dielectric anisotropy and is inclined in a predetermined direction D by the electric field.

Impurities 5 and 6 having polarity exist between the upper substrate 4 and the lower substrate 1, and the impurities 5 and 6 are moved by a force in a direction in which the liquid crystal LC is inclined. The direction D in which the liquid crystal LC is inclined is divided into a first direction D1 and a second direction D2 that are perpendicular to each other, and when a force is applied in the first direction D1, a boundary (dotted line) of the pixel is applied. Mark). At this time, the positive impurity 5 and the negative impurity 6 move in opposite directions, and an afterimage occurs as impurities 5 and 6 of the same polarity accumulate in a predetermined region such as the boundary of the pattern P. do.

Fig. 1C shows the principle of preventing the generation of afterimages. Referring to FIG. 1C, a wall 7 is formed at the boundary of the pixel between the upper substrate 4 and the lower substrate 1. The wall 7 physically blocks the movement of the impurities 5, 6. In addition, by reducing the magnitude of the electric field at the boundary of the pixel, the force acting on the impurities 5 and 6 is reduced, and the impurities 5 and 6 do not pass through the boundary of the pixel to prevent afterimages.

FIG. 2A is a plan view showing a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along the cutting line I-I ′ of FIG. 2A.

2A and 2B, the liquid crystal display 710 according to the present invention includes an array substrate 100, a color filter substrate 200, a spacer S, and a barrier B. The liquid crystal display 710 further includes a liquid crystal layer 50 interposed between the array substrate 100 and the color filter substrate 200 to control light transmittance.

The array substrate 100 includes a first base substrate 110 and pixel regions PA formed on the first base substrate 110. In the drawing of the present invention, not all the pixel areas PA are shown, only two pixel areas PA are shown. However, the pixel areas PA have the same structure.

The array substrate 100 further includes gate lines GL and data lines DL, which are formed on the first base substrate 110 and cross each other insulated from each other, and define the pixel regions PA. . The gate lines GL extend in a first direction D1 and the data lines DL extend in a second direction D2 orthogonal to the first direction D1.

 In addition, the array substrate 100 further includes thin film transistors T disposed on one side of the pixel areas PA and pixel electrodes 170 formed corresponding to the pixel areas PA. The thin film transistors T are electrically connected to the pixel electrodes 170 to apply pixel voltages provided to the pixel electrodes 170.

The thin film transistors T may include gate electrodes 121 branched from the gate lines DL, semiconductor patterns 140 formed on the gate electrodes 121, and data lines DL. Source electrodes 151 branched and formed on the semiconductor patterns 140 and drain electrodes 152 spaced apart from the source electrodes 151 are included. A gate insulating layer 131 is provided between the gate electrodes 121 and the semiconductor patterns 140. The semiconductor patterns 140 may be formed of a double layer of ohmic contact patterns 142 separated from the active patterns 141.

The first base substrate 110 may further include a passivation layer 161 covering the thin film transistors T, the data lines DL, and an organic insulating layer 162 formed on the passivation layer 161. do. Contact holes CH are formed in the passivation layer 161 and the organic insulating layer 162 to expose the drain electrodes 152. The pixel electrodes 170 are formed on the organic insulating layer 162 to correspond to the pixel areas PA, and are electrically connected to the drain electrodes 152 through the contact holes CH. Connected.

The array substrate 100 further includes a first storage electrode SE1, a second storage electrode SE1, and a storage line SL. The first storage electrode SE1 is spaced apart from the gate lines GL and provided in the pixel areas PA, respectively, and the second storage electrode SE2 extends from the drain electrodes 152. The first storage electrode SE1 is disposed to face the first storage electrode SE1. The storage capacitor Cst is formed by the first storage electrode SE1, the gate insulating layer 131, and the second storage electrode SE2. The storage line SL is electrically connected to the first storage electrode SE1 to transmit an electrical signal provided from a gate driver (not shown) to the first storage electrode SE1. In addition, the organic insulating layer 162 is removed in the region where the second storage electrode SE2 is formed to expose the passivation layer 161.

The color filter substrate 200 is coupled to face the array substrate 100, and includes a second base substrate 210, a black matrix 220, a color filter layer 230, and a common electrode 240.

The second base substrate 210 is a substrate made of a transparent material that transmits light. The second base substrate 210 faces the first base substrate 110, and the black matrix 220, the color filter layer 230, and the common electrode are formed on an upper surface of the second base substrate 210. 240 is formed.

The black matrix 220 may be formed on the second base substrate 210 to correspond to the ineffective display area of the array substrate 100. That is, the array substrate 100 is divided into an effective display area where an image is displayed and an invalid display area where an image is not displayed. The ineffective display area is an area in which the gate lines GL, the data lines DL, and the thin film transistors T are formed. In this case, the image is not substantially displayed because light is not transmitted. The black matrix 220 is formed in the ineffective display area to block light leaking from the peripheral portions of the pixel areas PA.

The color filter layer 230 is formed on the second base substrate 210 to face the pixel electrodes 170. The color filter layer 230 is formed of any one of red, green, and blue color pixels corresponding to three primary colors of light, and displays a color image by the combination of the three colors. Each of the red, green, and blue color pixels is formed to correspond to the pixel areas PA. The common electrode 240 is disposed on the black matrix 220 and the color filter layer 230 and faces the pixel electrodes 170 with the liquid crystal layer 50 therebetween.

On the other hand, the liquid crystal layer 50 is interposed between the array substrate 100 and the color filter substrate 200, and consists of a plurality of liquid crystal molecules. When the liquid crystal display 710 is operated, a gate-on signal is applied along the gate lines GL to turn on the thin film transistors T, and a data signal is applied along the data lines DL. The pixel voltage is applied to the pixel electrodes 170. In addition, a common voltage is applied to the common electrode 240 to form an electric field according to the difference between the common voltage and the pixel voltage between the array substrate 100 and the color filter substrate 200. The electric field acts on the liquid crystal molecules, and the arrangement direction of the liquid crystal molecules changes. The transmittance of light provided from the outside is adjusted according to the alignment direction of the liquid crystal molecules, and an image corresponding to the transmittance of the light is displayed on the display area.

The spacer S is interposed between the array substrate 100 and the color filter substrate 200 to space the array substrate 100 and the color filter substrate 200. The spacer S may correspond to the array substrate 100 and the color filter substrate corresponding to an area in which the first storage electrode SE1 is formed or an invalid display area so as not to reduce the aperture ratio of the pixel areas PA. Between 200). In addition, the spacer S is formed on any one of the array substrate 100 and the color filter substrate 200. In the present embodiment, an example in which the spacer S is formed on the color filter substrate 200 corresponding to a region where the first storage electrode SE1 is formed is described.

The barrier B is provided between the pixel areas PA to prevent impurities from moving between the pixel areas PA. The barrier B is formed on any one of the array substrate 100 and the color filter substrate 200. It may be formed of the same material as the spacer (S), and may be formed simultaneously in the same process as the spacer (S). For example, when the spacer S is a column spacer, the spacer S and the barrier B may be formed using a photoresist. In the exemplary embodiment of the present invention, an example in which the barrier B is formed on the color filter substrate 200 similarly to the spacer S is described.

The barrier B may have a closed loop shape formed along a boundary of the pixel electrodes 170. In addition, the barrier B may be formed along a boundary of the pixel electrodes 170 and may have an opening in which a portion thereof is removed. In the present exemplary embodiment, an example in which the barrier B is provided corresponding to an area where the gate lines GL and the data lines DL are formed so as not to reduce the aperture ratio of the pixel areas PA is described. do. The barrier B is spaced apart from the first barrier B1 and the first barrier B disposed in parallel to the gate lines GL, and the second barrier B is disposed in parallel to the data lines DL. Barrier B2 is included.

As an example of impurities present between the array substrate 100 and the color filter substrate 200, the ionic impurities of the liquid crystal are moved by the electric field. The impurity is limited to movement by the barrier B formed at the boundary of the pixel areas PA and thus cannot move to the adjacent pixel area PA. Therefore, the afterimage caused by the movement of the impurities is prevented. In addition, the barrier B reduces the force applied to the impurities by reducing the magnitude of the electric field at the boundary between the pixel electrodes 170, and the impurities do not pass through the boundary of the pixel electrodes 170. Afterimage is prevented.

Meanwhile, the barrier B is spaced apart from one of the array substrate 100 and the color filter substrate 200. In an embodiment of the present invention, the barrier B is formed on the color filter substrate 200 and spaced apart from the array substrate 100. When the barrier B is in contact with the top surface of the array substrate 100 and the color filter substrate 200, the barrier B is spaced apart from the array substrate 100 by the color filter substrate 200 at regular intervals. . As such, when the barrier B performs the same function as the spacer S, the compressibility between the array substrate 100 and the color filter substrate 200 is reduced. Therefore, the barrier B is provided to be spaced apart from any one of the array substrate 100 and the color filter substrate 200 in order to prevent the compressibility from being lowered.

For example, the height H1 of the spacer S may be greater than the height H2 of the barrier B to prevent the barrier B from functioning as the spacer S.

3A is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the cutting line II-II ′ of FIG. 3A. Detailed description of components identical to those illustrated in FIGS. 2A and 2B among the components illustrated in FIGS. 3A and 3B will be omitted.

3A and 3B, the liquid crystal display 720 according to another exemplary embodiment of the present invention includes an array substrate 300, a color filter substrate 400, a spacer S, and a barrier B. The liquid crystal display device 720 further includes a liquid crystal layer 50 interposed between the array substrate 300 and the color filter substrate 400 to control light transmittance.

The array substrate 300 includes a first base substrate 310 and pixels formed on the first base substrate 310. 3A and 3B do not show all the pixels but only one pixel.

A pixel area PA is formed on the array substrate 300, and the pixel is formed on the pixel electrode 170 corresponding to the pixel area PA and the first and the first base substrates 310. It includes two gate lines GL1 and GL2, a data line DL, first and second thin film transistors T1 and T2, a storage line SL, and a storage electrode SE. Not all pixel zeros PA are shown, only one pixel area PA is shown. However, the pixel areas PA have the same structure.

The first and second gate lines GL1 and GL2 extend in the first direction D1 and are spaced apart from each other at predetermined intervals. The second gate line GL1 extends in the first direction D1 adjacent to the pixel area PA. A first gate signal is applied to the first gate line GL1 during an initial H / 2 time of 1H time during which a row of pixels are driven, and a second gate signal is applied to the second gate line GL2 during a later H / 2 time. The gate signal is applied. The first and second gate signals maintain a gate on voltage for the initial H / 2 time and the later H / 2 time, respectively, and maintain a gate off voltage for the remaining time.

The data line DL extends in a second direction D2 orthogonal to the first direction D1 and is provided on a different layer from the first and second gate lines GL1 and GL2 to insulate each other. Intersect like that. A high pixel voltage is applied to the data line DL during the initial H / 2 time, and a low pixel voltage lower than the high pixel voltage is applied to the data line DL during the later H / 2 time.

The pixel electrode 370 includes a first pixel electrode 371 to which the high pixel voltage is applied during the initial H / 2 time and a second pixel electrode 372 to which the low pixel voltage is applied during the later H / 2 time. Is done.

The first thin film transistor T1 is electrically connected to the first gate line GL1 and the data line DL. In detail, the first thin film transistor T1 may include a first gate electrode 321 connected to the first gate line GL1, a first semiconductor pattern 340 formed on the first gate electrode 321, The first semiconductor pattern 340 includes a first source electrode 351 connected to the data line DL and a first drain electrode 352 connected to the first pixel electrode 371. Accordingly, the first thin film transistor T1 applies the high pixel voltage to the first pixel electrode 371 in response to the first gate signal during the initial H / 2 time.

The second thin film transistor T2 is electrically connected to the second gate line GL2 and the data line DL. In detail, the second thin film transistor T2 includes a second gate electrode 322 connected to the second gate line GL2, a second semiconductor pattern formed on the second gate electrode 322, and the second The semiconductor pattern includes a second source electrode 353 connected to the data line DL and a second drain electrode 354 connected to the second pixel electrode 372. Accordingly, the second thin film transistor T2 applies the low pixel voltage to the second pixel electrode 372 in response to the second gate signal during the later H / 2 time.

The pixel electrode 370 has a W shape lying in the second direction D2. Since the pixel electrode 370 extends in the second direction and is partially removed along the long side of the pixel electrode 370 that is bent in a W shape, a first opening 373 is formed in the pixel electrode 370. do. In particular, the first opening 373 is formed at a 1/2 position of two long sides parallel to each other.

In addition, the first opening 373 serves to electrically separate the first pixel electrode 371 and the second pixel electrode 372. The first pixel electrode 371 is bent in a third direction D3 opposite to the first direction D1 to have a V shape. The second pixel electrode 372 is defined as the remaining portion of the pixel electrode 370 except for the first pixel electrode 371. The second pixel electrode 372 is electrically separated from the first pixel electrode 371 by the second opening 253. For example, the first pixel electrode 371 has an area smaller than that of the second pixel electrode 372.

The storage line SL extends in the first direction D1 and is positioned between the first and second gate lines GL1 and GL2. The storage electrode SE extends in a rectangular shape from the storage line SL. The storage line SL receives a common voltage from the outside and applies the common voltage to the storage electrode SE. The storage electrode SE is disposed between the gate insulating layer 331 and the passivation layer 361 to face the pixel electrode 370. The storage electrode SE and the storage line SL are formed from the same layer as the first and second gate lines GL1 and GL2 but are electrically insulated from each other because different signals are applied thereto.

The array substrate 300 further includes an organic insulating layer 362 formed on the passivation layer 361, and the organic insulating layer 362 is removed from a region where the storage electrode SE is formed. In addition, a portion of the passivation layer 361 and the organic insulating layer 362 is removed to expose the first and second drain electrodes 352 and 354 of the first and second thin film transistors T1 and T2, respectively. First and second contact holes CH1 and CH2 are formed. The first pixel electrode 371 is electrically connected to the drain electrode 352 of the first thin film transistor T1 through the first contact hole CH1. The second pixel electrode 372 is electrically connected to the second drain electrode 354 of the second thin film transistor T2 through the second contact hole CH2.

The color filter substrate 400 may include a second base substrate 420, a black matrix 420 formed on the second base substrate 420, a first color filter layer 431, a second color filter layer 432, and a common substrate. Electrode 440. A first color filter layer 431 formed of any one of red, green, and blue color pixels is provided on the first base substrate 110, and each of the red, green, and blue color pixels corresponds one-to-one to the pixel electrode 370. Is formed. The black matrix 420 is interposed between the red, green, and blue color pixels to block light from leaking between the pixel areas PA. In the present embodiment, the black matrix 420 is formed to correspond to the region in which the second gate line GL2 and the first and second thin film transistors T1 and T2 are formed. In addition, the black matrix 420 has a W shape along the long side of the pixel electrode 370. As a result, the data line DL is not provided in an area where the black matrix 420 is formed.

A plurality of second openings 441 are formed in the common electrode 440 to expose the first color filter layer 431. As shown in FIG. 3A, the second opening 441 is positioned between the plurality of first openings 373 formed in the pixel electrode 370. Therefore, in the pixel area PA, a plurality of domains in which liquid crystal molecules interposed between the pixel electrode 370 and the common electrode 440 are aligned in different directions are defined.

The spacer S is interposed between the array substrate 300 and the color filter substrate 400 to space the array substrate 100 and the color filter substrate 200. The spacer S is provided between the array substrate 100 and the color filter substrate 200 corresponding to a region where the storage electrode SE is formed so as not to reduce the aperture ratio of the pixel area PA.

The second color filter layer 432 is formed between the spacer S and the array substrate 100, and is formed of at least one of the red, green, and blue color pixels. In the present embodiment, the second color filter layer 432 has a two-layer structure consisting of two of the red, green, and blue color pixels. The second color filter layer 432 may be simultaneously formed in the same process as the first color filter layer 431.

The barrier B is formed along a boundary of the pixel electrode 370 to block impurities from moving between the pixel areas PA. The region where the barrier B is formed is in the region where the black matrix 420 is formed so as not to reduce the aperture ratio of the pixel region PA. In this embodiment, the barrier B has an opening part partially removed.

Meanwhile, in the embodiment of the present invention, the spacer S and the barrier B are formed on the color filter substrate 400, and the second color filter layer 432 is formed of the spacer S and the first agent. It is provided between two color filter layers 432. Therefore, even when the spacer S and the barrier B are formed at the same height, the area where the spacer S is formed by the second color filter layer 432 provided under the spacer S and the barrier ( Since the step B occurs in the region where B is formed, the barrier B is spaced apart from the array substrate 300. Therefore, the compressibility between the array substrate 300 and the color filter substrate 400 is prevented from being lowered.

4A is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along the cutting line III-III ′ of FIG. 4A. Of the components shown in FIGS. 4A and 4B, the same components as those shown in FIGS. 2A and 2B are denoted by the same reference numerals, and detailed description thereof will be omitted.

4A and 4B, the liquid crystal display 730 according to the present invention includes an array substrate 100, a color filter substrate 200, a spacer S, and a barrier B. The liquid crystal display 730 further includes a liquid crystal layer 50 interposed between the array substrate 100 and the color filter substrate 200 to control light transmittance.

The array substrate 100 includes a first base substrate 110 and pixel regions PA formed on the first base substrate 110. In the drawing of the present invention, not all the pixel areas PA are shown, only two pixel areas PA are shown. However, the pixel areas PA have the same structure.

The array substrate 100 includes a first base substrate 110, gate lines GL, data lines DL, a storage line SL, first and second storage electrodes SE1 and SE2, and a passivation layer ( 161, an organic insulating layer 162, pixel electrodes 170, and thin film transistors T. In this embodiment, since the array substrate 100 is the same as the array substrate 100 shown in FIG. 2A, a duplicate description thereof will be omitted.

The pixel electrode 170 is formed on the organic insulating layer 162 corresponding to the pixel areas PA. The pixel electrodes 170 are patterned to partition each of the pixel areas PA into a plurality of domains in which liquid crystal molecules of the liquid crystal layer 50 are differently aligned. That is, the pixel electrodes 170 have a first opening 171 formed by removing portions of the pixel electrodes 170, respectively. The first opening 171 is formed to be inclined at a predetermined angle with respect to an imaginary line crossing the centers of the pixel areas PA in the second direction D2, and is mirror-symmetrical with respect to the imaginary line. It has a shape. The pixel electrodes 170 are partitioned into a plurality of domains by the first opening 171. In addition, the first opening 171 may be further partially removed along the imaginary line as shown in FIG. 4A.

The color filter substrate 200 is coupled to face the array substrate 100, and includes a second base substrate 210, a black matrix 220, a color filter layer 230, and a common electrode 240. Since the color filter substrate 200 is the same as the color filter substrate 200 illustrated in FIG. 2A, duplicate description thereof will be omitted.

The common electrode 240 has a second opening 241 partially removed to form the domains. In plan view, the second openings 241 are formed between the first openings 171 and extend in parallel to sides of the pixel electrodes 170 extending in the second direction D2. Can be. As described above, in the liquid crystal display 710, the pixel areas PA are divided into a plurality of domains, thereby improving visibility.

In the present exemplary embodiment, the contact hole CH electrically connecting the pixel electrodes 170 to the thin film transistors T is formed on the second storage electrode SE1.

As shown in FIG. 2A, the spacer S is provided between the array substrate 100 and the color filter substrate 200 corresponding to a region where the first storage electrode SE1 is formed.

In the present embodiment, the barrier B is formed along a boundary between the pixel electrodes 170 and includes protrusions 11a and 11b spaced apart from each other, and the protrusions 11a and 11b are alternately arranged. do. In more detail, the protrusions 11a and 11b are formed of the first protrusions 11a provided adjacent to the first pixel area PA1 of the pixel areas PA and the first of the pixel areas PA. The second protrusions 11b may be provided adjacent to the second pixel area PA2 adjacent to the pixel area PA1. The first and second protrusions 11a and 11b are alternately disposed. That is, the second protrusions 11b are positioned in the spaced apart area between the first protrusions 11a, and the first protrusions 11a are disposed in the spaced apart area between the second protrusions 11b. Located. Therefore, impurities existing between the array substrate 100 and the color filter substrate 200 are limited to movement by the first and second protrusions 11a and 11b to the adjacent pixel regions PA. I can't move.

A method of manufacturing the liquid crystal display 710 illustrated in FIG. 2A will be described with reference to FIGS. 2A and 2B.

A method of manufacturing the liquid crystal display 710 according to the present invention is as follows. The substrate 100 in which the pixel areas PA are defined is formed, and the color filter substrate 200 is formed to face the array substrate 100. The same as the spacer (S) and the spacer (S) for separating the array substrate 100 and the color filter substrate 200 on any one of the array substrate 100 and the color filter substrate 200 A barrier B may be formed of a material and disposed between the pixel areas PA to block impurities from moving between the pixel areas PA. The barrier B is formed to be spaced apart from any one of the array substrate 100 and the color filter substrate 200.

Specifically, the method of manufacturing the array substrate 100 is as follows.

Referring to FIG. 2B, the gate lines GL, the gate electrodes 121, and the first storage electrode SE1 deposit a gate conductive layer on the first base substrate 110, and form the gate conductive layer. It is formed by patterning. The process of patterning the gate conductive layer is performed by an exposure, development, and etching process using a photo mask. The gate conductive film is made of any one selected from aluminum, silver, copper, molybdenum, and chromium. The gate insulating layer 131 and the semiconductor film covering the gate lines GL, the gate electrodes 121, and the first storage electrode SE1 are sequentially deposited on the entire surface of the first base substrate 110. .

The gate insulating layer 131 may be formed of an inorganic layer, for example, silicon nitride. The semiconductor film is deposited on the entire surface of the first base substrate 110 using plasma chemical vapor deposition. The semiconductor film is composed of an active film made of amorphous silicon and a two-layer film of an ohmic contact film doped with impurity ions thereon. The semiconductor patterns are patterned to form the semiconductor patterns 140.

The data lines DL, the source electrodes 151, the drain electrodes 152, and the second storage electrode SE2 are formed by depositing a data conductive layer and patterning the data conductive layer. The data conductive film is made of the same metal material as the gate conductive film.

The passivation layer 161 may cover the data lines DL, the source electrodes 151, the drain electrodes 152, and the second storage electrode SE2 on the front surface of the first base substrate 110. And the organic insulating film 162 is continuously deposited. The protective film 161 is made of the same material as the gate insulating film, and the organic insulating film 162 is made of acrylic resin. A portion of the passivation layer 161 and the organic insulating layer 162 may be removed in a contact process using a photo mask to form contact holes CH exposing the drain electrode 152. In addition, the organic insulating layer 162 is etched in a region where the second storage electrode SE2 is formed to expose a portion of the passivation layer 161.

The pixel electrodes 170 are formed by depositing a transparent conductive layer and patterning the transparent conductive layer. The gate conductive layer is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The process of manufacturing the color filter substrate 200 is as follows.

Referring to FIG. 2B, the black matrix 220 is formed by applying a photoresist or a metal material on the second base substrate 210 and performing exposure, development, and etching processes using a photo mask. The color filter layer 230 is formed by coating and patterning a photoresist containing a pigment on the entire surface of the second base substrate 210. The common electrode 240 is formed by coating a transparent conductive film on the black matrix 220 and the color filter layer 230 and then patterning the transparent conductive film. The transparent conductive film is formed by depositing ITO and IZO.

5 is a cross-sectional view illustrating a process of manufacturing a spacer and a barrier according to an embodiment of the present invention. Of the components illustrated in FIG. 5, the same components as those illustrated in FIG. 2B are denoted by the same reference numerals, and detailed description thereof will be omitted.

Although an embodiment of the present invention describes a process of simultaneously producing a spacer (S) and a barrier (B) in the same process using a photoresist, this is merely to illustrate the invention and the invention is limited thereto. It is not. In addition, although the spacer S and the barrier B may be formed on either of the array substrate 100 and the color filter substrate 200, an example formed on the color filter substrate 200 will be described.

Referring to FIG. 5, the photoresist PR is uniformly coated on the color filter substrate 200 using a spray unit. The coated photoresist PR is exposed and developed to form the spacers S and the barriers B. In this case, the height H1 of the spacer S is greater than the height H2 of the barrier B so that the barrier B is formed to be spaced apart from the array substrate 100.

To this end, the exposure process of the photoresist PR may be performed using a slit mask or a halftone mask. The exposure amount of the photoresist PR may be adjusted using the slit mask or the halftone mask, and the heights H1 and H2 of the spacer S and the barrier B may be adjusted according to the exposure amount. Because. In the present embodiment, an example in which the spacer S and the barrier B are formed using the slit mask is described.

A photo mask 60 is provided on the color filter substrate 200 to which the photoresist PR is applied. The photo mask 60 includes a quartz substrate 61, a light shielding pattern 62a and a slit mask 62b formed on the quartz substrate 61. The quartz substrate 61 transmits light from the outside, and the light blocking pattern 62a blocks the light, and is formed of, for example, chromium as a light blocking material. The light blocking pattern 62a is formed on the quartz substrate 61 corresponding to a region where the spacer S is formed. The slit mask 62b is formed on the quartz substrate 61 to correspond to a region where the barrier B is formed, and the exposure amount may be adjusted by adjusting the slit interval of the slit mask 62b. By adjusting the exposure amount, the height H2 of the barrier may be smaller than the height H1 of the spacer S.

In the region where the light shielding pattern 62a and the slit mask 62b are not formed, the light is transmitted to expose the photoresist PR, and the light is blocked in the region where the light shielding pattern 62a is formed. Photoresist PR is not exposed. In addition, only a part of the photoresist PR is exposed in a region where the slit mask 62b is formed.

When the photoresist PR is exposed and subjected to a developing process, the spacer S and the barrier B are formed as shown in FIG. 5.

As described above, since the spacer S and the barrier B may be simultaneously formed in the same process, the process may be simplified. In addition, the height H1 of the spacer S is formed to be larger than the height H2 of the barrier B by using the slit mask 60 so that the barrier B is spaced apart from the array substrate 100. do.

As described above, according to the display device and a method of manufacturing the same, impurities present between the first substrate and the second substrate may be prevented from moving between adjacent pixel regions by the barrier. Therefore, afterimages can be prevented from occurring in the display device, thereby improving display quality.

In addition, the barrier may be formed to be spaced apart from any one of the first substrate and the second substrate to prevent the compressibility between the first substrate and the second substrate from being impaired.

In addition, the number of processes can be reduced by simultaneously forming the barrier and the spacer in the same process.

Claims (13)

A first substrate on which pixel regions are formed; A second substrate coupled to face the first substrate; A spacer interposed between the first substrate and the second substrate to space the first substrate and the second substrate; And And a barrier formed of the same material as the spacer and interposed between the pixel areas to block impurities from moving between the pixel areas. The method of claim 1, And the barrier is formed on one of the first and second substrates and is spaced apart from the other substrate. The method of claim 2, wherein the first substrate, Gate lines provided adjacent to each of the pixel regions and extending in one direction; Data lines crossing the gate lines to be insulated from each other; And And a plurality of pixel electrodes formed to correspond to the pixel areas. The method of claim 3, wherein the second substrate, A first color filter layer formed corresponding to the pixel electrodes; And And a second color filter layer formed between the spacer and the second substrate. The method of claim 4, wherein The first color filter layer is made of any one of red, green, and blue, And the second color filter layer is formed of at least one of red, green, and blue. The method of claim 3, wherein And the barrier has a closed loop shape formed along a boundary between the pixel electrodes. The method of claim 3, wherein And the barrier is formed along a boundary between the pixel electrodes and partially opened. The method of claim 3, wherein The barrier is formed along a boundary between the pixel electrodes and includes protrusions spaced apart from each other, And the spaced protrusions are alternately arranged. Forming a first substrate having pixel regions formed thereon; Forming a second substrate opposed to the first substrate; Forming a spacer spaced apart from the first substrate and the second substrate on one of the first substrate and the second substrate; And And forming a barrier formed of the same material as the spacer and interposed between the pixel areas to prevent impurities from moving between the pixel areas. The method of claim 9, And the barrier is formed on one of the first and second substrates and is spaced apart from the other substrate. The method of claim 10, The spacer is a column spacer, And the barrier is formed at the same time as the spacer. The method of claim 11, wherein the forming of the spacer and the barrier comprises: Applying a photoresist on any one of the first and second substrates; And Exposing the coated photoresist using a slit mask or a halftone mask. The method of claim 12, And forming a height of the spacer larger than a height of the barrier.

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