KR20080050032A - Display appartus and method for driving the same - Google Patents

Abstract

A display apparatus and a driving method thereof are provided to enhance response speed of the display apparatus by increasing frame and clock frequencies when motion picture is inputted. A display apparatus includes a signal controller(100), drivers(200,300), and a display panel(500). The signal controller receives first data and main clock signals of a current frame from outside, converts frequencies of the first data and main clock signals into second data and data clock signals, based on the image type of the first data signal, and outputs the converted signals. The drivers output driving signals in response to the second data and data clock signals from the signal controller. The display panel displays images corresponding to the current frame in response to the driving signals from the drivers.

Description

 DISPLAY APPARTUS AND METHOD FOR DRIVING THE SAME}

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating a signal controller shown in FIG. 1.

FIG. 3 is a block diagram illustrating an image discriminating unit illustrated in FIG. 2.

4 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: signal control unit 110: image determination unit

112: memory 114: comparison operator

116: image pattern discriminator 120: frequency converter

130: signal processor 140: control signal generator

200: data driver 300: scan driver

500: display panel

The present invention relates to a display device and a driving method thereof, and more particularly, to a display device capable of improving a response speed.

As a flat panel display, a liquid crystal display (LCD) is widely used. The liquid crystal display device includes two display substrates and a liquid crystal layer interposed between these display substrates. This liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display substrates, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Such a liquid crystal display includes a display panel including a pixel including a switching element, a display signal line, a gate driver to turn on / off a switching element of a pixel by sending a gate signal to a gate line among the display signal lines, and a data line among a display signal line. And a data driver for applying data voltages and a signal controller for controlling the data voltages.

In this case, the signal controller generates a control signal necessary to control the gate driver and the data driver based on a control signal, a clock signal, and an image signal from the outside, and changes the clock signal and the image signal according to the operation of the display panel.

The frequency of the video signal is 60 Hz per second and is displayed on the screen 60 times per second, and the frequency of the clock signal is very high frequency, for example, 65 MHz in the case of an XGA display device (1024 x 768 x 3).

On the other hand, the video signal and the clock signal frequency are equally applied to the case of displaying a still image or a video. In the case of moving images requiring higher response speed, it is very inefficient to use the same frequency of the video signal as the still image.

Accordingly, an object of the present invention is to provide a display device and a driving method thereof which can improve a response speed by differentially applying a signal frequency according to an image type.

According to an aspect of the present invention, a display device includes a signal controller, a driver, and a display panel. The signal controller receives a first data signal and a main clock signal of a current frame input from an external device, and adjusts a frame frequency of the first data signal and a frequency of the main clock signal based on an image type of the first data signal. They are varied and converted into a second data signal and a data clock signal, respectively, and output. The driving unit receives the second data signal and the data clock signal and outputs a driving signal in response to the second data signal and the data clock signal. The display panel receives the driving signal and displays an image of the current frame in response to the driving signal.

According to another aspect of the present invention, there is provided a method of driving a display device, which receives a first data signal and a main clock signal of a current frame. Subsequently, the first data signal is compared for each frame during the reference time to determine whether it is the same. In this case, when the first data signal of each frame is continuously input at the same value for more than the reference time, the first data signal and the main clock signal are converted into a second data signal having a first frequency and a data clock signal. Convert and output On the other hand, when the first data signal of each frame is input with a value that is not the same for more than the reference time, the first data signal and the main clock signal have a second data signal and a data clock having a second frequency. The signal is converted into a signal and output to the driver. Subsequently, in response to the second data signal and the data clock signal, a driving signal from the driving unit is output to the display panel. And receiving the driving signal and displaying a predetermined image corresponding to the driving signal.

According to the display device and the method of driving the display device according to the present invention, the frame frequency of the second data DATA2 and the data clock frequency HCLK are differentially applied according to the image type of the image signal input from the outside. That is, when a video signal such as a video is input, the frame frequency and the data clock frequency are increased. Therefore, the response speed of the display device can be improved.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings. In understanding the drawings, it should be noted that like parts are intended to be represented by the same reference numerals as much as possible. In addition, in the following description, numerous specific details, such as specific processing flows, are described to provide a more general understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. Incidentally, detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display apparatus includes a signal controller 100, drivers 200 and 300, a driving voltage generator 400, and a display panel 500 to display an image having improved display quality.

The signal controller 100 receives an image signal (hereinafter, referred to as a first data signal; DATA1) which is a digital signal from an external graphic controller (not shown). The signal controller 100 controls the video signal according to timing to provide an image data signal (hereinafter referred to as a second data signal; DATA2) and a data control signal to the driver 200, and the driver 300 ) Provides a scan control signal and provides a voltage driving signal Pcon to the driving voltage generator 400.

The image signal provided from the graphic controller includes, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a first data signal DATA1, a main clock signal MCK, and a data enable signal DE. Etc.

The vertical synchronization signal Vsync indicates the start or end of each field. The horizontal synchronization signal Hsync indicates the start or end of a row line in the display panel 500. The main clock signal MCK is a signal for synchronizing the external data signal DATA1. The data enable signal DE defines an effective range of the external data signal DATA1 between the horizontal synchronization signal Hsync and the horizontal synchronization signal Hsync.

The first data signal DATA1 includes RGB image information for displaying an image. That is, the first data signal DATA1 includes a red data signal having red image data, a green data signal having green image data, and a blue data signal having blue image data.

In this case, the signal controller 100 converts the first data signal DATA1 as described above into a second data signal DATA2 that can be processed by another driving circuit provided in the display device, and outputs the converted data. Specifically, the output second data signal DATA2 is input to the data driver 200 described in detail below, and the data driver 200 receives the data driving signal in response to the second data signal DATA2. Output The data driving signal is finally applied to the display panel 500, and the display panel 500 displays a predetermined image corresponding to the data driving signal.

Meanwhile, the signal controller 100 included in the display device of the present invention changes and outputs the frame frequency of the first data signal DATA1 according to the image information of the first data signal DATA1, that is, the image type. . That is, when the image type included in the first data signal DATA1 is a still image, the signal controller 100 outputs a second data signal DATA2 having a frame frequency of the existing frame frequency, for example, 60 Hz. On the other hand, when the image type included in the first data signal DATA1 is a moving picture, the signal controller 100 sets the first data signal DATA1 to a second data signal having a frame frequency of approximately 70 Hz to 80 Hz greater than 60 Hz. Convert to (DATA2) and print.

As described above, the signal controller 100 included in the display device of the present invention outputs the second data signal DATA2 by varying the frame frequency according to the image characteristic of the first data signal DATA1 input from the outside. The response speed characteristics of the display device can be improved without structural changes of the panel or other circuits. A more detailed description thereof will be described below.

Subsequently, the drivers 200 and 300 include a data driver 200 and a scan driver 300. The data driver 200 receives the second data signal DATA2 and the data clock signal HCLK from the signal controller 100, and transmits the second data signal DATA2 to the data clock signal HCLK and the data clock signal HCLK. Data control signal (STH, LOAD, DOT, etc.) The data control signal is a data start signal (STH) indicating the start of the second data signal (DATA2) and the data drive after the transmission of the image data signal (DATA2) And a data load signal Load for notifying the output of the signal, and a data synchronization signal DOT for synchronizing the image data signal DATA2.

The data driver 200 receives the image data signal DATA2, which is a digital signal, as a serial and temporarily stores the image data signal DATA2 in line units. The data stored in the line unit is converted into an analog signal according to a reference color data value in order to display an image having an actual desired color, and the data lines D1, D2, ..., D2m of the display panel 500. Is applied line by line.

The scan driver 300 receives the scan control signal generated by the signal controller 100 and is controlled by the scan control signal to scan lines G1, G2, ..., of the display panel 500. G2n) is sequentially applied to the scan drive signals Von / Voff. (Where n is a natural number.) The scan control signal is a scan start signal indicating the start of the output of the scan drive signals Von / Voff. STV) and a scan clock GCK for synchronizing the scan driving signals Von / Voff. In this case, the scan driver 300 receives an on / off reference voltage Von / Voff that provides a reference voltage of the scan driving signal Von / Voff from the driving voltage generator 400.

The driving voltage generator 400 is driven by receiving power Vcc from the outside, and is controlled by receiving the voltage driving signal Pcon from the signal controller 100, and the scan driver 300 and the display panel The driving voltage required to drive 500 is output.

For example, the on / off reference voltage Von / Voff applied to the scan driver 300 and a common voltage Vcom applied to a common electrode (not shown) formed on the display panel 500 may be applied to the driving voltage. ) And a storage reference voltage Vst applied to the reference voltage line formed on the display panel 500.

The display panel 500 includes an array substrate (not shown) provided with a plurality of switching elements, a color filter substrate (not shown) disposed to face the array substrate and having a plurality of color filters, and the array substrate and color. It consists of a liquid crystal layer interposed between filter substrates. The switching elements are thin film transistors.

In the array substrate, a plurality of data lines D1, D2,..., D2m are extended in a first direction D1 and arranged in parallel in a second direction, and a plurality of scan lines G1, G2,. , Gn are arranged in parallel along the second direction D2 perpendicular to the first direction D2. The data lines D1, D2, ..., D2m and the scan lines G1, G2, ..., Gn cross each other to define pixel regions, and a unit pixel is formed in each of the pixel regions. .

Each unit pixel includes a thin film transistor, a liquid crystal capacitor Clc, and a storage capacitor Cst, which are switching elements. Each thin film transistor includes a gate electrode, a source electrode and a drain electrode. The gate electrode is connected to the scan lines G1, G2, ..., Gn, the source electrode is connected to the data lines D1, D2, ..., D2m, and the drain electrode is the liquid crystal. It is connected to the pixel electrode which is the first electrode of the capacitor Clc.

The color filter substrate includes color filters including color pixels corresponding to each unit pixel, and a common electrode applied with the common voltage Vcom and a second electrode of the liquid crystal capacitor Clc.

The liquid crystal capacitor Clc is defined by the pixel electrode connected to the drain electrode and the common electrode applying the common voltage Vcom. In addition, the storage capacitor Cst is defined by a reference voltage line applying the storage reference voltage Vst and the pixel electrode.

In this case, the data driving signal generated by the data driver 200 and the scan driving signal generated by the scan driver 300 are the data lines D1, D2,..., D2m and the scan lines G1, G2, ..., Gn), an electric field is formed between the pixel electrode and the common electrode, and the electric field changes the transmittance of the liquid crystal layer interposed between the pixel electrode and the common electrode to display an image.

Hereinafter, the signal controller 100 will be described in more detail with reference to the accompanying drawings.

2 is a block diagram illustrating the signal controller 100 shown in FIG. 1.

Referring to FIG. 2, the signal controller 100 includes an image discriminator 110, a frequency converter 120, a signal processor 130, and a control signal generator 140.

The image discriminating unit 110 receives the first data signal DATA1 of the current frame input from the outside and determines the image type of the first data signal DATA1. Here, the image type of the first data signal is classified into a still image and a moving image, and the image determining unit 110 determines whether the image type of the first data signal input in the current frame is a still image or a moving image.

Hereinafter, the image discrimination unit 110 will be described in more detail with reference to the accompanying drawings.

3 is a block diagram illustrating the image discriminating unit 110 illustrated in FIG. 2.

Referring to FIG. 3, the image discrimination unit 110 includes a memory 112, a comparison operation unit 114, and the same pattern discriminator 116.

The memory 112 stores a data signal (hereinafter referred to as a 'third data signal') corresponding to an image signal of a previous frame input before the current frame input from the outside. In this case, the third data signal DATA1-1 is stored in frame units.

The comparison operator 114 receives and compares the third data signal DATA1-1 of the previous frame stored in the memory with the first data signal DATA1 of the current frame and compares the first data signal and the third data signal different from each other. If the value has a value, the image pattern signal SAME is output.

The same pattern discriminator 116 receives an image pattern signal SAME from the comparator 114, and when the image pattern signal SAME is continuously input to each other for a predetermined reference time T, Output the frequency selection signal SEL. The frequency selection signal includes a first selection signal sel1 and a second selection signal sel2. In this case, the reference time T is preferably set to 5 seconds or less, and the frequency selection signal SEL is preferably output for one frame. More preferably, the frequency selection signal SEL is output in units of 60 frames.

When the image pattern signal SAME is continuously input from the comparison operator 114 for the reference time T, the image pattern discriminator 116 determines the first data signal DATA1 of the current frame as a still image. The first selection signal sel1 corresponding to the still image is output.

On the other hand, if the same pattern signal SAME is not continuously input during the reference time, the first data signal DATA1 of the current frame is determined as a video and the frame corresponding to the video larger than the frame frequency corresponding to the still image. The second selection signal sel2 corresponding to the frequency (for example, 70 Hz or 80 Hz) is output.

In summary, the image discrimination unit 110 compares five frames, for example, for 5 seconds during the reference time. As a result of the comparison, when there is no change in the first data signal (R, G, B) that constitutes one frame, it is determined as a still image and outputs the first selection signal sel1; Output the signal sel2.

Referring back to FIG. 2, the frequency converter 120 receives the first data signal DATA1 and the main clock signal MCLK, and responds to the frequency selection signal SEL in response to the frequency selection signal SEL. The frame frequency of DATA1 and the frequency of the main clock signal MCLK are converted. In detail, the frequency converter 120 adjusts the frame frequency of the first data signal DATA1 and the frequency of the main clock signal MCLK in response to the first selection signal sel1 from the image discriminator 110. The frequency is adjusted to 60 Hz, and the frame frequency of the first data signal DATA1 and the frequency of the main clock signal MCLK are adjusted to a frequency of 70 Hz to 80 Hz in response to the second selection signal sel2.

The signal processor 130 receives a frequency-converted first data signal and a main clock signal, converts the second data signal DATA2 and the data clock signal HCLK, respectively, and outputs the converted data. The output second data signal DATA2 and data clock signal HCLK are output to the data driver 200 shown in FIG. 1.

The control signal generator 140 receives and controls the vertical synchronous signal Vsync, the horizontal synchronous signal Hsync, and the data enable signal DE to control the data start signal STH and the data load signal Load. ), A data synchronizing signal DOT, a scan start signal STV, a scan clock GCK, and a voltage driving signal Pcon are outputted. In this case, the data start signal STH, the data load signal Load and the data synchronization signal DOT are applied to the data driver 200, and the scan start signal STV and the scan clock GCK are scanned. The driving unit 300 is applied, and the voltage driving signal Pcon is applied to the driving voltage generation unit 400.

4 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, in the method of driving a display device, first, the first data signal DATA1 is applied to the signal controller 100 of the display device from an external graphic controller (not shown). In addition, the signal controller 100 receives a main clock signal MCLK and other control signals Vsync, Hsync, DE, etc. from the graphic controller (S410).

The first data signal DATA1 applied to the signal controller 100 is compared for equality for each frame (S420). That is, the first data signal DATA1 currently applied and the third data signal DATA1-1 previously applied are compared for each frame to confirm whether they are identical.

In this case, since the external data signal DATA1 includes a red data signal, a green data signal, and a blue data signal, the checking of the equality compares each of the red data signal, the green data signal, and the blue data signal for each frame. It is preferable to make.

In operation S430, it is checked whether the first data signal DATA1 of each frame is continuously applied to the signal controller 100 for the same time or longer. Here, the reference time is preferably set to 5 seconds or less. Specifically, when the first data signal DATA1 of each frame is continuously input at the same value for more than the reference time T, the first data signal and the main clock signal are inputted at a first frequency (for example, 60 Hz). Is converted into the second data signal DATA2 and the data clock signal HCLK and output to the data driver 200 (S440a).

On the other hand, when the first data signal DATA1 of each frame is input with a value that is not the same for more than the reference time T, the first data signal DATA1 and the main clock signal MCLK may be inputted. A second data signal having a second frequency (70 Hz to 80 Hz) and a data clock signal are converted and output to the data driver 200 (S440b).

Thereafter, a driving signal from the data driver 200 is output in response to the second data signal DATA2 and the data clock signal HCLK having the selected frequency, and the output driving signal is provided to the display panel 500. do.

The display panel displays a predetermined image corresponding to the driving signal in response to the input driving signal.

According to the display device and the method of driving the display device according to the present invention as described above, the frame frequency of the second data (DATA2) and the data clock frequency (HCLK) is differentially differentiated according to the image type of the image signal input from the outside. Apply to. That is, when a video signal such as a video is input, the frame frequency and the clock frequency are increased. Therefore, the response speed of the display device can be improved.

As described above, the optimum embodiment has been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (10)

The first data signal and the main clock signal of the current frame are received from the outside, and the frame frequency of the first data signal and the frequency of the main clock signal are varied based on the image type of the first data signal, respectively. A signal controller converting the signal and the data clock signal to output the signal; A driver which outputs a driving signal in response to the second data signal and the data clock signal from the signal controller; And And a display panel configured to display an image corresponding to the current frame in response to the driving signal from the driver. The method of claim 1, wherein the image type includes a still image and a video. And a frame frequency of the second data signal corresponding to the still image is lower than a frame frequency of the second data signal corresponding to the video. The display device of claim 2, wherein the frame frequency of the second data signal corresponding to the still image is 60 Hz. The method of claim 2, wherein the signal control unit, An image discriminating unit comparing the first data signal of the current frame with a third data signal of a previous frame and outputting a frequency selection signal corresponding to an image type of the first data signal according to a comparison result; A frequency converter configured to receive the first data signal and the main clock signal from an external source, and convert a frame frequency of the first data signal and a frequency of the main clock signal in response to the frequency selection signal; And And a signal processor configured to receive the frequency-converted first data signal and main clock signal, and convert the first data signal and the main clock signal into a second data signal and a data clock signal. The method of claim 3, wherein the image discriminating unit, A memory for storing a third data signal of the previous frame; A comparator which receives the first data signal of the current frame and the third data signal of the previous frame and compares the received data; And When the image pattern signal is continuously input from the comparator, the frequency selection signal corresponding to the still image is output, and when the image pattern signal is not continuously input during the reference time, And an image pattern discriminator for outputting a corresponding frequency selection signal.  The method of claim 4, wherein And the reference time is 5 seconds or less. A display device having a driving unit for generating a driving signal and a display panel for displaying a predetermined image in response to the driving signal, Receiving a first data signal and a main clock signal corresponding to one pixel; Determining whether the first data signal is input at the same value for a reference time; When the first data signal is continuously input at the same value during the reference time, the first data signal and the main clock signal are converted into a second data signal having a first frequency and a data clock signal, and output. When the first data signal is continuously input to a value that is not the same for a reference time, the first data signal and the main clock signal are converted into a second data signal having a second frequency and a data clock signal to the driving unit. Outputting; Outputting a driving signal from the driving unit to the display panel in response to a second data signal and a data clock signal; And And receiving the driving signal and displaying a predetermined image corresponding to the driving signal. The method of claim 7, wherein And the first frequency is lower than the second frequency. The method of claim 7, wherein And the first frequency is 60 Hz, and the second frequency is 70 Hz to 80 Hz. The method of claim 7, wherein And the reference time is 5 seconds or less.

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