KR20080049825A - 임베딩된 마스킹을 갖는 빠른 회전자와 그 방법 - Google Patents

임베딩된 마스킹을 갖는 빠른 회전자와 그 방법 Download PDF

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Publication number
KR20080049825A
KR20080049825A KR1020087009079A KR20087009079A KR20080049825A KR 20080049825 A KR20080049825 A KR 20080049825A KR 1020087009079 A KR1020087009079 A KR 1020087009079A KR 20087009079 A KR20087009079 A KR 20087009079A KR 20080049825 A KR20080049825 A KR 20080049825A
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KR
South Korea
Prior art keywords
rotor
input
decoder
shift
receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020087009079A
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English (en)
Korean (ko)
Inventor
링콘 알. 누네스
알베르트 엔. 데니쉬
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20080049825A publication Critical patent/KR20080049825A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/764—Masking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/017—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising using recirculating storage elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/768—Data position reversal, e.g. bit reversal, byte swapping

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Executing Machine-Instructions (AREA)
KR1020087009079A 2005-10-17 2006-10-04 임베딩된 마스킹을 갖는 빠른 회전자와 그 방법 Withdrawn KR20080049825A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/252,061 2005-10-17
US11/252,061 US20070088772A1 (en) 2005-10-17 2005-10-17 Fast rotator with embedded masking and method therefor

Publications (1)

Publication Number Publication Date
KR20080049825A true KR20080049825A (ko) 2008-06-04

Family

ID=37949361

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087009079A Withdrawn KR20080049825A (ko) 2005-10-17 2006-10-04 임베딩된 마스킹을 갖는 빠른 회전자와 그 방법

Country Status (4)

Country Link
US (1) US20070088772A1 (https=)
JP (1) JP2009512090A (https=)
KR (1) KR20080049825A (https=)
WO (1) WO2007047167A2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170005751A (ko) * 2015-07-06 2017-01-16 삼성전자주식회사 비트-마스크드 가변 정밀 바렐 시프터
GB2637295A (en) * 2024-01-10 2025-07-23 Imagination Tech Ltd Vector bitwise rotations

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1720171B1 (fr) * 2005-05-04 2009-01-28 St Microelectronics S.A. Dispositif de décalage en anneau
FR2914447B1 (fr) * 2007-03-28 2009-06-26 St Microelectronics Sa Dispositif electronique de decalage de donnees en particulier pour du codage/decodage avec un code ldpc
US8041755B2 (en) * 2007-06-08 2011-10-18 Apple Inc. Fast static rotator/shifter with non two's complemented decode and fast mask generation
JP5206603B2 (ja) * 2009-07-01 2013-06-12 富士通株式会社 シフト演算器
US8356145B2 (en) * 2010-01-15 2013-01-15 Qualcomm Incorporated Multi-stage multiplexing operation including combined selection and data alignment or data replication
US8768989B2 (en) * 2011-03-18 2014-07-01 Apple Inc. Funnel shifter implementation
US8972469B2 (en) 2011-06-30 2015-03-03 Apple Inc. Multi-mode combined rotator
US20130151820A1 (en) * 2011-12-09 2013-06-13 Advanced Micro Devices, Inc. Method and apparatus for rotating and shifting data during an execution pipeline cycle of a processor
US10289382B2 (en) 2012-12-20 2019-05-14 Wave Computing, Inc. Selectively combinable directional shifters
US9933996B2 (en) * 2012-12-20 2018-04-03 Wave Computing, Inc. Selectively combinable shifters
US9490971B2 (en) * 2012-12-28 2016-11-08 Intel Corporation Instruction for fast ZUC algorithm processing
US9419792B2 (en) * 2012-12-28 2016-08-16 Intel Corporation Instruction for accelerating SNOW 3G wireless security algorithm
US9904511B2 (en) * 2014-11-14 2018-02-27 Cavium, Inc. High performance shifter circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4139899A (en) * 1976-10-18 1979-02-13 Burroughs Corporation Shift network having a mask generator and a rotator
US4396994A (en) * 1980-12-31 1983-08-02 Bell Telephone Laboratories, Incorporated Data shifting and rotating apparatus
US4653019A (en) * 1984-04-19 1987-03-24 Concurrent Computer Corporation High speed barrel shifter
JPH02197919A (ja) * 1989-01-27 1990-08-06 Matsushita Electric Ind Co Ltd 異種サイズ対応ローテータとシフタ
US6116768A (en) * 1993-11-30 2000-09-12 Texas Instruments Incorporated Three input arithmetic logic unit with barrel rotator
US5961635A (en) * 1993-11-30 1999-10-05 Texas Instruments Incorporated Three input arithmetic logic unit with barrel rotator and mask generator
US5652718A (en) * 1995-05-26 1997-07-29 National Semiconductor Corporation Barrel shifter
US5729482A (en) * 1995-10-31 1998-03-17 Lsi Logic Corporation Microprocessor shifter using rotation and masking operations
US5844825A (en) * 1996-09-03 1998-12-01 Wang; Song-Tine Bidirectional shifter circuit
US5822231A (en) * 1996-10-31 1998-10-13 Samsung Electronics Co., Ltd. Ternary based shifter that supports multiple data types for shift functions
US6260055B1 (en) * 1997-10-15 2001-07-10 Kabushiki Kaisha Toshiba Data split parallel shifter and parallel adder/subtractor
US6098087A (en) * 1998-04-23 2000-08-01 Infineon Technologies North America Corp. Method and apparatus for performing shift operations on packed data
US6393446B1 (en) * 1999-06-30 2002-05-21 International Business Machines Corporation 32-bit and 64-bit dual mode rotator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170005751A (ko) * 2015-07-06 2017-01-16 삼성전자주식회사 비트-마스크드 가변 정밀 바렐 시프터
GB2637295A (en) * 2024-01-10 2025-07-23 Imagination Tech Ltd Vector bitwise rotations

Also Published As

Publication number Publication date
WO2007047167A2 (en) 2007-04-26
US20070088772A1 (en) 2007-04-19
JP2009512090A (ja) 2009-03-19
WO2007047167A3 (en) 2008-01-17

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Date Code Title Description
PA0105 International application

Patent event date: 20080416

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid