KR20080048609A - Voltage generator and method using the same - Google Patents

Abstract

A voltage generator and a method for generating voltages are provided to prevent the erroneous operation of a charge pump by ensuring one period of the pumping of the charge pump. A voltage generator includes a charge pump(14), a voltage detector(11), a latch unit(12), and an oscillator(13). The charge pump receives a first oscillation signal, performs charge pumping during the activation of the first oscillation signal, and adjusts the levels of inner voltages. The voltage detector detects the levels of inner voltages, activates a first detection signal when the inner voltage is deviated from a reference level, and outputs the activated first detection signal. The latch unit outputs a second detection signal by buffering the first detection signal when a second oscillation signal is inactive based on the first oscillation signal and outputs the first detection signal as the second detection signal when the second oscillation signal is active. The oscillator, which is driven based on the second detection signal, outputs the first oscillation signal.

Description

Voltage generator and method using the same}

1 is a block diagram illustrating a voltage generator according to an embodiment of the present invention.

2 is a circuit diagram illustrating a latch unit included in the voltage generator of FIG. 1 according to an exemplary embodiment of the present invention.

3 is a circuit diagram illustrating a latch unit included in the voltage generator of FIG. 1 according to another exemplary embodiment of the present disclosure.

4 is a circuit diagram illustrating a clock inverter included in the latch unit of FIG. 3 according to an exemplary embodiment of the present invention.

5 is a block diagram illustrating a voltage generator according to an embodiment of the present invention.

6 is a circuit diagram illustrating a pulse width expander included in the voltage generator of FIG. 5 according to an embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a latch unit included in the voltage generator of FIG. 5, according to an exemplary embodiment.

FIG. 8 is a circuit diagram illustrating a latch unit included in the voltage generator of FIG. 5, according to another exemplary embodiment.

9 is a timing diagram illustrating an operation of the voltage generator of FIG. 5 according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: voltage generator

11: voltage detector

12: latch portion

13: ring oscillator

14: charge pump

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a voltage generator and a voltage generating method.

In general, a semiconductor device generates and uses an internal voltage having various levels according to an internal situation using a voltage applied from the outside. In this case, a voltage lower than the externally applied voltage is simply generated using a voltage divider using a resistor, but a voltage generator using a charge pump is used to generate a voltage having a voltage higher than the externally applied voltage or a reverse phase. The voltage generator consists of a voltage detector, a ring oscillator, and a charge pump. The voltage generator requires a minimum time to complete one cycle of operation.

In the conventional voltage generator, when the output signal of the voltage detector is changed to “low” in a section in which the output signal of the ring oscillator is “high”, a problem may occur in that the charge pump may stop immediately. Because it is impossible to predict when the output signal of the voltage detector will turn "low", it is impossible to predict how long the last pulse width of the output signal of the ring oscillator will be.

For example, in the case of a three-stage pumping charge pump, if the pulse width of the output signal of the ring oscillator is wide enough, the charge pump operates up to three stages of pumping to supply sufficient charge, so that the output voltage reaches the target value. Can be reached. However, when the pulse width of the output signal of the ring oscillator is narrow, the charge pump may operate up to two stage pumping so that no charge is supplied. In addition, since it is difficult to predict the voltage level of internal nodes while the charge pump is not operating, an error may occur in the charge pump during the next operation. If you add a path that precharges the internal node's voltage level to the initial state while the charge pump is not operating, the error may not occur in the charge pump during the next operation. It will not contribute to raising the level.

Therefore, there is a need for a voltage generator that guarantees one cycle of the charge pump, thereby preventing operation of the charge pump and reducing power consumption.

An object of the present invention is to provide a voltage generator (Voltage Generator) that can prevent the operation error of the charge pump, and can reduce the power consumption.

Another object of the present invention is to provide a semiconductor device including a voltage generator capable of preventing an operation error of a charge pump and reducing power consumption.

Still another object of the present invention is to provide a voltage generation method which can prevent an operation error of the charge pump and reduce power consumption.

A voltage generator according to an embodiment of the present invention includes a charge pump, a voltage detector, a latch unit, and an oscillator. The charge pump receives the first oscillation signal and performs charge pumping during the period in which the first oscillation signal is activated to adjust the level of the internal voltage. The voltage detector detects a level of the internal voltage, and activates and outputs a first detection signal when the internal voltage is out of a reference level. The latch unit buffers the first detection signal and outputs the second detection signal when the second oscillation signal based on the first oscillation signal is inactivated, and when the second oscillation signal is activated, the second oscillation signal. Outputs the latched first detection signal as the second detection signal when is activated. The oscillator is driven based on the second detection signal to output the first oscillation signal.

In some embodiments, the second oscillation signal may be the same as the first oscillation signal.

In an embodiment, the voltage generator is connected between an output terminal of the oscillator and an input terminal of the latch unit, and receives the first oscillation signal to output the second oscillation signal extending the activation period of the first oscillation signal. It may further comprise a pulse width expander. The pulse width expander may output the second oscillation signal by performing an OR operation on the signal obtained by inverting the first oscillation signal N times (N is an even number of 2 or more) and the first oscillation signal.

In an embodiment, the latch unit may include a first inverter configured to receive and invert the second oscillation signal; A transfer gate configured to transfer the first detection signal in response to an output of the first inverter and the second oscillation signal; A second inverter configured to receive and invert the first detection signal passing through the transfer gate; A third inverter configured to receive the output of the second inverter, invert it, and provide it to an input terminal of the second inverter; And a fourth inverter that receives the output of the second inverter, inverts the output of the second inverter, and outputs the second detection signal.

In an embodiment, the latch unit may include a first inverter configured to receive and invert the second oscillation signal; A transfer gate configured to transfer the first detection signal in response to an output of the first inverter and the second oscillation signal; A second inverter configured to receive and invert the first detection signal passing through the transfer gate; A clock inverter controlled by the output of the first inverter and the second oscillation signal, receiving and inverting the output of the second inverter and providing it to an input terminal of the second inverter; And a third inverter configured to receive the output of the second inverter, invert it, and output the inverted signal as the second detection signal.

A semiconductor device according to an embodiment of the present invention may include a voltage generator including a charge pump, a voltage detector, a latch unit, and an oscillator. The charge pump receives the first oscillation signal and performs charge pumping during the period in which the first oscillation signal is activated to adjust the level of the internal voltage. The voltage detector detects a level of the internal voltage, and activates and outputs a first detection signal when the internal voltage is out of a reference level. The latch unit buffers the first detection signal and outputs the second detection signal when the second oscillation signal based on the first oscillation signal is inactivated, and when the second oscillation signal is activated, the second oscillation signal. Outputs the latched first detection signal as the second detection signal when is activated. The oscillator is driven based on the second detection signal to output the first oscillation signal.

In some embodiments, the second oscillation signal may be the same as the first oscillation signal.

In an embodiment, the voltage generator is connected between an output terminal of the oscillator and an input terminal of the latch unit, and receives the first oscillation signal to output the second oscillation signal extending the activation period of the first oscillation signal. It may further comprise a pulse width expander. The pulse width expander may output the second oscillation signal by performing an OR operation on the signal obtained by inverting the first oscillation signal N times (N is an even number of 2 or more) and the first oscillation signal.

According to an embodiment of the present invention, a voltage generation method includes: receiving a first oscillation signal and performing charge pumping during a period in which the first oscillation signal is activated, adjusting the level of the internal voltage; Detecting a level of the internal voltage and activating and outputting a first detection signal when the internal voltage is out of a reference level; When the second oscillation signal based on the first oscillation signal is inactivated, the first detection signal is buffered and output as a second detection signal. When the second oscillation signal is activated, the second oscillation signal is activated. Outputting the latched first detection signal as the second detection signal; And driving based on the second detection signal to output the first oscillation signal.

In some embodiments, the second oscillation signal may be the same as the first oscillation signal.

According to an embodiment, the voltage generation method may further include receiving the first oscillation signal and outputting the second oscillation signal extending the activation period of the first oscillation signal. The outputting of the second oscillation signal may output the second oscillation signal by performing an OR operation on the signal obtained by inverting the first oscillation signal N times (N is an even number of two or more) and the first oscillation signal.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, operations, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a block diagram illustrating a voltage generator according to an embodiment of the present invention.

Referring to FIG. 1, the voltage generator 10 includes a voltage detector 11, a latch unit 12, a ring oscillator 13, and a charge pump 14 to generate an output voltage V14.

According to an embodiment, the voltage generator 10 may be a high voltage generator that generates a voltage higher than an externally applied voltage, or may be a negative voltage generator that generates a negative voltage. Hereinafter, the operation of the phase high voltage generator will be described for convenience of description.

The voltage detector 11 detects the output voltage V14 and outputs a first detection signal V11 that is activated when the output voltage V14 falls below a reference voltage of a target level. It will be apparent to those skilled in the art that the voltage detector 11 may be implemented in various ways such as a differential amplifier type or an inverter type.

The latch unit 12 receives the first detection signal V11, and accordingly performs a latch operation to output the second detection signal V12.

The ring oscillator 13 receives the second detection signal V12 and is driven when the second detection signal V12 is activated to generate an oscillation signal V13.

The charge pump 14 receives the oscillation signal V13 and performs charge pumping during a period in which the oscillation signal V13 is activated to generate the output voltage V14.

2 is a circuit diagram illustrating a latch unit included in the voltage generator of FIG. 1 according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the latch unit 12A includes a transfer gate 111 and first to fourth inverters 112, 113, 114, and 115.

The first inverter 112 receives and inverts the oscillation signal V13 and provides the inverted signal to the transfer gate 111.

The transfer gate 111 receives the oscillation signal V13 and its inverted signal, that is, the output of the first inverter 112. When the oscillation signal V13 is logic 'low', the transfer gate 111 is turned on, so that the first detection signal V11 is transmitted to the second inverter 113. When the oscillation signal V13 is logic 'high', the transfer gate 111 is turned off, so that the first detection signal V11 is not transmitted to the second inverter 113.

When the transfer gate 111 is turned on, the second inverter 113 receives and inverts the first detection signal V11. The third inverter 114 receives and inverts the output of the second inverter 113. The output terminal of the third inverter 114 is connected to the input terminal of the second inverter 113 to form a latch structure.

When the transfer gate 111 is turned off, the second inverter 113 does not receive the first detection signal V11 and receives the output of the third inverter 114 to receive a previous level signal. Output

The fourth inverter 115 receives and inverts the output of the second inverter 113. The output of the fourth inverter 115 becomes the second detection signal V12.

  3 is a circuit diagram illustrating a latch unit included in the voltage generator of FIG. 1 according to another exemplary embodiment of the present disclosure.

Referring to FIG. 3, the latch unit 12B includes a transfer gate 121, first to third inverters 122, 123, and 125 and a clocked inverter 124.

The first inverter 122 receives the oscillation signal V13 and provides an output signal V15 inverted thereto to the transfer gate 121.

The transfer gate 121 receives the oscillation signal V13 and its inverted signal, that is, the output signal V15 of the first inverter 122. When the oscillation signal V13 is logic 'low', the transfer gate 121 is turned on, so that the first detection signal V11 is transmitted to the second inverter 123. When the oscillation signal V13 is logic 'high', the transfer gate 121 is turned off, so that the first detection signal V11 is not transmitted to the second inverter 123.

When the transfer gate 121 is turned on, the second inverter 123 receives the first detection signal V11 and generates an output signal V16 inverting it. The clock inverter 124 receives the output signal V16 of the second inverter 123 and inverts the output signal V17 in response to the oscillation signal V13 and its inverted signal V15. Create An internal structure and operation of the clock inverter 124 will be described below with reference to FIG. 4. The output terminal of the clock inverter 124 is connected to the input terminal of the second inverter 123 to form a latch structure.

When the transfer gate 121 is turned off, the second inverter 123 does not receive the first detection signal V11, but receives the output signal V17 of the clock inverter 124 to a previous level. Outputs the signal of.

The third inverter 125 receives and inverts the output signal V16 of the second inverter 123. The output of the fourth inverter 125 becomes the second detection signal V12.

4 is a circuit diagram illustrating a clock inverter included in the latch unit of FIG. 3 according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the clock inverter 124 includes first and second PMOS transistors MP1 and MP2 and first and second NMOS transistors MN1 and MN2 connected in series between a power supply voltage and a ground voltage. ).

The gate of the first PMOS transistor MP1 receives the inverted signal of the oscillation signal V13, that is, the output signal V15 of the first inverter 122, and the second NMOS transistor MN2. The gate of receives the oscillation signal V13.

When the oscillation signal V13 is logic 'high', the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on so that the clock inverter 124 performs an inversion operation. Can be. In this case, the gates of the second PMOS transistor MP2 and the first NMOS transistor MN1 receive the output signal V16 of the second inverter 123. When the output signal V16 of the second inverter 123 is logic 'high', the output signal V17 of the clock inverter 124 is logic 'low' and the output signal of the second inverter 123 is When V16 is logic 'low', the output signal V17 of the clock inverter 124 becomes logic 'high'.

When the oscillation signal V13 is logic 'low', the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned off so that the clock inverter 124 performs an inversion operation. Can't.

5 is a block diagram illustrating a voltage generator according to an embodiment of the present invention.

Referring to FIG. 5, the voltage generator 20 includes a voltage detector 21, a latch unit 22, a ring oscillator 23, a charge pump 24, and a pulse width expander 25, and output voltage V24. ) Unlike the voltage generator 10 of FIG. 1, the voltage generator 20 further includes the pulse width expander 25 to extend the pulse width of the output signal V23 of the ring oscillator 23 to the latch. It is provided to the part 22.

According to an embodiment, the voltage generator 20 may be a high voltage generator or a negative voltage generator. Hereinafter, for convenience of description, the operation of the high voltage generator will be described.

The voltage detector 21 senses the output voltage V24 and outputs a first detection signal V21 that is activated when the output voltage V24 falls below a reference voltage of a target level.

The latch unit 22 receives the first detection signal V21, and accordingly performs a latch operation to output the second detection signal V22.

The ring oscillator 23 is driven based on the second detection signal V22 to output the first oscillation signal V23.

The charge pump 24 receives the first oscillation signal V23 and performs charge pumping during a period in which the first oscillation signal V23 is activated to generate the output voltage V24.

The pulse width expander 25 is connected between an output terminal of the ring oscillator 23 and an input terminal of the latch unit 22 to receive the first oscillation signal V23 to receive the first oscillation signal V23. The second oscillation signal V25 having the extended activation period is output.

6 is a circuit diagram illustrating a pulse width expander included in the voltage generator of FIG. 5 according to an embodiment of the present invention.

Referring to FIG. 6, the pulse width expander 25 includes an output inverter 251, a NOR gate 252, and an even number of inverters 253, 254, 255, and 256.

The even-numbered inverters 253, 254, 255, and 256 receive the first oscillation signal V23, invert the even number of times, and output a delayed first oscillation signal. The NOR gate 252 receives the first oscillation signal V23 and the delayed first oscillation signal and performs a NOR operation. The output inverter 251 receives and inverts the output of the NOR gate 252. The output of the output inverter 251 becomes the second oscillation signal V25.

The pulse width expander 25 includes the NOR gate 252 and the output inverter 251. However, the pulse width expander 25 may perform an OR operation by varying the configuration according to an embodiment. Do.

As the number of even-numbered inverters increases, the delay amount of the first oscillation signal V23 increases. Since the pulse width expander 25 performs an OR operation on the first oscillation signal V23 and the delayed first oscillation signal, as the number of the even-numbered inverters increases, the second oscillation signal V25 is logic. The interval 'high', that is, the pulse width is increased. Accordingly, the number of even-numbered inverters may be adjusted to appropriately secure a margin from the falling edge of the first detection signal V21 to the falling edge of the first oscillation signal V23.

FIG. 7 is a circuit diagram illustrating a latch unit included in the voltage generator of FIG. 5, according to an exemplary embodiment.

Referring to FIG. 7, the latch portion 22A includes a transfer gate 211 and first to fourth inverters 212, 213, 214, and 215.

The first inverter 212 receives and inverts the second oscillation signal V25 to provide it to the transfer gate 211.

The transfer gate 211 receives the second oscillation signal V25 and its inverted signal, that is, the output of the first inverter 212. When the second oscillation signal V25 is logic 'low', the transfer gate 211 is turned on so that the first detection signal V21 is transmitted to the second inverter 213. . When the second oscillation signal V25 is logic 'high', the transfer gate 211 is turned off so that the first detection signal V21 is not transmitted to the second inverter 213. Do not.

When the transfer gate 211 is turned on, the second inverter 213 receives and inverts the first detection signal V21. The third inverter 214 receives and inverts the output of the second inverter 213. The output terminal of the third inverter 214 is connected to the input terminal of the second inverter 213 to form a latch structure.

When the transfer gate 211 is turned off, the second inverter 213 does not receive the first detection signal V21 and receives the output of the third inverter 214 to receive a previous level signal. Output

The fourth inverter 215 receives and inverts the output of the second inverter 213. The output of the fourth inverter 215 becomes the second detection signal V22.

FIG. 8 is a circuit diagram illustrating a latch unit included in the voltage generator of FIG. 5, according to another exemplary embodiment.

Referring to FIG. 8, the latch unit 22B includes a transfer gate 221, first to third inverters 222, 223, and 225, and a clock inverter 224.

The first inverter 222 receives the second oscillation signal V25 and provides an output signal V26 inverted thereto to the transfer gate 221.

The transfer gate 221 receives the second oscillation signal V25 and its inverted signal, that is, the output signal V26 of the first inverter 222. When the second oscillation signal V25 is logic 'low', the transfer gate 221 is turned on so that the first detection signal V21 is transmitted to the second inverter 223. . When the second oscillation signal V25 is logic 'high', the transfer gate 221 is turned off so that the first detection signal V21 is not transmitted to the second inverter 223. Do not.

When the transfer gate 221 is turned on, the second inverter 223 receives the first detection signal V21 and generates an inverted output signal V27. The clock inverter 224 receives the output signal V27 of the second inverter 223 in response to the second oscillation signal V25 and the inverted signal V26 thereof, and inverts the output signal V28. ) Since the internal structure and operation of the clock inverter 224 are the same as in FIG. 4, a detailed description thereof will be omitted. The output terminal of the clock inverter 224 is connected to the input terminal of the second inverter 223 to form a latch structure.

When the transfer gate 221 is turned off, the second inverter 223 does not receive the first detection signal V21, but receives the output signal V28 of the clock inverter 224 to provide a previous level. Outputs the signal of.

The third inverter 225 receives and inverts the output signal V27 of the second inverter 223. The output of the fourth inverter 225 becomes the second detection signal V22.

9 is a timing diagram illustrating an operation of the voltage generator of FIG. 5 according to an embodiment of the present invention.

The voltage generator 20 of FIG. 5 may include the latch portion 22A of FIG. 7 or the latch portion 22B of FIG. 8, but the latch portion 22B of FIG. 8 is referred to as the voltage generator 20 of FIG. 5. Will be described.

Referring to FIG. 9, the output voltage V24, the first detection signal V21 of the voltage detector 21, the second detection signal V22 of the latch unit 22, and the ring oscillator 23 The first oscillation signal V23 and the second oscillation signal V25 of the pulse width expander 25 appear in order.

  When the output voltage V24 of the charge pump 24 falls below a target level, the voltage detector 21 detects this and outputs the first detection signal V21 as logic 'high'. In this case, since the ring oscillator 23 is before operation, the first oscillation signal V23 is logic 'low', and the second oscillation signal V25 of the pulse width expander 25 is also logic 'low'. 'to be. In response to the second oscillation signal V25, the transfer gate 221 of the latch unit 22B is turned on, so that the first detection signal V21 in a 'high' state is transferred to the latch unit ( 22B) outputs a second detection signal V22 that is logic 'high'.

When the second detection signal 22 is logic 'high', the ring oscillator 23 operates to output a constant pulse signal, that is, the first oscillation signal V23. The charge pump 24 performs a pumping operation in response to the first oscillation signal V23 to supply charge to an output node, whereby the output voltage V24 is raised.

When the operation of the ring oscillator 23 starts in response to the second detection signal V12, the ring oscillator 23 continues to generate the first oscillation signal V23 having a constant pulse width. The pulse width expander 25 receives the first oscillation signal V23 to generate the second oscillation signal V25 having an increased pulse width. The transfer gate 221 of the latch unit 22B does not transmit the first detection signal V21 while the second oscillation signal V25 is a logic '1'.

Therefore, even if the output voltage V24 rises above the target level and the first detection signal V21 turns to logic 'low', while the first oscillation signal V23 is logic 'high', The second oscillation signal V24 is also logic 'high'. In this case, the transfer gate 221 of the latch unit 22 does not transmit the first detection signal V21 that is logic 'low', and transmits the latched logic 'high' signal to the second detection signal V22. ) That is, even if the output voltage rises above the target value, the second detection signal V22 maintains a logic 'high' to ensure one cycle of the pumping operation of the charge pump 24.

After one cycle of the charge pump 24 once started, the second detection signal V22 turns to logic 'low' to stop the operation of the ring oscillator 23 and the first oscillation signal ( V23) changes to logic 'low'. Since one cycle of the pumping operation of the charge pump 24 is guaranteed, an operation error of the charge pump 24 can be prevented and power consumption can be reduced.

As described above, the voltage generator and the voltage generating method according to the embodiment of the present invention can guarantee one cycle of the pumping operation of the charge pump, thereby preventing an operation error of the charge pump and reducing power consumption.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

Claims (14)

A charge pump configured to receive a first oscillation signal and perform charge pumping during a period in which the first oscillation signal is activated, thereby adjusting a level of an internal voltage; A voltage detector detecting the level of the internal voltage and activating and outputting a first detection signal when the internal voltage is out of a reference level; When the second oscillation signal based on the first oscillation signal is inactivated, the first detection signal is buffered and output as a second detection signal. When the second oscillation signal is activated, the second oscillation signal is activated. A latch unit for outputting the first detection signal latched at the time as the second detection signal; And And a oscillator driven based on the second detection signal to output the first oscillation signal. The voltage generator of claim 1, wherein the second oscillation signal is the same as the first oscillation signal. The oscillator of claim 1, wherein the voltage generator is connected between an output terminal of the oscillator and an input terminal of the latch unit, and receives the first oscillation signal to output the second oscillation signal extending the activation period of the first oscillation signal. The voltage generator further comprises a pulse width expander. 4. The pulse oscillator of claim 3, wherein the pulse width expander outputs the second oscillation signal by performing an OR operation on the signal obtained by inverting the first oscillation signal N times (N is an even number of 2 or more) and the first oscillation signal. Voltage generator. The method of claim 4, wherein the latch unit A first inverter configured to receive and invert the second oscillation signal; A transfer gate configured to transfer the first detection signal in response to an output of the first inverter and the second oscillation signal; A second inverter configured to receive and invert the first detection signal passing through the transfer gate; A third inverter configured to receive the output of the second inverter, invert it, and provide it to an input terminal of the second inverter; And And a fourth inverter which receives the output of the second inverter, inverts the output of the second inverter, and outputs the second detection signal. The method of claim 4, wherein the latch unit A first inverter configured to receive and invert the second oscillation signal; A transfer gate configured to transfer the first detection signal in response to an output of the first inverter and the second oscillation signal; A second inverter configured to receive and invert the first detection signal passing through the transfer gate; A clock inverter controlled by the output of the first inverter and the second oscillation signal, receiving and inverting the output of the second inverter and providing it to an input terminal of the second inverter; And And a third inverter which receives the output of the second inverter, inverts the output of the second inverter, and outputs the second detection signal. A charge pump configured to receive a first oscillation signal and perform charge pumping during a period in which the first oscillation signal is activated, thereby adjusting a level of an internal voltage; A voltage detector detecting the level of the internal voltage and activating and outputting a first detection signal when the internal voltage is out of a reference level; When the second oscillation signal based on the first oscillation signal is inactivated, the first detection signal is buffered and output as a second detection signal. When the second oscillation signal is activated, the second oscillation signal is activated. A latch unit for outputting the first detection signal latched at the time as the second detection signal; And And a voltage generator driven on the basis of the second detection signal and including an oscillator for outputting the first oscillation signal. 8. The semiconductor device of claim 7, wherein the second oscillation signal is the same as the first oscillation signal. The oscillator of claim 7, wherein the voltage generator is connected between an output terminal of the oscillator and an input terminal of the latch unit, and receives the first oscillation signal to output the second oscillation signal extending the activation period of the first oscillation signal. The semiconductor device further comprises a pulse width expander. 10. The method of claim 9, wherein the pulse width expander outputs the second oscillation signal by performing an OR operation on the signal obtained by inverting the first oscillation signal N times (N is an even number of 2 or more) and the first oscillation signal. Semiconductor device. Adjusting a level of the internal voltage by receiving a first oscillation signal and performing charge pumping during a period in which the first oscillation signal is activated; Detecting a level of the internal voltage and activating and outputting a first detection signal when the internal voltage is out of a reference level; When the second oscillation signal based on the first oscillation signal is inactivated, the first detection signal is buffered and output as a second detection signal. When the second oscillation signal is activated, the second oscillation signal is activated. Outputting the latched first detection signal as the second detection signal; And And driving the second detection signal based on the second detection signal to output the first oscillation signal. 12. The method of claim 11, wherein the second oscillation signal is the same as the first oscillation signal. 12. The method of claim 11, wherein the voltage generation method further comprises receiving the first oscillation signal and outputting the second oscillation signal extending the activation period of the first oscillation signal. . The method of claim 13, wherein the outputting of the second oscillation signal comprises performing an OR operation on the signal obtained by inverting the first oscillation signal N times (N is an even number of two or more) and the first oscillation signal to generate the second oscillation signal. Voltage generation method characterized in that the output.

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