KR20080046814A - Liquid crystal display and manufacturing method thereof - Google Patents

Abstract

An LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to install a semiconductor and a resistant contact member between an end portion of a data line and a substrate, thereby preventing the end portion of the data line from peeling off. A gate line is formed on an insulating substrate(110) and includes a gate pad. A gate insulating layer(140) is formed on the gate line. A semiconductor and a resistant contact member are formed sequentially on the gate insulating layer. A data line and a drain electrode are formed on the resistant contact member and includes a source electrode and a data pad. A passivation layer is formed on the data line and the drain electrode. A pixel electrode is formed on the passivation layer. The data pad is contacted with the resistant contact member. The layer structure of the data line and the drain electrode is different from that of the resistant contact member. The resistant contact member is made of doped amorphous silicon.

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views taken along line II-II, line III-III ', and line III'-III of FIG. 1, respectively, of the liquid crystal display including the thin film transistor array panel illustrated in FIG. 1;

4 is a layout view of a thin film transistor array panel at an intermediate stage of manufacturing the thin film transistor array panel illustrated in FIG. 1 according to an exemplary embodiment of the present disclosure;

5 and 6 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 4 taken along the lines V-V ', VI-VI', and VI'-VI '', respectively.

FIG. 7 is a layout view of a thin film transistor array panel in the next step of FIG. 4;

8 and 9 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along the lines VIII-VIII ', IX-IX', and IX'-IX '', respectively.

FIG. 10 is a layout view of a thin film transistor array panel in the next step of FIG. 7;

11 and 12 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 10 taken along lines XI-XI ', XII-XII', and XII'-XII '', respectively.

FIG. 13 is a layout view of a thin film transistor array panel in the next step of FIG. 10.

14 and 15 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 13 taken along lines XIV-XIV ', XV-XV', and XV-XV ', respectively.

The present invention relates to a liquid crystal display and a method of manufacturing the same.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic light emitting display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) for transmitting a scan signal to the thin film transistor and a data line for transmitting a data signal, in addition to the thin film transistor and the pixel electrode connected thereto.

The thin film transistor is a switching element that controls a data signal transmitted to a pixel electrode through a data line according to a gate signal transmitted through a gate line. The thin film transistor includes a semiconductor layer and a data line forming a channel and a gate electrode connected to the gate line. A source electrode and a drain electrode facing the source electrode are mainly formed around the semiconductor layer. In this case, the data signal is transmitted through a data pad that is electrically connected to the driver, that is, the end of the data line.

In order to manufacture the thin film transistor array panel, several photolithography processes are required.

Meanwhile, in the thin film transistor array panel formed through five etching processes, an end portion of the data line is present on the insulating substrate. Here, the end portion of the data line made of chromium (Cr) has a low adhesive strength with the insulating substrate.

Thus, the end portion of the data line may be lifted or separated from the substrate during the liquid crystal display manufacturing process. At this time, when pieces of data lines separated from the substrate are placed between neighboring data lines, neighboring data lines are shorted to each other.

Therefore, the technical problem to be achieved by the present invention is to improve the adhesion of the end of the data line when forming a thin film transistor array panel through a five-time photolithography process.

In the method of manufacturing a liquid crystal display according to the present invention, forming a gate line including a gate pad on an insulating substrate, forming a gate insulating film on the gate line, and sequentially forming a semiconductor layer and a contact member layer on the gate insulating film. Forming a semiconductor and a resistive contact member by patterning the semiconductor layer and the contact member layer, forming a data line and a drain electrode including a source electrode and a data pad on the resistive contact member, the data line and Forming a passivation layer on the drain electrode, wherein the ohmic contact and the semiconductor are sequentially formed below the data pad.

The data line and the drain electrode may include chromium (Cr).

The method may further include forming a contact hole exposing the gate pad, the data pad, and the drain electrode by etching the passivation layer, and forming a pixel electrode on the contact hole and the passivation layer.

An insulating substrate, a gate line including a gate pad, a gate insulating film formed on the gate line, a semiconductor and an ohmic contact member sequentially formed on the gate insulating film, and formed on the ohmic contact member. And a data line and a drain electrode including a source electrode and a data pad, a passivation layer formed on the data line and the drain electrode, and a pixel electrode formed on the passivation layer, wherein the data pad includes an end of the ohmic contact member. In contact with the portion, the layer structure of the data line and the drain electrode and the layer structure of the ohmic contact member are different from each other.

The ohmic contact may be made of doped amorphous silicon.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in between. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, the structure of a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

FIG. 1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 illustrate a liquid crystal display including the thin film transistor array panel shown in FIG. 1, respectively. Sectional view taken along lines III-III 'and III'-III.

1 to 3, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding downward and an end portion 129 having a large area for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110, It may be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the gate line 121 and a plurality of pairs of storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line is closer to the lower side of the two gate lines 121. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of one sustain electrode 133b has a large area, and its free end is divided into two parts, a straight part and a bent part. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, or molybdenum ( It may be made of molybdenum-based metals such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal to reduce signal delay or voltage drop. On the other hand, other conductive films are made of other materials, particularly materials having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum, and the like. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 121 and 124 and the storage electrode line 131 may be made of various metals and conductors.

Side surfaces of the gate conductors 121 and 124 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 121 and 124 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of polysilicon are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, and its end portion 159 is wide and includes a plurality of projections 154 extending toward the gate electrode 124. The linear semiconductor 151 has a wider width in the vicinity of the gate line 121 and the storage electrode line 131 and covers them widely.

Linear and island ohmic contacts 161 and 165 are sequentially formed on the semiconductor 151. The end portion 169 of the linear ohmic contact 161 is present over the end portion 159 of the semiconductor 151 and is wide.

The ohmic contacts 161 and 165 may be made of a material such as amorphous silicon and polycrystalline silicon doped with a high concentration of n-type impurities such as phosphorus or p-type impurities such as boron (B), or may be made of silicide. . The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductors 151 and 154 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and runs between adjacent sets of storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and an end portion 179 having a large area for connection with another layer or an external driving circuit. In this case, the end portion 179 of the data line 171 is present on the end portion 169 of the linear ohmic contact 161.

In the present invention, the linear resistive contact member made of amorphous silicon doped with the end portion 179 of the data line 171 made of the above-described metal in the five-sheet liquid crystal display formed by using the five-time photolithography process ( The adhesive force may be improved by being brought into contact with the end portion 169 of the 161. Accordingly, a defect in which the data line 171 is separated from the substrate 110 and is disposed between the data lines 171 which are adjacent to each other can be prevented in advance. Here, the layer structures of the data line 171 and the drain electrode 175 and the layer structures of the ohmic contacts 161 and 165 are different from each other.

A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with respect to the gate electrode 124.

Each drain electrode 175 has one wide end portion and the other end having a rod shape, and the rod end portion is partially surrounded by the bent source electrode 173.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, titanium, or an alloy thereof, and a conductive film (not shown) such as a refractory metal and a low resistance material conductive film. It may have a multilayer film structure composed of (not shown). Examples of the multilayer film structure include a double film of chromium or molybdenum (alloy) lower film and an aluminum (alloy) upper film, a triple layer of molybdenum (alloy) lower film, aluminum (alloy) interlayer and molybdenum (alloy) upper film. However, the data conductors 171 and 175 may be made of various other metals or conductors.

The data conductors 171 and 175 also preferably have their side surfaces inclined at an inclination angle of 30 ° to 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 thereon, the end portion 179 of the data line 171 and the drain electrode 175 therebetween. Lower the contact resistance.

The semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and not covered by the data line 171, the end portion 179 of the data line 171, and the drain electrode 175. have. In most places, the width of the linear semiconductor 151 is smaller than the width of the data line 171. However, as described above, the width of the linear semiconductor 151 is widened at the portion where it meets the gate line 121 to smooth the profile of the surface. Prevents disconnection.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed semiconductor 151.

The passivation layer 180 is made of an organic insulator or the like, and has a flat surface. Here, the organic insulator may have photosensitivity and the dielectric constant thereof is preferably about 4.0 or less.

The passivation layer 180 is formed with a plurality of contact holes 181, 182, and 185 exposing the end portion 179 and the drain electrode 175 of the data line 171, respectively. The gate insulating layer 140 includes a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 and a plurality of contact holes 183a exposing a part of the sustain electrode line 131 near the fixed end of the sustain electrode 133b. And a plurality of contact holes 183b exposing a straight portion of the free end of the sustain electrode 133a.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied has a liquid crystal between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. The direction of the liquid crystal molecules in the layer (not shown) is determined. The polarization of light passing through the liquid crystal layer varies according to the direction of the liquid crystal molecules determined as described above. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor formed by the pixel electrode 191 and the drain electrode 175 electrically connected to the pixel electrode 191 overlapping the storage electrode line 131 is called a storage capacitor, and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact assistants 81 and 82 compensate for and protect the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device.

The connecting leg 83 crosses the gate line 121 and exposes the exposed portion of the storage electrode line 131 and the storage electrode through contact holes 183a and 183b positioned on opposite sides with the gate line 121 interposed therebetween. 133b) is connected to the exposed end of the free end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device shown in FIGS. 1 to 3 according to an embodiment of the present invention will be described in detail with reference to FIGS. 4 to 15.

5 and 6 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 4 taken along the lines V-V ', VI-VI', and VI'-VI '', respectively, and FIG. 7 is a next step of FIG. 8 and 9 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along the lines VIII-VIII ', IX-IX', and IX'-IX '', respectively. FIG. 10 is a layout view of a thin film transistor array panel in the next step of FIG. 7, and FIGS. 11 and 12 are lines XI-XI ′, XII-XII ′, and XII′-XII ′, respectively, of the thin film transistor array panel illustrated in FIG. 10. 13 is a layout view of a thin film transistor array panel in the next step of FIG. 10, and FIGS. 14 and 15 show XIV-XIV and XV- lines of the thin film transistor array panel shown in FIG. It is sectional drawing cut along the XV 'line and XV-XV "line.

First, as shown in FIGS. 4 to 6, a metal film is sputtered on the insulating substrate 110 made of glass or plastic, and then photo-etched to form the gate electrode 124 and the end portion 129. ) And a plurality of storage electrode lines 131 including the plurality of gate lines 121 and the storage electrodes 133a and 133b.

Next, as illustrated in FIGS. 7 to 9, the gate insulating layer 140 is laminated on the gate line 121 and the storage electrode line 131 by a chemical vapor deposition method or the like.

Subsequently, intrinsic amorphous silicon and impurity amorphous silicon layers are sequentially stacked on the gate insulating layer 140, and the two layers are sequentially patterned to form a plurality of linear impurity semiconductors 164 and a plurality of layers. The linear intrinsic semiconductor 151 is formed.

Next, as shown in FIGS. 10 to 12, a metal film is sputtered on the gate insulating layer 140 and the linear impurity semiconductor 164 and photo-etched to form a drain electrode 175 and a source electrode ( A plurality of data lines 171 including 173 and end portions 179 of the data lines 171 are formed. Subsequently, as illustrated in FIGS. 13 and 15, the plurality of linear portions including the protrusions 163 are removed by removing portions of the impurity semiconductor 164 that are not covered by the data line 171 and the drain electrode 175. The ohmic contact 161 and the plurality of islands of ohmic contact 165 are completed, while the portion of the intrinsic semiconductor 151 underneath is exposed. Here, the end portion 169 of the linear ohmic contact 161 is formed between the end portion 179 of the data line 171 and the end portion 159 of the linear semiconductor intrinsic semiconductor 151. 171 is wider than the width of the linear ohmic contact 161 formed below.

As described above, in the thin film transistor array panel according to the exemplary embodiment of the present invention, the end portion 169 of the linear ohmic contact 161 and the end portion of the linear intrinsic semiconductor 151 under the end portion 179 of the data line 171. 159 are arranged one by one. Accordingly, the end portion 179 of the data line 171 contacts the end portion 169 of the linear ohmic contact 161, and the data line made of metal and the linear ohmic contact member 161 made of doped amorphous silicon. The 171 may be excellent in adhesion, thereby preventing the data line 171 from peeling off and causing a defect in a subsequent liquid crystal display manufacturing process.

Next, it is preferable to perform oxygen (O ₂ ) plasma following to stabilize the surface of the exposed intrinsic semiconductor 151 portion.

Next, the passivation layer 180 made of the photosensitive organic material may be coated with the gate insulating layer 140, the drain electrode 175, and the data line 171.

Subsequently, the protective layer 180 is irradiated with light through a photo mask (not shown), and then developed to expose the contact holes 182 and 185 exposing the drain electrode 175 and the end portion 179 of the data line 171. And a plurality of contact holes 183a exposing the end portion 129 of the gate line 121 and a portion of the storage electrode line 131 near the fixed end of the storage electrode 133b by removing a portion of the gate insulating layer 140 thereunder. And a plurality of contact holes 183b exposing a straight portion of the free end of the sustain electrode 133a.

Finally, as shown in FIGS. 1 to 3, transparent electrodes such as ITO or IZO are sputtered on the contact holes 181, 182, 183a, 183b, and 185 and the passivation layer 180, and a plurality of photolithography processes are performed by sputtering. The pixel electrode 191, the contact members 81 and 82, and the connection electrode 83 are formed.

According to the present invention, when the thin film transistor array panel is manufactured by performing an etching process five times, a semiconductor and an ohmic contact may be disposed between the end of the data line and the substrate to prevent the data line from being peeled off. Therefore, the reliability of the liquid crystal display device can be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (5)

Forming a gate line including a gate pad on the insulating substrate, Forming a gate insulating film on the gate line; Sequentially forming a semiconductor layer and a contact member layer on the gate insulating film, Patterning the semiconductor layer and the contact member layer to form a semiconductor and an ohmic contact; Forming a data line and a drain electrode including a source electrode and a data pad on the ohmic contact member; Forming a passivation layer on the data line and the drain electrode Including; And a resistive contact member and the semiconductor are sequentially formed below the data pad. In claim 1, The data line and the drain electrode include chromium (Cr). In claim 1, Etching the passivation layer to form contact holes exposing the gate pad, the data pad, and the drain electrode, respectively; And forming a pixel electrode on the contact hole and the passivation layer. Insulation board, A gate line formed on the insulating substrate and including a gate pad; A gate insulating film formed on the gate line, A semiconductor and an ohmic contact member which are sequentially formed on the gate insulating film, A data line and a drain electrode formed on the ohmic contact and including a source electrode and a data pad; A protective film formed on the data line and the drain electrode; A pixel electrode formed on the passivation layer Including; And the data pad is in contact with the ohmic contact, and the layer structure of the data line and the drain electrode is different from the layer structure of the ohmic contact. In claim 4, And the ohmic contact member is formed of doped amorphous silicon.

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