KR20080046454A - Thin film transistor array substrate and manufacturing method of the same - Google Patents

Abstract

A thin film transistor array substrate and a manufacturing method of the same are provided to improve the display quality by removal of residual image and prevention of contrast lowering through leakage current minimization, and to lower the production cost by a single layer patterning manner. A gate line(102) intersects a data line(108) interleaved with a gate insulation layer(144) in-between on a substrate(142). A TFT(Thin Film Transistor)(106) is formed on every intersection, connected to the data line and operated by the gate voltage supplied from the gate line. A pixel electrode(118) is connected to the TFT. The TFT comprises phase transition semiconductor pattern(160) having electric characteristic varied with the magnitude of gate voltage. The impedance of the phase transition semiconductor pattern decreases in case of applying gate high voltage to the gate line and increases in case of applying gate low voltage to the gate line. A storage capacitor is formed on the superposition section between the pixel electrode and gate line of previous section.

Description

Thin Film Transistor Array Substrate and Method for Manufacturing the Same {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD OF THE SAME}

1 is a plan view schematically illustrating a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′. FIG.

3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view schematically illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along a line II-II '.

6 is a simulation result showing a change in resistance in a phase-transfer semiconductor pattern with temperature.

7 is a simulation result showing the degree of leakage current generation in the channel in the present invention and the prior art.

8A through 8D are steps illustrating a manufacturing process of the thin film transistor array substrate illustrated in FIG. 6.

 <Description of Symbols for Main Parts of Drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10, 110: source electrode 12, 112: drain electrode

14, 114: active layer 16,116: first contact hole

18, 118: pixel electrode 20: storage capacitor

144 gate insulating film 160 phase change semiconductor pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array substrate and a method of manufacturing the same, which can improve display quality and simplify a process.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes a gate line and a data line, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, a pixel electrode formed of a liquid crystal cell and connected to the thin film transistor, and the like. It consists of the applied alignment film. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.

The liquid crystal panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

1 is a plan view illustrating a conventional thin film transistor array substrate, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 1 taken along the line II ′.

The thin film transistor array substrate illustrated in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed to intersect on a lower substrate 42 with a gate insulating film 44 interposed therebetween, and formed at each intersection thereof. A thin film transistor (hereinafter referred to as "TFT") 6 and a pixel electrode 18 formed in a cell region provided in a cross structure thereof are provided. The TFT array substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the previous gate line 2.

The TFT 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 16, The active layer 14 overlaps the gate electrode 8 and forms a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the storage upper electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and further has a channel portion between the source electrode 10 and the drain electrode 12. Include. An ohmic contact layer 48 for ohmic contact with the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14. Hereinafter, the active layer 14 and the ohmic contact layer 148 are referred to as a semiconductor pattern 49.

The TFT 6 causes the pixel voltage signal supplied to the data line 4 to be charged and held in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the TFT 6 through the first contact hole 16 penetrating the protective film 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the TFT array substrate and the color filter array substrate is rotated by dielectric anisotropy and transmits the light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The storage capacitor 20 includes a storage electrode 22 overlapping the front gate line 2, the gate line 2 and the gate insulating layer 44, the active layer 14, and the ohmic contact layer 48 therebetween, The pixel electrode 22 is overlapped with the storage electrode 22 and the passivation layer 50 interposed therebetween, and connected to the pixel electrode 22 via the second contact hole 24 formed in the passivation layer 50. The storage capacitor 20 helps the pixel voltage charged in the pixel electrode 18 to be maintained until the next pixel voltage is charged.

Hereinafter, a method of manufacturing a TFT array substrate will be described with reference to FIGS. 3A to 3D.

First, a gate metal layer is formed on the lower substrate 42 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a mask to form gate patterns including the gate line 2 and the gate electrode 8, as shown in FIG. 3A. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

The gate insulating layer 44 is formed on the lower substrate 42 on which the gate patterns are formed by a deposition method such as PECVD or sputtering. As the material of the gate insulating film 44, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

An amorphous silicon layer, an n + amorphous silicon layer, and a source / drain metal layer are sequentially formed on the lower substrate 42 on which the gate insulating layer 44 is formed.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the TFT 6 as a mask, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Next, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 4, the source electrode 10, the drain electrode 12 integrated with the source electrode 10, and the storage electrode 22 are formed. Source / drain patterns including are formed.

Next, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form a semiconductor pattern 49 including the ohmic contact layer 48 and the active layer 14.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, as shown in FIG. 3B, the active layer 14 of the channel portion is exposed and the source electrode 10 and the drain electrode 12 are electrically separated.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process. As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu), aluminum-based metal and the like are used.

The passivation layer 50 is entirely formed on the gate insulating layer 44 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 50 is patterned by a photolithography process and an etching process using a mask to form first and second contact holes 16 and 24, as shown in FIG. 3C. The first contact hole 16 penetrates the passivation layer 50 to expose the drain electrode 12, and the second contact hole 24 penetrates the passivation layer 50 to expose the storage electrode 22. Is formed.

As the material of the protective film 50, an inorganic insulating material such as the gate insulating film 44 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

The transparent electrode material is entirely deposited on the passivation layer 50 by a deposition method such as sputtering. Subsequently, the transparent electrode material is patched through a photolithography process and an etching process using a mask, thereby forming transparent electrode patterns including the pixel electrode 18 as illustrated in FIG. 3D. The pixel electrode 18 is electrically connected to the drain electrode 12 through the first contact hole 16, and the storage electrode 22 overlapping the front gate line 2 through the second contact hole 24. Electrically connected. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

In the TFT array substrate, the channel is unstable due to interfacial instability between the active layer 14 and the ohmic contact layer 48 and contamination due to the external environment between the formation of the n + amorphous silicon layer and before the formation of the amorphous silicon layer. A problem arises in that the on / off characteristic is deteriorated. In particular, since a leakage current (off current) flowing from the drain electrode 12 to the source electrode 10 is generated, the pixel voltage to the pixel electrode 18 is not uniformly maintained for one frame and normal charging and discharging is not performed. This causes a problem that the display quality is degraded, such as the contrast ratio being lowered and the afterimage appearing.

In addition, in order to form the semiconductor pattern 49 in FIGS. 1 and 2, an n + amorphous silicon layer and an amorphous silicon layer must be formed, respectively, and each of them is etched. In the channel portion, only the n + amorphous silicon layer is selectively etched. There is a problem that the process is complicated and lengthened, such as an additional process.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same, which can improve display quality and simplify the process.

In order to achieve the above object, a thin film transistor array substrate according to the present invention includes a gate line and a data line formed to cross each other with a gate insulating film therebetween; A thin film transistor connected to the data line and driven by a gate voltage from the gate line; The thin film transistor includes a pixel electrode connected to the thin film transistor, and the thin film transistor includes a phase change semiconductor pattern whose electrical characteristics vary according to the magnitude of the gate voltage.

The phase change semiconductor pattern has a low resistivity when a gate high voltage is supplied to the gate line, and a high resistivity when a gate low voltage is supplied to the gate line.

The gate high voltage is a turn-on voltage of the thin film transistor, and the gate low voltage is a turn-off voltage of the thin film transistor.

The phase change semiconductor pattern is composed of a single layer.

The phase change semiconductor pattern includes germanium (Ge), antimony (Sb), and tellurium (Te).

A pixel electrode in contact with the storage electrode through the storage electrode overlapping the gate line with the gate line and the gate insulating layer interposed therebetween, the phase change semiconductor pattern disposed under the storage electrode, and a contact hole exposing the storage electrode. The storage capacitor further comprises.

A method of manufacturing a thin film transistor array substrate according to the present invention includes forming a gate pattern including a gate electrode of a thin film transistor and a gate line connected to the gate electrode on a substrate; Forming a gate insulating film on the gate pattern; A source / drain pattern including a data line connected to the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode is formed on the gate insulating layer, and is positioned below the source / drain pattern. Forming a phase change semiconductor pattern whose electrical characteristics vary depending on the magnitude of the gate voltage supplied to the gate electrode; Forming a protective film having a first contact hole exposing the drain electrode; Forming a pixel electrode in contact with the drain electrode through the first contact hole.

Contacting the storage electrode through the gate line, the storage electrode overlapping the gate line with the gate insulating layer interposed therebetween, the phase change semiconductor pattern positioned below the storage electrode, and a second contact hole exposing the storage electrode. The method may further include forming a storage capacitor including the pixel electrode.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 8D.

4 is a plan view illustrating a TFT array substrate according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the TFT array substrate illustrated in FIG. 4 taken along a line II-II '.

The thin film transistor array substrate illustrated in FIGS. 4 and 5 includes a gate line 102 and a data line 104 formed to intersect on the lower substrate 142 with a gate insulating layer 144 therebetween, and a thin film formed at each intersection thereof. A transistor (Thin Film Transistor) (hereinafter referred to as " TFT ") 106 and a pixel electrode 118 formed in a cell region provided in a cross structure thereof are provided. The TFT array substrate includes a storage capacitor 120 formed at an overlapping portion of the pixel electrode 118 and the previous gate line 102.

The pixel electrode 118 is connected to the drain electrode 112 of the TFT 106 through the first contact hole 116 penetrating the protective film 150. The pixel electrode 118 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage.

The storage capacitor 120 includes the front gate line 102, the storage electrode 122 overlapping the gate line 102, the gate insulating layer 144, and the phase change semiconductor pattern 160 therebetween, and the storage electrode ( The pixel electrode 122 is overlapped with the passivation layer 150 interposed therebetween and connected through the second contact hole 124 formed in the passivation layer 150. The storage capacitor 120 helps to maintain the pixel voltage charged in the pixel electrode 118 until the next pixel voltage is charged.

The TFT 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, a drain electrode 112 connected to the pixel electrode 116, The phase change semiconductor pattern 160 overlaps the gate electrode 108 and forms a channel between the source electrode 110 and the drain electrode 112. The phase change semiconductor pattern 160 improves display quality by minimizing off current.

The phase change semiconductor pattern 160 exhibits electrical characteristics similar to crystalline silicon when the gate high voltage is supplied to the gate electrode 8 and similar characteristics to amorphous silicon when the gate low voltage is supplied to the gate electrode 8. In particular, when the gate low voltage is supplied to the gate electrode 8, the resistance in the phase change semiconductor pattern 160 becomes very high. Accordingly, the on / off characteristic of the thin film transistor 106 can be improved, so that no off current is generated. As a result, charging and discharging to each pixel electrode 18 are normally performed, thereby improving display quality.

Hereinafter, the phase change semiconductor pattern 160 and its effects will be described in more detail with reference to FIGS. 6 to 7.

The phase change semiconductor pattern 160 is a semiconductor material in which germanium (Ge), antimony (Sb), and tellurium (Te) are mixed, and thus have resistance to temperature as shown in FIG. 6.

Curves A, B, and C in FIG. 6 are simulation results showing a change in resistance of a phase-transfer semiconductor material having different mixing ratios of germanium (Ge), antimony (Sb), and tellurium (Te) as the temperature increases. In particular, the temperature in FIG. 6 represents a numerical value proportional to the magnitude of the gate voltage supplied to the gate electrode 108 of the liquid crystal display panel.

Curves A, B, and C are respectively mixed at the ratio of Ge ₁ Sb ₂ Te ₄ , and are mixed at the ratio of Ge ₂ Sb ₂ Te ₅ , and increased at the ratio of Ge ₄ Sb ₁ Te ₅ . The resistance value is shown. It can be seen that the curves A, B, and C in FIG. 6 commonly exhibit high resistance values at low temperatures, whereas low curves are shown at high temperatures. That is, the semiconductor material composed of GeSbTe has a property of showing high resistance at low temperatures and low resistance at high temperatures.

Accordingly, in the present invention, as the channel of the thin film transistor 106 is formed using the semiconductor material composed of GeSbTe, when the gate high voltage is supplied to the gate electrode 108, the electrical properties of the semiconductor material composed of GeSbTe It shows similar characteristics to this crystalline semiconductor. In contrast, when a gate low voltage is supplied to the gate electrode 108, the electrical properties of the semiconductor material composed of GeSbTe exhibit characteristics similar to those of a highly resistive amorphous semiconductor.

The difference between the resistance value of the phase change semiconductor pattern 160 when the gate low voltage is supplied and the resistance value of the phase change semiconductor pattern 160 when the gate high voltage is supplied is 10 ⁶ to 10 ⁷ (Ωcm).

Accordingly, the thin film transistor 106 including the phase change semiconductor pattern 160 made of GeSbTe can maintain the difference in resistance value between switching turn-on and turn-off at about 10 ⁶ to 10 ⁷ (Ωcm). .

7 is a simulation result showing the degree of leakage current generation in the thin film transistor 106 employing the conventional thin film transistor 106 and the phase change semiconductor pattern 160.

In FIG. 7, P2 represents a leakage current in the thin film transistor employing the phase change semiconductor pattern 160, and P1 represents a leakage current in a conventional thin film transistor.

Referring to FIG. 7, at or below a threshold voltage (Vth) of about 2V, the leakage current value of the thin film transistor employing the phase change semiconductor pattern 160 is 0.0004 A or less, but the leakage current value of the conventional thin film transistor is 0.7V. It can be seen that the degree is about 0.0016 A.

That is, since the resistance of the channel is large during turn-off of the thin film transistor, leakage current from the drain electrode 112 to the source electrode 110 can be minimized.

As a result, the pixel voltage to the pixel electrode 18 can be uniformly maintained for one frame and charge and discharge can be normally performed, thereby eliminating afterimages and increasing the contrast ratio, thereby improving display quality.

Hereinafter, a method of manufacturing a TFT array substrate will be described with reference to FIGS. 8A to 8D.

First, a gate metal layer is formed on the lower substrate 142 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a mask to form gate patterns including the gate line 102 and the gate electrode 108, as shown in FIG. 8A. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

The gate insulating layer 144 is formed on the lower substrate 142 on which the gate patterns are formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating film 144, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

On the lower substrate 142 on which the gate insulating layer 144 is formed, a semiconductor layer in which germanium (Ge), antimony (Sb), and tellurium (Te) are mixed and a source / drain metal layer are sequentially formed.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the TFT 106 as a mask, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 104, the source electrode 110, the drain electrode 112 integrated with the source electrode 110, and the storage electrode 122 are formed. Source / drain patterns including are formed.

Next, the phase change semiconductor pattern 160 is formed by patterning the semiconductor layer by an etching process using the same photoresist pattern.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern of the channel portion is etched by a dry etching process. Accordingly, as shown in FIG. 8B, the phase transition semiconductor pattern 165 of the channel portion is exposed and the source electrode 110 and the drain electrode 112 are electrically separated.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process. As the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu), aluminum-based metal and the like are used.

The passivation layer 150 is entirely formed on the gate insulating layer 144 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 150 is patterned by a photolithography process and an etching process using a mask to form first and second contact holes 116 and 124 as shown in FIG. 8C. The first contact hole 116 is formed to pass through the passivation layer 150 to expose the drain electrode 112, and the second contact hole 124 is formed to pass through the passivation layer 150 to expose the storage electrode 122. do.

As the material of the passivation layer 150, an inorganic insulating material such as the gate insulating film 144, an acrylic insulating compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like is used.

The transparent electrode material is deposited on the entire surface of the passivation layer 150 by a deposition method such as sputtering. Subsequently, the transparent electrode material is etched through a photolithography process and an etching process using a mask, thereby forming transparent electrode patterns including the pixel electrode 118 as illustrated in FIG. 8D. The pixel electrode 118 is electrically connected to the drain electrode 112 through the first contact hole 116 and the storage electrode 122 overlapping the front gate line 102 through the second contact hole 124. Electrically connected. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, in the method of manufacturing the thin film transistor array substrate according to the present invention, as the semiconductor pattern is formed as a single layer in the second mask process, the structure and the process may be simplified and the manufacturing cost may be reduced.

As described above, the thin film transistor array substrate and the method of manufacturing the same according to the present invention form a phase-transfer semiconductor pattern whose electrical characteristics vary depending on the gate high voltage and the gate low voltage. Accordingly, the resistance in the channel is large during the period of maintaining the turn-off of the thin film transistor, thereby minimizing leakage current. As a result, the display quality is improved compared to the conventional art, such that afterimages are eliminated and the lowering of the contrast ratio is prevented.

In addition, since the phase-transfer semiconductor pattern is composed of a single layer, the process is simplified and the manufacturing cost can be reduced as compared with the manufacturing process of the conventional double layer semiconductor pattern.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

A gate line and a data line intersecting each other with the gate insulating film interposed therebetween; A thin film transistor connected to the data line and driven by a gate voltage from the gate line; A pixel electrode connected to the thin film transistor, The thin film transistor is A thin film transistor array substrate comprising a phase change semiconductor pattern whose electrical characteristics vary depending on the magnitude of the gate voltage. The method of claim 1, The phase change semiconductor pattern And a resistivity decreases when a gate high voltage is supplied to the gate line, and increases resistivity when a gate low voltage is supplied to the gate line. The method of claim 2, And the gate high voltage is a turn-on voltage of the thin film transistor, and the gate low voltage is a turn-off voltage of the thin film transistor. The method of claim 1, The phase change semiconductor pattern is a thin film transistor array substrate, characterized in that consisting of a single layer. The method of claim 1, The phase transition semiconductor pattern includes germanium (Ge), antimony (Sb), tellurium (Te). The method of claim 1, A pixel electrode in contact with the storage electrode through the gate line, a storage electrode overlapping the gate line with the gate insulating layer interposed therebetween, the phase change semiconductor pattern under the storage electrode, and a contact hole exposing the storage electrode. The thin film transistor array substrate further comprising a storage capacitor. Forming a gate pattern including a gate electrode of the thin film transistor and a gate line connected to the gate electrode on a substrate; Forming a gate insulating film on the gate pattern; A source / drain pattern including a data line connected to the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode is formed on the gate insulating layer, and is positioned below the source / drain pattern. Forming a phase change semiconductor pattern whose electrical characteristics vary depending on the magnitude of the gate voltage supplied to the gate electrode; Forming a protective film having a first contact hole exposing the drain electrode; And forming a pixel electrode in contact with the drain electrode through the first contact hole. The method of claim 7, wherein Contacting the storage electrode through the gate line, the storage electrode overlapping the gate line with the gate insulating layer interposed therebetween, the phase change semiconductor pattern positioned below the storage electrode, and a second contact hole exposing the storage electrode. A method of manufacturing a thin film transistor array substrate, the method comprising: forming a storage capacitor including the pixel electrode. The method of claim 7, wherein The phase change semiconductor pattern The resistivity decreases when the gate high voltage is supplied to the gate electrode, and the resistivity increases when the gate low voltage is supplied to the gate electrode. The method of claim 9, The gate high voltage is a turn-on voltage of the thin film transistor, and the gate low voltage is a turn-off voltage of the thin film transistor. The method of claim 7, wherein The phase change semiconductor pattern is a method of manufacturing a thin film transistor array substrate, characterized in that consisting of a single layer. The method of claim 7, wherein The phase change semiconductor pattern may include germanium (Ge), antimony (Sb), tellurium (Te).

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