KR20080044042A - Flash memory device and method for controlling read operation thereof - Google Patents

Abstract

A flash memory device and a method for controlling read operation thereof are provided to increase current sensing margin of a peripheral current measurement circuit. A semiconductor substrate(110) has a source region(120) and a drain region(130) separated from each other. N channel regions are formed between the source region and the drain region, and are doped with different density. A floating gate(150) is formed on the top of the channel region. A control gate(160) is formed on the top of the floating gate. The N channel regions include a first channel region(140) and a second channel region(145) doped with higher density than the first channel region.

Description

Flash memory device and method for controlling read operation

1 is a view schematically showing the structure of a flash memory device according to an embodiment of the present invention.

FIG. 2A is a vertical sectional view showing one side of the flash memory device of FIG.

FIG. 2B is a vertical sectional view showing the other side of the flash memory device of FIG.

3 is a diagram illustrating an example of a first gate voltage and a second gate voltage applied to a flash memory device of the present invention.

4A illustrates the presence or absence of channel formation upon application of a first gate voltage in a first programming state in which charge is charged to a floating gate by a first amount of charge.

4B illustrates the presence or absence of channel formation upon application of a second gate voltage in a first programming state in which charge is charged to a floating gate by a first amount of charge.

4C is a graph illustrating the relationship between the gate voltage applied in the first programming state of FIGS. 4A and 4B and the measured drain current.

5A illustrates the presence or absence of channel formation upon application of a first gate voltage in a second programming state in which charge is charged to a floating gate by a second amount of charge.

5B illustrates the presence or absence of channel formation upon application of a second gate voltage in a second programming state in which charge is charged to a floating gate by a second amount of charge.

5C is a graph illustrating the relationship between the applied gate voltage and the measured drain current in the second programming state of FIGS. 5A and 5B.

6A illustrates the presence or absence of channel formation upon application of a first gate voltage in a third programming state in which charge is charged to a floating gate by a third amount of charge.

6B illustrates the presence or absence of channel formation upon application of a second gate voltage in a third programming state in which charge is charged to a floating gate by a third amount of charge.

6C is a graph illustrating the relationship between the applied gate voltage and the measured drain current in the third programming state of FIGS. 6A and 6B.

FIG. 7A illustrates the presence or absence of channel formation upon application of a first gate voltage in a fourth programming state in which charge is charged to a floating gate by a fourth amount of charge.

FIG. 7B illustrates the presence or absence of channel formation upon application of a second gate voltage in a fourth programming state in which charge is charged to a floating gate by a fourth amount of charge.

FIG. 7C is a graph illustrating the relationship between the gate voltage applied and the measured drain current in the fourth programming state of FIGS. 7A and 7B.

8A illustrates the presence or absence of channel formation upon application of a first gate voltage in a fifth programming state in which charge is charged to a floating gate by a fifth amount of charge.

8B illustrates the presence or absence of channel formation upon application of a second gate voltage in a fifth programming state in which charge is charged to a floating gate by a fifth amount of charge.

FIG. 8C is a graph illustrating the relationship between the gate voltage applied and the measured drain current in the fifth programming state of FIGS. 8A and 8B.

<Description of the symbols for the main parts of the drawings>

110: semiconductor substrate 120: source region

130: drain region 140: first channel region

145: second channel region 150: floating gate

160: control gate

The present invention relates to a flash memory device, and more particularly, to a flash memory device having a multi-channel structure, each having a different doping concentration, and a read operation control method in such a flash memory device.

The flash memory device is a memory device having low power consumption and a characteristic in which stored information does not disappear even when the power is turned off. Therefore, unlike DRAM, it not only preserves stored information even when power is cut off, but also frees input / output (write, erase and read) of information, which is widely used in digital televisions, digital camcorders, digital cameras, mobile phones, and MP3 players. It is used.

The flash memory device further includes a floating gate capable of accumulating charge in a general MOS transistor structure. Flash memory devices are divided into single level flash memory devices that can only program level '0' or level '1' and multiple level flash memory devices that can program more levels. For example, in a multilevel flash memory device having a data bit of 2, four levels of '00', '01', '10', and '11' can be programmed corresponding to the amount of charge accumulated in the floating gate. In such a multilevel flash memory device, the identification (reading) of each level (that is, the programming state of the device) corresponding to the amount of charge accumulated in the floating gate is performed by applying a voltage having a different magnitude to the control gate of the flash memory device. The method of applying several times is used.

In this case, in a multi-level flash memory device having a single channel, a voltage sensing method and a current sensing method are used as a method for identifying each level. However, in the case of using the voltage measurement method in a multi-level flash memory device having a single channel, there is a problem in that a large number of voltages must be applied to the control gate to check each level. For example, in a two-bit multilevel flash memory with a single channel, at least three different voltages are required to distinguish each of the four levels. This is because in order to distinguish the four levels, the device must have four types of channel formation distinguished according to the applied voltage. That is, in a multilevel flash memory device having a single channel, four distinct channel formation types are required only when three different voltages are applied to the control gate three times, one at a time (when a channel is formed at all applied voltages). , The channel is formed only at any two applied voltages, the channel is formed only at one applied voltage, and the channel is not formed at all applied voltages). Four levels can be distinguished. Accordingly, in the case of the M-bit multi-level flash memory device having a single channel, a total of 2 ^M in order to distinguish a total of 2 ^M of the level - to be applied to a single respective different voltages to the control gate. As a result, a multilevel flash memory device having a single channel has a problem in that the read speed is slow because a lot of time is required to read each level (programming state) of the device.

In addition, in the case of using the current measurement method in a multi-level flash memory device having a single channel, the difference in the amount of current flowing in each case is increased by increasing the difference in the amount of charge stored in the floating gate in order to increase the current sensing margin. There is a problem that a large or high performance current measurement circuit is required. In particular, in the case of using a high-performance current measurement circuit, there is a problem in that power consumption increases or operation speed becomes slow.

Accordingly, an aspect of the present invention is to provide a flash memory device having a multi-channel structure having a different doping concentration and a read operation control method in the flash memory device.

In addition, the present invention can reduce the read operation time and the program check time of the device through a multi-channel structure, the flash memory device and the flash memory device that can increase the current sensing margin (current sensing margin) of the current measuring circuit around the device To provide a read operation control method in.

Other objects of the present invention will be readily understood through the following description.

According to an aspect of the invention, a semiconductor substrate having a source region and a drain region formed spaced apart from each other; N channel regions (N is a natural number of two or more) formed between the source region and the drain region, each doped at different concentrations; A floating gate formed over the channel region; And a control gate formed on the floating gate.

Here, the N channel regions may be formed as two channel regions of the first channel region and the second channel region doped at a higher concentration than the first channel region.

Here, the semiconductor substrate may be a doped semiconductor substrate, and any one channel region of the N channel regions may be formed as a predetermined region of the doped semiconductor substrate.

Here, the N channel regions may be formed in the length direction connecting the source region and the drain region, respectively.

According to another aspect of the present invention, a semiconductor substrate having a source region and a drain region, a first channel region formed between the source region and the drain region, and a second channel region, a floating gate and a control doped to a higher concentration than the first channel region A method of controlling a read operation of a flash memory device for controlling a read operation in a flash memory device including a gate, the method comprising: a gate voltage applied to a control gate, a threshold voltage V _THL of a first channel region, and a second channel region; A method of controlling a read operation of a flash memory device may be provided that compares threshold voltages V _THH to determine a programming state corresponding to an amount of charge accumulated in a floating gate.

Here, the gate voltage applied to the control gate may use the first gate voltage V ₁ and the second gate voltage V _{2 that} is higher than the first gate voltage. In this case, the first gate voltage V ₁ and the second gate voltage V ₂ may be determined to satisfy values of inequalities 1 to 5 below.

Inequality 1

V ₁ 〉 V _THH1

Inequality 2

V _THL2 <V ₁ <V _THH2 <V ₂

Inequality 3

V ₁ <V _THL3 <V _THH3 <V ₂

Inequality 4

V ₁ <V _THL4 <V ₂ <V _THH4

Inequality 5

V ₂ 〈V _THL5

Here, V _THH1 is the threshold voltage of the second channel region in the first programming state in which the charge is charged in the floating gate by the first amount of charge, and V _THL2 and V _THH2 are the second in which the charge is charged in the floating gate by the second amount of charge. Threshold voltages of the first channel region and the second channel region in the programming state, and V _THL3 and V _THH3 are the first channel region and the second channel in the third programming state in which the floating gate is charged with a third amount of charge. Respective threshold voltages of the channel region, and V _THL4 and V _THH4 are the respective threshold voltages of the first channel region and the second channel region in the fourth programming state in which the floating gate is charged with the fourth amount of charge, and V _THH5 Is the threshold voltage of the first channel region in the fifth programming state in which charge is charged in the floating gate by the fifth charge amount.

In addition, in the read operation control method of the flash memory device of the present invention, the programming state is the first drain current (I _D1 ) and the second gate voltage measured in the drain region as the first gate voltage (V ₁ ) is applied. As (V ₂ ) is applied, the second drain current I _D2 measured in the drain region may be determined by comparing the first reference current I _REF1 and the second reference current I _REF2 , respectively.

Here, the first drain current I _D1 is the current I _CH1 flowing through the first channel region measured in the drain region and the current I _CH2 flowing through the second channel region as the first gate voltage V ₁ is applied. ), And the second drain current I _D2 is a current I _CH1 flowing through the first channel region measured in the drain region as the second gate voltage V ₂ is applied, and a current flowing through the second channel region. Is the sum of (I _CH2 ).

Here, the comparison between the first drain current I _D1 and the second drain current I _D2 and the first reference current I _REF1 and the second reference current I _REF2 is performed using the following inequality 6 to inequality 10, The first programming state to the fifth programming state may be set to correspond one-to-one with the following inequality 6 to inequality 10.

Inequality 6

When first gate voltage is applied: I _D1 〉 I _REF1 , I _D1 〉 I _REF2

When applying the second gate voltage: I _D2 〉 I _REF1, I _D2 〉 I _REF2

Inequality 7

When the first gate voltage is applied: I _D1 <I _REF1 , I _D1 > I _REF2

When applying the second gate voltage: I _D2 〉 I _REF1, I _D2 〉 I _REF2

Inequality 8

When applying the first gate voltage: I _D1 <I _REF1 , I _D1 ≤ I _REF2

When applying the second gate voltage: I _D2 〉 I _REF1, I _D2 〉 I _REF2

Inequality 9

When applying the first gate voltage: I _D1 <I _REF1 , I _D1 ≤ I _REF2

When applying the second gate voltage: I _D2 <I _REF1 , I _D2 > I _REF2

Inequality 10

When applying the first gate voltage: I _D1 <I _REF1 , I _D1 ≤ I _REF2

When applying the second gate voltage: I _D1 <I _REF1 , I _D2 ≤ I _REF2

In this case, the second reference current I _REF2 may be set to 0 or a predetermined current value corresponding thereto, and the first reference current I _REF1 may be set such that the above inequalities 6 to 10 are satisfied. That is, the first reference current I _REF1 has the first _reference current I _D1 and the second drain current I _D2 when the current flows in the first channel region and the second channel region, respectively. If greater than I _REF1 and current flows only in the first channel region, the first drain current I _D1 and the second drain current I _D2 are greater than the second reference current I _REF2, respectively, and the first reference current. It may be set to be smaller than (I _REF1 ).

Here, any four programming states of the first to fifth programming states may correspond one-to-one with one of the levels '00', '01', '10', and '11'.

Hereinafter, a flash memory device and a read operation control method thereof according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings, wherein the same or corresponding elements are designated by the same reference numerals regardless of the reference numerals. Duplicate explanations will be omitted. In describing the present invention, when it is determined that the detailed description of the related well-known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a view schematically showing the structure of a flash memory device according to an embodiment of the present invention, Figure 2a is a vertical cross-sectional view showing one side of the flash memory device of Figure 1, Figure 2b is a flash memory of Figure 1 Vertical cross-sectional view showing the other side of the device. 2A illustrates a vertical cross section based on the line AA ′ of FIG. 1, and FIG. 2B illustrates a vertical cross section based on the line BB ′ of FIG. 1.

In all the drawings below, a flash memory device having two channel regions as shown in FIG. 1 will be described. However, the flash memory devices according to the present invention each have a total N doped at different concentrations (N is a natural number of 2 or more). Flash memory device having N channel areas may be easily derived from the following detailed description. In addition, the present invention can be applied regardless of its type, such as a NAND flash memory and a NOR flash memory.

Referring to FIG. 1, a flash memory device of the present invention may include a semiconductor substrate 110 having a source region 120 and a drain region 130, and a first channel region formed between the source region 120 and the drain region 130. 140 and the second channel region 145, the floating gate 150, and the control gate 160. In addition, although not separately illustrated in FIG. 1, the flash memory device of the present invention includes a source electrode formed on the source region 120, a drain electrode formed on the drain region 130, and first and second channel regions 140. Of course, the tunnel oxide film formed between the 145 and the floating gate 150, the gate insulating film formed between the floating gate 150 and the control gate 160 may be further included.

The source region 120 and the drain region 130 are formed to be spaced apart from each other in one region on both sides of the semiconductor substrate 110. For example, when a P-type substrate is used as the semiconductor substrate 110, an N-type is formed by doping a region on both sides of the semiconductor substrate 110 with a Group 5 element (for example, arsenic (As) or the like). Source and drain regions 120 and 130 are formed. In addition, it is apparent that the P-type source region 120 and the drain region 130 may be formed using Group III elements (eg, boron (B), etc.) in one region on both sides of the N-type substrate.

The first channel region 140 and the second channel region 145 are doped with each other in a region (hereinafter, referred to as an intermediate region) between the source region 120 and the drain region 130 formed in the semiconductor substrate 110. It is formed by varying the concentration. As such, in order to form two channel regions, a method of doping the portions in which the first channel region 140 and the second channel region 145 are to be formed with different concentrations may be used. When the semiconductor substrate 110 is used, one of the two channel regions does not need to be doped separately.

That is, when a substrate doped with an impurity is used as the semiconductor substrate 110, the channel capable of moving electrons may be formed in a predetermined region of the semiconductor substrate 110 according to a voltage applied to the device. The channel region of does not need to be formed separately. Therefore, in this case, there is an advantage in the device fabrication process capable of forming each of the two channel regions with only one separate doping treatment. For example, assuming that the second channel region 145 is doped to a higher concentration than the first channel region 140 (hereinafter, referred to as this), the first channel region 140 is doped without a separate doping treatment. The second channel region 145 may be directly implemented by the semiconductor substrate 110, and the second channel region 145 having a high concentration may be added by only one doping treatment for additionally injecting impurities into one region (part of the intermediate region) of the semiconductor substrate 110. ) Can be formed.

As described above, when the first channel region 140 is formed without a separate doping process, the first channel region 140 is only one region of the semiconductor substrate 110 having no difference from the semiconductor substrate 110 in terms of physical properties. However, in all the drawings below FIG. 1, the semiconductor is emphasized that the first channel region 140 is a region capable of forming a channel through which electrons can move according to a voltage applied to the device, similarly to the second channel region 145. It is clearly illustrated as the substrate 110.

In addition, the first channel region 140 and the second channel region 145 may be longitudinally connected to each other so as to enable connection between the source region 120 and the drain region 130 as illustrated in FIGS. 2A and 2B. A-A 'direction and B-B' direction of 1) are preferable. In the flash memory device according to the present invention, in order to check (read) the programming state (level) of the device using only two applied voltages, in the first channel region 140 and the second channel region 145 according to the applied voltage. This is because channels must be formed independently of each other. For example, although a channel is not formed in the first channel region 140 according to the application of a specific voltage, a channel capable of moving electrons is formed in the second channel region 145 so that the drain region 130 is formed from the source region 120. There must be a current flowing in the) direction. To this end, the first channel region 140 and the second channel region 145 may be formed to enable connection between the source region 120 and the drain region 130, respectively.

The floating gate 150 is formed on the first channel region 140 and the second channel region 140 to serve as an accumulation (storage) space of the charge in the flash memory device, and the control gate 160 is a flash. It controls the specific operations (write, erase and read) of the memory device. The control principle of write and erase operations in the flash memory device will be briefly described to help understand the role of the floating gate 150 and the control gate 160. The principle of controlling the read operation in the flash memory device will be described in more detail later with reference to FIGS. 3 to 8C.

Write operation control methods in flash memory devices include Hot Electron Injection (Nor Flash memory) and FN Tunneling (Fowler-Nordheim tunneling). In the case of erasing control, a Fowler-Nordheim tunneling method is commonly used. Here, in the Hot Electron Injection method, for example, when a voltage of 10 V is applied to the control gate 160 and 5 V to the drain region 130, a high electric field is formed between the channel and the control gate 160. The electrons moving from the source region 120 to the drain region 130 through the channel flow into the floating gate 150 by the high electric field, thereby performing a write operation. In addition, FN tunneling (Fowler-Nordheim tunneling) method is moving through a channel by applying a positive voltage to the control gate 160 and a negative voltage to the semiconductor substrate 110 by using a quantum mechanical tunneling phenomenon As the electrons flow into the floating gate 150, a write operation is performed. On the contrary, charges accumulated by applying a negative voltage to the control gate 160 and a positive voltage to the semiconductor substrate 110 are stored in the floating gate 150. The erase operation is performed by leaking from the. As such, the write and erase operations in the flash memory device are the same as the inflow and outflow of charges in the floating gate 150, which is controlled by the voltage applied to the control gate 160.

3 is a diagram illustrating an example of a first gate voltage and a second gate voltage applied to a flash memory device of the present invention.

Referring to FIG. 3, two gate voltages V _G , each having a different magnitude, are illustrated. Here, the gate voltage V _G refers to a voltage applied between the control gate 160 and the semiconductor substrate 110. In the following description, the second gate voltage V ₂ of the two gate voltages V _G is described. As shown in FIG. 3, it is assumed that the voltage is higher than the first gate voltage V ₁ .

The flash memory device having a multi-channel according to the present invention is a combination of a voltage measurement method and a current measurement method, and can control a read operation by using two gate voltages V _G having different magnitudes. That is, the read operation in the device is performed only by applying the first gate voltage V ₁ and the second gate voltage V ₂ to the control gate 160 twice, each time (see reference numeral T in FIG. 3). Control is possible. Therefore, the multi-channel flash memory device according to the present invention has a shorter time required for a read operation than the multi-level flash memory device having a single channel. For example, in the case of a flash memory device having a single channel, at least three or more different voltages must be applied to each other in order to distinguish four or more levels. In this case, the read time can be reduced by at least one cycle than in the case of using a single channel.

In addition, the current sensing margin in the device is increased because the amount of current flowing through the device is expressed as the sum of the currents flowing in each state when the current measuring method is used together. Therefore, in the case of a flash memory device having a multi-channel according to the present invention, since the amount of current flowing through the device shows a large difference in each state, unlike the flash memory device having a single channel, the difference in the amount of current flowing in each state is increased or There is an advantage that it is not necessary to have a high performance current measurement circuit.

Hereinafter, a method of controlling a read operation using two gate voltages V _G in a multi-channel flash memory device will be described in detail with reference to FIGS. 4A to 8C. To help understand, the following terms will be introduced first.

As the drain current I _D is applied with the gate voltage V _G to the device, a channel capable of moving electrons is formed in both the first channel region 140 and the second channel region 145 or any one channel region. This means a current flowing from the source region 120 toward the drain region 130. In other words, the drain current I _D is formed by the first channel current I _CH1 and the second channel region flowing through the channel formed in the first channel region 140 as the gate voltage V _G is applied to the device. It is equal to the sum of the second channel current I _CH2 flowing through the channel formed in 145 (ie, I _D = I _CH1 + I _CH2 ).

In this case, as the first gate voltage V ₁ is applied to the device, the drain current I _D flowing through the channel is referred to as the first drain current I _D1 , and as the second gate voltage V ₂ is applied. The drain current I _D flowing through the channel is called a second drain current I _D2 .

In addition, as a specific gate voltage V _G is applied in an arbitrary programming state, a channel current flowing through a channel formed in a specific channel region is expressed as follows. Here, the programming state is determined (divided) by the amount of charge stored in the floating gate 150. For example, I _{CH1 (2, 3)} is the first channel current I _CH1 flowing through a channel formed in the first channel region 140 as the second gate voltage V ₂ is applied in the third programming state. Means. That is, the first number in parentheses identifies the applied gate voltage (V _G ) and the second number identifies the programming state of the device.

In addition, the threshold voltage (V _TH ) (Threshold voltage) means a minimum voltage for forming a channel in the device according to the gate voltage (V _G ) is applied. That is, the threshold voltage V _TH is equal to the magnitude of the applied gate voltage V _G when current starts to flow as a channel is formed in the device. The threshold voltage VTH varies depending on the doping concentration of the channel region and the amount of charge accumulated in the floating gate 150. In general, the threshold voltage V _TH increases as the impurity doping concentration in the channel region increases, and as the amount of charge accumulated in the floating gate 150 increases.

In this case, the threshold voltage V _TH of the first channel region 140 is referred to as the first threshold voltage V _THL , and the threshold voltage V _TH of the second channel region 145 is referred to as the second threshold voltage V _THH. It is called). Here, since the second channel region 145 is doped at a higher concentration than the first channel region 140, the second threshold voltage V _THH has a value greater than the first threshold voltage V _HTL .

4A is a diagram illustrating the presence or absence of channel formation upon application of a first gate voltage in a first programming state in which charge is charged to a floating gate by a first charge amount, and FIG. 4B is a charge in the floating gate by a first charge amount. 4A and 4B illustrate the relationship between the gate voltage applied in the first programming state of FIGS. 4A and 4B and the measured drain current. One graph. In the present exemplary embodiment, the programming state of the device when the charge is charged to the floating gate 150 by the first charge amount Q ₁ is described by way of example, but the charge is charged to the floating gate 150. Of course, the initial state of the device that is not present can be used as the first programming state.

Referring to FIG. 4A, as the first gate voltage V ₁ is applied to the control gate 160, a channel is formed in both the first channel region 140 and the second channel region 145. That is, in the first programming state in which a charge equal to the first charge amount Q ₁ is charged in the floating gate 150, the first gate voltage V ₁ is applied to flow through the first channel region 140. 1 channel current I _{CH1 (1,1)} (see identification (a) of FIG. 4A) and second channel current I _{CH2 (1,1)} flowing through second channel region 145 (FIG. 4A (B)) are all present.

In addition, referring to FIG. 4B, in the flash memory device of the present invention, as the second gate voltage V ₂ is applied to the control gate 160 in the first programming state, the first channel region 140 and the second channel region ( 145) channels are formed in all. That is, the first channel current I _{CH1 (2, 1)} flowing through the first channel region 140 ₍ see identification code (c) of FIG. 4B) and the second channel flowing through the second channel region 145. The current I _{CH2 (2,1)} (see identification code (d) in FIG. 4B) is all present.

When the first gate voltage V ₁ or the second gate voltage V ₂ is applied in the first programming state, channel formation between the first channel region 140 and the second channel region 145 is performed through FIG. 4C. It can be explained more clearly.

Referring to FIG. 4C, two straight lines illustrating the relationship between the gate voltage V _G applied in the first programming state and the drain current I _D flowing through the channel are illustrated. Both straight lines have a predetermined slope and are formed for each channel region. The first straight line 11 has a gate voltage V _G and a drain current in the first channel region 140 in a first programming state. (I _D) with the relationship between the second straight line 21 is representative of the relationship between the first gate voltage (V _G) and the drain current (I _D) of the second channel section 145 in the programmed state.

In this case, the first straight line 11 and the second straight line 21 are respectively the threshold voltage V _THL1 of the first channel region 140 in the first programming state and the second channel region 145 in the first programming state. Is started from the threshold voltage (V _THH1 ). Because a channel is formed in each of the first channel region 140 and the second channel region 145 so that the channel current flows, the gate voltage V _G is applied to the first threshold voltage V _THL1 and the second threshold, respectively. This is because it must have a value larger than the voltage V _THH1 .

Therefore, as shown in FIG. 4C, when the first gate voltage V ₁ is set to a value greater than the first threshold voltage V _THL1 and the second threshold voltage V _THH1 , the first channel as shown in FIG. 4A. The channel may be controlled to be formed in both the region 140 and the second channel region 145. In this case, since the second gate voltage V ₂ has a larger value than the first gate voltage V ₁ , even when the second gate voltage V ₂ is applied, the first channel region 140 as shown in FIG. 4B. And a channel is formed in both the second channel region 145.

That is, when the relation of the following inequality 1 is established between the first gate voltage V ₁ and the second threshold voltage V _THH1 , a channel having a shape as shown in FIGS. 4A and 4B (hereinafter, referred to as a first channel shape). Is formed.

[Inequality 1] V ₁ 〉 V _THH1

After all, this means that when the voltage satisfying the above inequality 1 is selected as the first gate voltage V ₁ , it is possible to control the first channel shape to be formed in the flash memory device of the present invention.

Here, the following inequality 2 may be used to determine whether the first channel form is formed.

[Inequality 2] I _D1 〉 I _REF1 , I _D2 〉 I _REF1

Here, the first drain current I _D1 in the first programming state is the first flowing through the channel formed in the first channel region 140 as the first gate voltage V ₁ is applied to the device as described above. The sum of the channel current I _{CH1 (1,1)} and the second channel current I _{CH2 (1,1)} flowing through the channel formed in the second channel region 145 (that is, I _D1 = I _{CH1 (1 , 1)} + I _{CH2 (1,1)} ). In addition, the second drain current I _D2 in the first programming state is the first channel current flowing through the channel formed in the first channel region 140 as the second gate voltage V ₂ is applied to the device. I _{CH1 (2,1))} and a second channel region (second channel current (I _{CH2 (2,1} flowing through a channel formed in _145)), the sum (that _{is, I D2 = I CH1 (2,1} ) of a) + I _{CH2 (2,1)} ).

That is, the first drain current I _D1 and the second gate voltage V ₂ measured in the drain region 130 when the first gate voltage V ₁ is applied are measured in the drain region 130. When the second drain current I _D2 has a value larger than the first reference current I _REF1 , it may be determined that the first channel shape is formed in the device.

As described above, the relation of inequality 2 holds when the first channel shape is formed in the device.

First, referring to FIG. 4C, when the first gate voltage V ₁ is applied, the first gate voltage V ₁ may correspond to the threshold voltage V _THL1 and the first voltage of the first channel region 140 in the first programming state. Since the threshold voltage V _THH1 of the two-channel region 145 is greater than the threshold voltage V _THH1 , the first channel current I _{CH1 (1} ) through each channel corresponds to the first straight line 11 and the second straight line 12, respectively. ₁₎ and the second channel current I _{CH2 (1,1)} flow, respectively. That is, when the first gate voltage V ₁ is applied in the first programming state, a channel is formed in both the first channel region 140 and the second channel region 145 as shown in FIG. 4A. .

In this case, the sum of the first channel current I _{CH1 (1, 1} ) and the second channel current I _CH 2 _{(1, 1)} flowing through each channel as the first gate voltage V ₁ is applied ( That is, it can be seen that the first drain current I _D1 has a larger value than the first reference current I _REF1 . In other words, the first reference current I _REF1 is formed when a channel is formed in both the first channel region 140 and the second channel region 145 as the first gate voltage V ₁ is applied. It means that it is set to have a value smaller than the first drain current (I _D1 ) flowing through each channel.

Next, Fig. Referring to the second gate voltage (V ₂₎ when an applied in 4c, the second gate voltage (V ₂₎ is also the threshold voltage of the first channel section (140) (V _THL1) and the second channel section (145 Since the threshold voltage V _THH1 is greater than the threshold voltage V _THH1 , the first channel current I _{CH1 (2, 1} ) and the second channel current correspond to the first straight line 11 and the second straight line 12, respectively. (I _{CH2 (2,1)} ) flows. That is, when the second gate voltage V ₂ is applied in the first programming state, a channel is formed in both the first channel region 140 and the second channel region 145 as shown in FIG. 4B. , The second drain current I _D2 (that is, the sum of the first channel current I _{CH1 (2,1} ) and the second channel current I _{CH2 (2,1)} ) is the first reference current I _REF1. It can be seen that the value is greater than).

As described above, the first drain current I _D1 and the second drain current I _D2 in the first programming state have a larger value than the first reference current I _REF1 , respectively, and this relationship (Inequality 2) This allows the programming state of the flash memory device to be determined (read). That is, when the inequality 2 is established between the first drain current I _D1 , the second drain current I _D2 , and the first reference current I _REF1 , the flash memory device of the present invention may enter the first programming state ( That is, it may be determined that the charge is charged in the floating gate 150 by the first charge amount Q ₁ .

FIG. 5A is a diagram illustrating the presence or absence of channel formation upon application of a first gate voltage in a second programming state in which charge is charged in a floating gate by a second charge amount, and FIG. 5B is in which charge is charged in a floating gate by a second charge amount. 5A and 5B illustrate a relationship between the gate voltage applied in the second programming state of FIG. 5A and FIG. 5B and the measured drain current. One graph. In other words, FIGS. 5A to 5C are in a state in which the floating gate 150 of the flash memory device of the present invention is charged with a second charge amount Q ₂ (hereinafter, referred to as a second programming state). To illustrate.

Referring to FIG. 5A, as the first gate voltage V ₁ is applied to the control gate 160, a channel is formed only in the first channel region 140. That is, in the second programming state in which a charge equal to the second charge amount Q ₂ is charged to the floating gate 150, the first gate voltage V ₁ is applied to flow through the first channel region 140. Only one channel current I _{CH1 (1, 2)} is present (see identification (e) in FIG. 5A), and no current flows through the second channel region 145.

Referring to FIG. 5B, as the second gate voltage V ₂ is applied to the control gate 160, a channel is formed in both the first channel region 140 and the second channel region 145. That is, in the second programming state, as the second gate voltage V ₂ is applied, the first channel current I _{CH1 (2, 2)} flowing through the first channel region 140 (identification code f of FIG. 5B). ) And the second channel current I _{CH2 (2, 2)} flowing through the second channel region 145 ₍ see identification symbol (g) of FIG. 5B).

When the first gate voltage V ₁ or the second gate voltage V ₂ is applied in the second programming state, channel formation between the first channel region 140 and the second channel region 145 is performed through FIG. 5C. It can be explained more clearly.

Referring to FIG. 5C, two straight lines illustrating the relationship between the gate voltage V _G applied in the second programming state and the drain current I _D flowing through the channel are illustrated. Here, the third straight line 12 is a relationship between the gate voltage V _G and the drain current I _D in the first channel region 140 in the second programming state, and the fourth straight line 22 is the second In the programming state, the relationship between the gate voltage V _G and the drain current I _D in the second channel region 145 is represented. At this time, the second programmed state the threshold voltage (V _THL2) of the first channel section 140 in having a large value, the threshold voltage (V _THL1) of the first channel region 140 in the first programmed state beam, The threshold voltage V _THH2 of the second channel region 145 in the second programming state has a value greater than the threshold voltage V _THH1 of the second channel region 140 in the first programming state. This is because the threshold voltage V _TH of each channel region gradually increases as the amount of charge accumulated in the floating gate 150 increases. Here, it is assumed that the second charge amount Q ₂ corresponding to the second programming state is greater than the first charge amount Q ₁ corresponding to the first program state.

In addition, the threshold voltage V _THL2 of the first channel region 140 and the threshold voltage of the second channel region 145 in the first and second gate voltages V ₁ and V ₂ and the second programming state. The relationship as shown in the following inequality 3 holds between the voltages V _THH2 .

Inequality 3 V _THL2 <V ₁ <V _THH2 <V ₂

Therefore, when the second programming state in which the first gate voltage (V ₁₎ in applying a first gate voltage (V ₁₎ is large, the second channel section than the threshold voltage (V _THL2) of a first channel region (140 and 145 Since the channel is smaller than the threshold voltage V _{THH2 of} FIG. 5, a channel is formed in the first channel region 140 as shown in FIG. 5A, but no channel is formed in the second channel region 145.

Second programmed state at the second gate voltage if (V ₂₎ which is applied to the second gate voltage (V ₂₎ is the first channel section 140, the threshold voltage (V _THL2) and the second channel section 145 of the Since the threshold voltage V _THH2 is greater than the threshold voltage, a channel is formed in both the first channel region 140 and the second channel region 145 as shown in FIG. 5B.

That is, the threshold of the first gate voltage (V ₁₎ and a second gate voltage (V ₂₎ and a second programmed state first channel section 140, the threshold voltage (V _THL2) and the second channel section 145 of the in When the relationship as shown in the above inequality 3 is established between the voltage V _THH2 , a channel having a shape as shown in FIGS. 5A and 5B (hereinafter, referred to as a second channel shape) is formed. This means that when the voltage satisfying the above inequality 3 is selected as the first gate voltage V ₁ and the second gate voltage V ₂ , it is possible to control the formation of the second channel shape in the flash memory device of the present invention. it means.

Here, the following inequality 4 may be used to determine whether the second channel form is formed.

[Inequality 4] I _D2 〉 I _REF1 〉 I _D1 〉 I _REF2

That is, when the first gate voltage V ₁ is applied in the second programming state, the drain region 130 when the first drain current I _D1 and the second gate voltage V ₂ measured in the drain region 130 are applied. When the second drain current I _D2 measured at 130 satisfies the above inequality 4, it may be determined that the second channel shape is formed in the device.

As described above, in the case where the second channel shape is formed in the device, the relation of inequality 4 holds in more detail below.

First, a case in which the first gate voltage V ₁ is applied in FIG. 5C will be described. As the first gate voltage V ₁ is applied, the first channel current I _{CH1 (1, 2)} flows through the first channel region 140 corresponding to the third straight line 12. At this time, since no current flows through the second channel region 145, the first channel current I _{CH1 (1,} 2) becomes the first drain current I _D1 in the second programming state. Therefore, the first drain current I _D1 has a value larger than the second reference current I _REF2 and smaller than the first reference current I _REF1 .

Here, as described above, the first reference current I _REF1 has a drain current I when a channel is formed in both the first channel region 140 and the second channel region 145 so that current flows through each channel. It is preferable to set to a value smaller than _D ). In addition, the second reference current I _REF2 is a value when no drain current I _D flows through each channel because no channel is formed in both the first channel region 140 and the second channel region 145. Can be set. Therefore, the second reference current I _REF2 will preferably be 0, but in consideration of the leakage current that may occur in the device, the predetermined offset value of the peripheral current measuring circuit or the peripheral current measuring circuit It may be set to a predetermined current value that can be recognized and operated as a value of zero at the design stage.

Thus, if the measured drain current (I _D) having a value less than the second reference current (I _REF2), it means that it is not formed in the both two of the channel region, and greater than the second reference current (I _REF2) When the value is smaller than the first reference current I _REF1 , it means that a channel is formed only in one of two channel regions (the first channel region 140 having a low doping concentration in this embodiment). In the case of having a value larger than the first reference current I _REF1 , this means that a channel is formed in both channel regions.

Next, a case in which the second gate voltage V ₂ is applied in FIG. 5C will be described. As the second gate voltage V ₂ is applied, the first channel current I _{CH1 (2,} 2) and the second channel current I _CH2 corresponding to the third straight line 12 and the fourth straight line 22, respectively. _{(2, 2)} flows through the first channel region 140 and the second channel region 145, respectively. Therefore, in this case, the second drain current I _D2 (that is, I _{CH1 (2,2)} + I _{CH2 (2,2)} ) has a larger value than the first reference current I _REF1 .

Accordingly, when the first drain current I _D1 and the second drain current I _D2 satisfy the above inequality 4, the first drain current I _D1 and the second drain current I _D2 have a second channel shape as shown in FIGS. 5A and 5B. It is possible to determine (read) that the flash memory device of the present invention is in a second programming state (that is, a state in which a charge corresponding to the second charge amount Q ₂ is accumulated in the floating gate 150).

FIG. 6A is a diagram illustrating the presence or absence of channel formation when the first gate voltage is applied in the third programming state in which the charge is charged to the floating gate by the third charge amount, and FIG. 6B is a charge in the floating gate that is charged by the third charge amount. 6A and 6B illustrate a relationship between the gate voltage applied in the third programming state of FIG. 6A and FIG. 6B and the measured drain current. FIG. One graph. In other words, FIGS. 6A to 6C are in a state where a charge equal to the third charge amount Q ₃ is charged to the floating gate 150 of the flash memory device of the present invention (hereinafter, referred to as a third programming state). To illustrate.

Referring to FIG. 6A, when the first gate voltage V ₁ is applied to the control gate 160 in the third programming state in which the floating gate 150 is charged with the third charge amount Q ₃ , the first gate voltage V ₁ is applied. Channels are not formed in both the first channel region 140 and the second channel region 145.

Referring to FIG. 6B, as the second gate voltage V ₂ is applied to the control gate 160 in the third programming state, a channel is formed in both the first channel region 140 and the second channel region 145. have. That is, in the third programming state, as the second gate voltage V ₂ is applied, the first channel current I _{CH1 (2, 3)} flowing through the first channel region 140 (identification code (h) of FIG. 6B). ) And the second channel current I _{CH2 (2, 3)} flowing through the second channel region 145 ₍ see identification symbol (i) of FIG. 6B).

When the first gate voltage V ₁ or the second gate voltage V ₂ is applied in the third programming state, channel formation between the first channel region 140 and the second channel region 145 is performed through FIG. 6C. It can be explained more clearly.

Referring to FIG. 6C, the fifth straight line 13 represents the relationship between the gate voltage V _G and the drain current I _D in the first channel region 140 in the third programming state. ) Represents the relationship between the gate voltage V _G and the drain current I _D in the second channel region 145 in the third programming state. In this case, the threshold voltage V _THL3 of the first channel region 140 in the third programming state is greater than the threshold voltage V _THL2 of the first channel region 140 in the second programming state. The threshold voltage V _THH3 of the second channel region 145 in the third programming state has a value greater than the threshold voltage V _THH2 of the second channel region 140 in the second programming state. Here, it is assumed that the third charge amount Q ₃ corresponding to the third programming state is greater than the second charge amount Q ₂ corresponding to the second program state.

In addition, the threshold voltage V _THL3 of the first channel region 140 and the threshold voltage of the second channel region 145 in the first gate voltage V ₁ and the second gate voltage V ₂ , and in a third programming state. The relationship as shown in the following inequality 5 is established between the voltages V _THH3 .

Inequality 5 V ₁ <V _THL3 <V _THH3 <V ₂

Therefore, the third case the programming state in which the first gate voltage (V ₁₎ in applying a first gate voltage (V ₁₎ is the threshold voltage of the first channel section (140), (V _THL3) and a second channel region (145) Since the threshold voltage V _THH3 is smaller than the threshold voltage V _THH3 , no channel is formed in both the first channel region 140 and the second channel region 145 as shown in FIG. 6A.

Third programmed state at the second gate voltage if (V ₂₎ which is applied to the second gate voltage (V ₂₎ is the first channel section 140, the threshold voltage (V _THL3) and the second channel section 145 of the Since the threshold voltage V _THH3 is greater than the threshold voltage, a channel is formed in both the first channel region 140 and the second channel region 145 as shown in FIG. 6B.

That is, the first gate voltage V ₁ and the second gate voltage V ₂ , and the threshold voltage V _THL3 of the first channel region 140 and the threshold of the second channel region 145 in the third programming state. When the relationship as shown in the above inequality 5 is established between the voltages V _THH3 , a channel having a shape (hereinafter, referred to as a third channel shape) as shown in FIGS. 6A and 6B is formed. This means that when the voltage satisfying the above inequality 5 is selected as the first gate voltage V ₁ and the second gate voltage V ₂ , it is possible to control the third channel shape to be formed in the flash memory device of the present invention. it means.

Here, the following inequality 6 may be used to determine whether the third channel form is formed.

Inequality 6 I _D2 > I _REF1 , I _D1 ≤ I _REF2

That is, the drain region when the first drain current I _D1 and the second gate voltage V ₂ measured in the drain region 130 are applied when the first gate voltage V ₁ is applied in the third programming state. When the second drain current I _D2 measured at 130 satisfies the above inequality 6, it may be determined that the third channel shape is formed in the device.

Referring to the case where the first gate voltage V ₁ is applied in FIG. 6C, since no current flows through the first channel region 140 and the second channel region 145, the first drain current in the third programming state. I _D1 has a value less than or equal to the second reference current I _REF2 . Here, the equal sign assumes the case where the second reference current I _REF2 becomes preferably zero.

Next, a case in which the second gate voltage V ₂ is applied to FIG. 6C will be described. As the second gate voltage V ₂ is applied, the first channel current I _{CH1 (2, 3} ) and the second channel current I _CH2 corresponding to the fifth straight line 13 and the sixth straight line 23, respectively. _(2,3) flows through the first channel region 140 and the second channel region 145, respectively. Therefore, in this case, the second drain current I _D2 (that is, I _{CH1 (2, 3)} + I _{CH 2 (2, 3)} ) has a larger value than the first reference current I _REF1 .

Therefore, when the first drain current I _D1 and the second drain current I _D2 satisfy the above inequality 6, the first drain current I _D1 and the second drain current I _D2 have a third channel shape as shown in FIGS. 6A and 6B. It is possible to determine (read) that the flash memory device of the present invention is in a third programming state (that is, a state in which charge by the third charge amount Q ₃ is accumulated in the floating gate 150).

FIG. 7A is a diagram illustrating the presence or absence of channel formation upon application of a first gate voltage in a fourth programming state in which charge is charged in a floating gate by a fourth amount of charge, and FIG. 7B is a diagram in which charge is charged in a floating gate by a fourth amount of charge. 7A and 7B illustrate the relationship between the gate voltage applied in the fourth programming state of FIGS. 7A and 7B and the measured drain current. One graph. In other words, FIGS. 7A to 7C are in a state in which the floating gate 150 of the flash memory device of the present invention is charged with the fourth charge amount Q ₄ (hereinafter, referred to as a fourth programming state). To illustrate.

Referring to FIG. 7A, when the first gate voltage V ₁ is applied to the control gate 160 in the fourth programming state, no channel is formed in both the first channel region 140 and the second channel region 145. It is not.

Referring to FIG. 7B, as the second gate voltage V ₂ is applied to the control gate 160 in the fourth programming state, a channel is formed only in the first channel region 140. That is, in the fourth programming state, only the first channel current I _{CH1 (2, 4)} flowing through the first channel region 140 exists as the second gate voltage V ₂ is applied (identification of FIG. 7B). Reference (j)), no current flows through the second channel region 145.

When the first gate voltage V ₁ or the second gate voltage V ₂ is applied in the fourth programming state, channel formation between the first channel region 140 and the second channel region 145 is performed through FIG. 7C. It can be explained more clearly.

Referring to FIG. 7C, the seventh straight line 14 indicates the relationship between the gate voltage V _G and the drain current I _D in the first channel region 140 in the fourth programming state. ) Represents the relationship between the gate voltage V _G and the drain current I _D in the second channel region 145 in the fourth programming state. In this case, the threshold voltage V _THL4 of the first channel region 140 in the fourth programming state is greater than the threshold voltage V _THL3 of the first channel region 140 in the third programming state. The threshold voltage V _THH4 of the second channel region 145 in the fourth programming state has a value greater than the threshold voltage V _THH3 of the second channel region 140 in the third programming state. Here, the fourth the fourth charge amount (Q ₄₎ corresponding to the programmed state is assumed to be greater than the amount of charge (Q ₄₎ corresponding to the third program state.

In addition, the threshold voltage V _THL4 of the first channel region 140 and the threshold voltage of the second channel region 145 in the first programming state and the first gate voltage V ₁ and the second gate voltage V ₂ . The relationship as shown in the following inequality 7 holds between the voltages V _THH4 .

Inequality 7 V ₁ <V _THL4 <V ₂ <V _THH4

Therefore, the fourth case the programming state in which the first gate voltage (V ₁₎ in applying a first gate voltage (V ₁₎ is the threshold voltage of the first channel section (140), (V _THL4) and a second channel region (145) Since the threshold voltage V _THH4 is smaller than the threshold voltage V _THH4 , no channel is formed in both the first channel region 140 and the second channel region 145 as shown in FIG. 7A.

The fourth programming a second gate voltage in a state when (V ₂₎ which is applied to the second gate voltage (V ₂₎ is first large and a second channel region (145) than a threshold voltage (V _THL4) of the channel region 140, Since it has a value smaller than the threshold voltage V _THH4 , the channel is formed only in the first channel region 140 as shown in FIG. 7B.

That is, the first gate voltage V ₁ and the second gate voltage V ₂ , and the threshold voltage V _THL4 of the first channel region 140 and the threshold of the second channel region 145 in the fourth programming state. When the relationship as shown in the inequality 7 above is established between the voltage V _THH4 , a channel having a shape as shown in FIGS. 7A and 7B (hereinafter, referred to as a fourth channel shape) is formed. This means that when the voltage satisfying the above inequality 7 is selected as the first gate voltage V ₁ and the second gate voltage V ₂ , it is possible to control the fourth channel shape to be formed in the flash memory device of the present invention. it means.

Here, the following inequality 8 may be used to determine whether the fourth channel shape is formed.

Inequality 8 I _REF2 〈I _D2 〈I _REF1 , I _D1 ≤ I _REF2

That is, the drain region when the first drain current I _D1 and the second gate voltage V ₂ measured in the drain region 130 are applied when the first gate voltage V ₁ is applied in the fourth programming state. When the second drain current I _D2 measured at 130 satisfies the above inequality 8, it may be determined that the fourth channel shape is formed in the device.

Referring to the case where the first gate voltage V ₁ is applied in FIG. 7C, since no current flows through the first channel region 140 and the second channel region 145, the first drain current in the fourth programming state. I _D1 has a value less than or equal to the second reference current I _REF2 . Here, the equal sign assumes the case where the second reference current I _REF2 is preferably zero.

Next, a case in which the second gate voltage V ₂ is applied in FIG. 7C will be described. As the second gate voltage V ₂ is applied, the first channel current I _{CH1 (2, 4)} flows through the first channel region 140 corresponding to the seventh straight line 14. Therefore, in this case, the second drain current I _D2 (that is, equal to I _{CH1 (2, 4)} ) is greater than the second reference current I _REF2 and less than the first reference current I _REF1 . do.

Accordingly, when the first drain current I _D1 and the second drain current I _D2 satisfy the above inequality 8, the first drain current I _D1 and the second drain current I _D2 have the fourth channel shape as shown in FIGS. 7A and 7B. It is possible to determine (read) that the flash memory device of the present invention is in the fourth programming state (that is, the state in which the charge corresponding to the fourth charge amount Q ₄ is accumulated in the floating gate 150).

8A is a diagram illustrating the presence or absence of channel formation upon application of a first gate voltage in a fifth programming state in which charge is charged in a floating gate by a fifth charge amount, and FIG. 8B is a charge in the floating gate as a fifth charge amount. 8A and 8B illustrate the relationship between the gate voltage applied in the fifth programming state of FIGS. 8A and 8B and the measured drain current. One graph. In other words, FIGS. 8A to 8C illustrate a case in which the floating gate 150 of the flash memory device of the present invention is charged with a charge equal to the fifth charge amount Q ₅ (hereinafter, referred to as a fifth programming state). To illustrate.

8A and 8B, when the first gate voltage V ₁ or the second gate voltage V ₂ is applied to the control gate 160 in the fifth programming state, the first channel region 140 and the first channel region 140 may be applied. Channels are not formed in both of the two channel regions 145. When the first gate voltage V ₁ or the second gate voltage V ₂ is applied in the fifth programming state, channel formation between the first channel region 140 and the second channel region 145 is illustrated in FIG. 8C. This can be explained more clearly.

Referring to FIG. 8C, the ninth straight line 15 represents the relationship between the gate voltage V _G and the drain current I _D in the first channel region 140 in the fifth programming state. ) Represents the relationship between the gate voltage V _G and the drain current I _D in the second channel region 145 in the fifth programming state. In this case, the threshold voltage V _THL5 of the first channel region 140 in the fifth programming state is greater than the threshold voltage V _THL4 of the first channel region 140 in the fourth programming state. The threshold voltage V _THH5 of the second channel region 145 in the fifth programming state has a value greater than the threshold voltage V _THH4 of the second channel region 140 in the fourth programming state. Here, it is assumed that the fifth charge amount Q ₅ corresponding to the fifth programming state is greater than the fourth charge amount Q ₄ corresponding to the fourth program state.

In addition, the threshold voltage V _THL5 of the first channel region 140 and the threshold voltage of the second channel region 145 in the first and second gate voltages V ₁ and V ₂ , and a fifth programming state. The relationship as shown in the following inequality 9 holds between the voltages V _THH5 .

Inequality 9 V ₂ 〈V _THL5

Therefore, when the first gate voltage V ₁ or the second gate voltage V ₂ is applied in the fifth programming state, the first gate voltage V ₁ and the second gate voltage V ₂ are both the first channel. region 140 because of the different values that are less than the threshold voltage (V _THH5) of the threshold voltage (V _THL5) and the second channel section 145, the first channel section as shown in Fig. 8a and 8b (140) and second Channels are not formed in all of the channel regions 145.

That is, the threshold voltage V _THL5 of the first channel region 140 and the threshold voltage of the second channel region 145 in the fifth programming state with the first gate voltage V ₁ and the second gate voltage V ₂ . When the relationship as shown in the above inequality 9 is established between the voltages V _THH5 , channels (hereinafter, referred to as fifth channel shapes) of the shapes shown in FIGS. 8A and 8B are formed. This means that when the voltage satisfying the above inequality 9 is selected as the first gate voltage V ₁ and the second gate voltage V ₂ , it is possible to control the fifth channel shape to be formed in the flash memory device of the present invention. it means.

Here, the following inequality 10 may be used to determine whether the fifth channel form is formed.

Inequality 10 I _D1 ≤ I _REF2 , I _D2 ≤ I _REF2 .

That is, the drain region when the first drain current I _D1 and the second gate voltage V ₂ measured in the drain region 130 are applied when the first gate voltage V ₁ is applied in the fifth programming state. When the second drain current I _D2 measured at 130 satisfies the above inequality 10, it may be determined that the fifth channel shape is formed in the device.

Referring to the case in which the first gate voltage V ₁ or the second gate voltage V ₂ is applied in FIG. 8C, current does not flow through the first channel region 140 and the second channel region 145. In a programming state, the first drain current I _D1 and the second drain current I _D2 have a value equal to or less than the second reference current I _REF2 . Here, the equal sign assumes the case where the second reference current I _REF2 becomes preferably zero.

Accordingly, when the first drain current I _D1 and the second drain current I _D2 satisfy the above inequality 10, the first drain current I _D1 and the second drain current I _D2 have the fifth channel shape as shown in FIGS. 8A and 8B. It is possible to determine (read) that the flash memory device of the present invention is in a fifth programming state (that is, a state in which charge as much as the fifth charge amount Q ₅ is accumulated in the floating gate 150).

As described above, the flash memory device having a multi-channel according to the present invention can read out each programming state of the device using only a total of two gate voltages V _G. In particular, a flash memory device having two channels according to an embodiment of the present invention can control read operations according to a total of five programming states by applying two gate voltages V _G two times, one time each. For this reason, the read operation time in the flash memory device can be reduced.

Herein, any four programming states among the above-described first to fifth programming states correspond one-to-one to respective levels '00', '01', '10', and '11' in the case of a multi-level flash memory device. It can be used to program multilevel flash memory devices.

In this case, the reading of each program state can be performed simply by comparing the drain current I _D measured according to the gate voltage V _G applied to the device with a predetermined reference current. That is, in the flash memory device of the present invention, the first gate voltage first drain current at the time of the application of (V ₁₎ (I _D1) and a second drain current at the time of the application of the second gate voltage (V _2), as described above By comparing (I _D2 ) with the first reference current (I _REF1 ) and the second reference current (I _REF2 ), respectively, each programming state of the device can be easily checked (read).

As described above, according to the flash memory device and the read operation control method according to the present invention, it is possible to reduce the read operation time and the program check time in the flash memory device through a multi-channel structure having different doping concentrations, respectively, This has the effect of increasing the current sensing margin of the current measurement circuit.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be readily understood that modifications and variations are possible.

Claims (11)

A semiconductor substrate having a source region and a drain region formed to be spaced apart from each other; N channel regions (N is a natural number of two or more) formed between the source region and the drain region, each doped at a different concentration; A floating gate formed on the channel region; And A control gate formed on the floating gate Flash memory device comprising a. The method of claim 1, And the N channel regions are formed of two channel regions of a first channel region and a second channel region doped at a higher concentration than the first channel region. The method of claim 1, The semiconductor substrate is a doped semiconductor substrate, One channel region of the N channel region is formed as a predetermined region of the doped semiconductor substrate. The method of claim 1, The N channel regions are formed in the longitudinal direction connecting the source region and the drain region, respectively. A semiconductor substrate having a source region and a drain region, a flash including a first channel region formed between the source region and the drain region and a second channel region doped at a higher concentration than the first channel region, a floating gate, and a control gate A read operation control method of a flash memory device for controlling a read operation in a memory device, A programming state corresponding to the amount of charge accumulated in the floating gate by comparing the gate voltage applied to the control gate with the threshold voltage V _{THL of} the first channel region and the threshold voltage V _THH of the second channel region, respectively. The read operation control method of the flash memory device for determining. The method of claim 5, And a gate voltage applied to the control gate using a first gate voltage (V ₁ ) and a second gate voltage (V ₂ ) that is higher than the first gate voltage. The method of claim 6, And the first gate voltage (V ₁ ) and the second gate voltage (V ₂ ) are determined to satisfy values of inequalities 1 to 5 below. Inequality 1 V ₁ 〉 V _THH1 Inequality 2 V _THL2 <V ₁ <V _THH2 <V ₂ Inequality 3 V ₁ <V _THL3 <V _THH3 <V ₂ Inequality 4 V ₁ <V _THL4 <V ₂ <V _THH4 Inequality 5 V ₂ 〈V _THL5 -here, V _THH1 is a threshold voltage of a second channel region in a first programming state in which charge is charged in the floating gate by a first charge amount, V _THL2 and V _THH2 are the respective threshold voltages of the first channel region and the second channel region in the second programming state in which charge is charged in the floating gate by a second amount of charge, V _THL3 and V _THH3 are the threshold voltages of each of the first channel region and the second channel region in a third programming state in which charge is charged in the floating gate by a third amount of charge, V _THL4 and V _THH4 are the threshold voltages of each of the first channel region and the second channel region in the fourth programming state in which charge is charged in the floating gate by a fourth amount of charge, V _THH5 is a threshold voltage of a first channel region in a fifth programming state in which charge is charged in the floating gate by a fifth amount of charge. The method of claim 7, wherein Wherein the programmed state is the first gate voltage (V ₁₎ a first drain current is measured at the drain region as the applied (I _D1) and the second gate voltage (V ₂₎ measured at the drain region as this is The second drain current I _D2 is compared with a predetermined first reference current I _REF1 and a second reference current I _REF2 , respectively. The method of claim 8, The comparison between the first drain current I _D1 and the second drain current I _D2 and the first reference current I _REF1 and the second reference current I _REF2 may be performed using the following inequality 6 to inequality 10. , And the first programming state to the fifth programming state correspond to the following inequality 6 to inequality 10 in one-to-one correspondence. Inequality 6 I _D1 〉 I _REF1 , I _D2 〉 I _REF1 Inequality 7 I _D2 〉 I _REF1 〉 I _D1 〉 I _REF2 Inequality 8 I _D2 〉 I _REF1 , I _D1 ≤ I _REF2 Inequality 9 I _REF2 〈I _D2 〈I _REF1 , I _D1 ≤ I _REF2 Inequality 10 I _D1 ≤ I _REF2 , I _D2 ≤ I _REF2 The method of claim 9, The second reference current I _REF2 is set to 0 or a predetermined current value corresponding thereto, When the current flows in the first channel region and the second channel region, respectively, the first reference current I _REF1 is the first drain current I _D1 and the second drain current I _D2 , respectively. When the current flows only in the first channel region, the first drain current I _D1 and the second drain current I _D2 are greater than the first reference current I _REF1 , respectively. _REF2 ) and a read operation control method of the flash memory device configured to be smaller than the first reference current I _REF1 . The method of claim 9, Any four programming states of the first to fifth programming states control read operations of a flash memory device having one-to-one correspondence with one of '00', '01', '10', and '11'. Way.

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