KR20080043700A - Photodiode - Google Patents

Abstract

A photodiode is provided to separate three wavelength ranges of ultraviolet rays and to detect respective intensities of the wavelength ranges of ultraviolet rays by opposing a high-density P-type diffusion region and a high-density N-type diffusion region to each other. A plurality of silicon semiconductor layers(4a,4b) having different thickness values are formed on an insulating layer. Each of the silicon semiconductor layers has a low-density diffusion region which is formed by diffusing one of a low-density P type impurity and a low-density N type impurity. A high-density P-type diffusion region is formed by diffusing a high-density P type impurity. A high-density N-type diffusion region is formed by diffusing a high-density N type impurity. The high-density P-type diffusion region and the high-density N-type diffusion region are arranged opposite to each other.

Description

Photodiode {PHOTODIODE}

The present invention relates to a photodiode that receives light, in particular ultraviolet light, to generate a current.

A conventional photodiode is an N-type impurity in a silicon semiconductor layer in which N-type impurities of a SOI (Silicon On Insulator) substrate in which a silicon semiconductor layer having a thickness of about 150 nm is formed with a buried oxide film on a silicon substrate are diffused at low concentration. The N + diffused layer formed by diffusing to a high concentration to form an "E" comb and the comb portion of the P + diffused layer formed by forming a "Π" comb into a high concentration by diffusing P-type impurities into a horizontal shape, A predetermined voltage is applied to a metal wiring electrically connected to the N + diffusion layer and the P + diffusion layer to detect the intensity of the ultraviolet rays (see Patent Document 1, for example).

[Patent Document 1] Japanese Patent Application Laid-Open No. 7-162024 (Page 4, Paragraph 0025-Page 5, Paragraph 0035, Fig. 2, Fig. 3)

Today, with the increase in the irradiation amount of ultraviolet rays due to the destruction of the ozone layer, there is a concern about the effect on the human body and the environment of ultraviolet rays contained in sunlight.

Generally, ultraviolet rays refer to unrecognizable light in the ultraviolet region having a wavelength of 400 nm or less, but long-wave ultraviolet (UV-A wavelength: about 320 to 400 nm) and medium-wave ultraviolet (UV-B wave: about 280 to wavelength) 320 nm) and short-wave ultraviolet light (UV-C wave: wavelength of about 280 nm or less), and the influence on the human body and the environment varies according to these wavelength ranges, and the UV-A wave blackens the skin and reaches the dermis. It causes aging, and UV-B waves cause skin irritation and skin cancer, and UV-C waves are considered to be absorbed by the ozone layer although they have a strong bactericidal action.

For this reason, the expectation is high for the development of the sensor which isolate | separates the ultraviolet-ray of these three wavelength ranges, and detects the intensity.

However, in the conventional technique described above, although the total amount of ultraviolet rays in the ultraviolet region having a wavelength of 400 nm or less can be detected, there is a problem that three wavelength regions cannot be detected separately.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a photodiode capable of separating three wavelength regions of ultraviolet rays and detecting the intensity thereof.

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention includes a plurality of silicon semiconductor layers having different thicknesses formed on the insulating layer, and each of the silicon semiconductor layers having a thickness of either the P-type or N-type P type high concentration diffusion layer formed by diffusing impurities at low concentration and formed by diffusing P type impurities at high concentration with each of said low concentration diffusion layers interposed therebetween, and N type formed by diffusing N type impurities at high concentration The high concentration diffusion layer is arranged to face each other.

Thus, the present invention provides each photosensitive element formed in a silicon semiconductor layer having a different thickness.

From the output of the ruler, it is possible to obtain the photodiode which can separate the ultraviolet rays of the three wavelength ranges by calculation, and can easily obtain the photodiode which can separate the ultraviolet rays of the three wavelength ranges and detect the intensity. Obtained.

EMBODIMENT OF THE INVENTION Below, the Example of the photodiode by this invention is described with reference to drawings.

Example 1

1 is an explanatory diagram showing a top surface of a photodiode of Example 1, FIG. 2 is an explanatory diagram showing a cross section of a photodiode of Example 1, and FIGS. 3 to 6 are views showing a manufacturing method of a photo IC of Example 1; It is also.

2 is a cross-sectional view taken along the line A-A of FIG. 1.

1 and 2, 1 is a photodiode, and a thin single crystal is interposed between a buried oxide film 3 serving as an insulating layer made of silicon oxide (SiO ₂ ) on a silicon substrate made of silicon (Si) (not _shown ). By the first and second photosensitive elements 11 and 21 formed in the first and second silicon semiconductor layers 4a and 4b having different thicknesses of the semiconductor wafer of the SOI structure in which the silicon semiconductor layer 4 made of silicon is different. It is composed.

The thicknesses of the first and second silicon semiconductor layers 4a and 4b of the present embodiment are 36 nm or less in thickness in order to separate the ultraviolet rays of the three wavelength regions of the ultraviolet region having a wavelength of 400 nm or less and detect the intensity thereof. In the range of, each step is set to a different thickness.

That is, the light absorption factor I / Io in silicon is represented by the Ber's law shown in the following formula using the light absorption coefficient α.

I / Io = exp (-αZ) ------ (1)

Where Z is the entrance depth of light, I is the light intensity at depth Z, and Io is the incident light intensity.

As shown in FIG. 7, the light absorption coefficient α has a wavelength dependency, and when the light absorption coefficient I / Io is obtained for each thickness Z of the silicon semiconductor layer 4 using Equation (1), as shown in FIG. 8. A graph is obtained.

As shown in Fig. 8, when the light absorption rate I / Io is 0.1 or less, i.e., 10% or less, the light absorption rate I / Io decreases rapidly, and as the thickness becomes thinner, the wavelength becomes shorter, that is, in the ultraviolet region. It can be seen that the shift in the direction.

In order to take advantage of this property, when the wavelength at which the light absorption rate I / Io is 10% with respect to the thickness of the silicon semiconductor layer 4 is obtained, as shown in FIG. 9, sensitivity is selectively selected in an ultraviolet region having a wavelength of 400 nm or less. In order to have it, it turns out that the thickness of the silicon semiconductor layer 4 should just be 50 nm or less.

Based on the above calculation results, a photosensitive element having the same configuration as that of the first photosensitive element 11 described later is formed alone in the silicon semiconductor layer 4 whose thickness is varied in a range of 50 nm or less. The sensitivity with respect to the wavelength of these light was measured by experiment.

20 is a graph showing the sensitivity of the photosensitive element when the thickness of the silicon semiconductor layer 4 is 40.04 nm. As shown in FIG. 20, in the photosensitive element whose thickness was set to about 40 nm, the sub peak (circle shown in FIG. 20) to the wavelength range (purple) of visible light longer than a wavelength range of an ultraviolet-ray (wavelength range 400 nm or less of wavelength) is shown. ) Is present.

This calculation was performed assuming that light passed through the silicon semiconductor layer 4 as it was in the above calculation. However, in the actual photosensitive device, light is reflected at the interface between the silicon semiconductor layer 4 and the buried oxide film 3. This is considered to be because the length of the path through which the light passes increases and reacts with visible light having a wavelength longer than that of the ultraviolet light, which appears as a sub peak.

Such a sub peak also appears in the thinner silicon semiconductor layer 4, and the resultant wavelength (referred to as the sub peak wavelength) is obtained by experiment.

As shown in FIG. 21, the sub peak wavelength is shortened as the thickness of the silicon semiconductor layer 4 becomes thin, the thickness of the silicon semiconductor layer 4 is Tsi (unit: nm), and the sub peak wavelength is Ls. When set to (unit: nm),

Ls = 2.457Tsi + 312.5 ------ (2)

The first and second silicon are approximated by an empirical formula represented by, in order to avoid the influence of reflection at the interface between the silicon semiconductor layer 4 and the buried oxide film 3 and not to react with visible light having a wavelength longer than 400 nm. It is understood that the thicknesses of the semiconductor layers 4a and 4b should be different thicknesses in the range of 36 nm or less.

For this reason, the thickness of the silicon semiconductor layer 4 for selectively detecting only the ultraviolet region is preferably set to 36 nm or less, and the lower limit thereof is preferably set to 3 nm.

The thickness of the silicon semiconductor layer 4 is 3 nm or more because it becomes difficult to absorb the variation in thickness in the case of forming the silicon semiconductor layer 4 on the semiconductor wafer.

The first silicon semiconductor layer 4a of the present embodiment is formed to a thickness thicker than the second silicon semiconductor layer 4b, and the thickness of the first silicon semiconductor layer 4a is 35 nm and the second silicon semiconductor layer 4b. Is 10 nm.

Thus, on the 1st silicon semiconductor layer 4a with the thickness set, as shown in FIGS. 3-6, the 1st diode formation area for forming the 1st photosensitive element 11 of the photodiode 1 is shown. 6a, transistor forming regions 8a and 8b for forming nMOS element 31 and pMOS element 41 as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are set, and on second silicon semiconductor layer 4b The second diode formation region 6b for forming the second photosensitive element 21 of the photodiode 1 is set.

In addition, element isolation for forming the element isolation layer 9 is formed in a region surrounding each of the first and second diode formation regions 6a and 6b and the transistor formation regions 8a and 8b in a rectangular frame shape. The area 10 is set.

The element isolation layer 9 is formed by reaching the buried oxide film 3 with an insulating material such as silicon oxide in the first silicon semiconductor layer 4a having a thick thickness of the element isolation region 10. Electrically between the first and second diode forming regions 6a and 6b of the silicon semiconductor layers 4a and 4b and neighboring each of the transistor forming regions 8a and 8b of the first silicon semiconductor layer 4a. It has a function of separating and insulating.

In addition, in this description, as shown to FIG. 1, FIG. 2 etc., the element isolation layer 9 is shown by the mesh wire for a distinction.

The first photosensitive element 11 of the present embodiment is formed in the first diode forming region 6a set in the thick first silicon semiconductor layer 4a.

12 is a first P + diffusion layer as a P-type high concentration diffusion layer, and is a diffusion layer formed by diffusing P-type impurities such as boron (B) at a relatively high concentration in the first silicon semiconductor layer 4a of the first diode formation region 6a. As shown in FIG. 1, the peak part 12a which contact | connects the one side 9a inside the element isolation layer 9, and the element isolation layer 9 which oppose the one side 9a from the peak part 12a are shown. Is formed in a comb shape formed of a plurality of comb portions 12b extending toward the other side 9b of the inner side.

The first P + diffusion layer 12 of the present embodiment extends the two comb portions 12b from the peak portion 12a and is formed in a “Π” shape.

14 is a first N + diffusion layer as an N-type high concentration diffusion layer, and in the first silicon semiconductor layer 4a of the first diode formation region 6a, a type opposite to the P-type high concentration diffusion layer, that is, phosphorus (P) or arsenic ( As a diffusion layer formed by diffusing an N-type impurity such as As) at a relatively high concentration, as shown in FIG. 1, the peak portion 14a and the peak portion (a) contacting the other side 9b inside the device isolation layer 9 are formed. It is formed in the shape of a comb formed from a plurality of comb portions 14b extending from the side 14a toward the opposite side 9a.

The first N + diffusion layer 14 of the present embodiment extends the three comb-tooth portions 14b from both ends and the center of the peak portion 14a, and is formed in an "E" shape.

15 is a first P-diffusion layer serving as a low concentration diffusion layer, which is spaced apart from each other to engage the comb portions 12b and 14b so as to be in contact with the first P + diffusion layer 12 and the first N + diffusion layer 14 which are disposed to face each other. A diffusion layer formed by diffusing a P-type impurity at a relatively low concentration in one silicon semiconductor layer 4a, and is a site where electron-hole pairs are generated by ultraviolet light absorbed by a depletion layer formed thereon.

By the above structure, as shown in FIG. 1, the 1st photosensitive element 11 of the photodiode 1 of a present Example has the 1st P + diffused layer 12 and the 1st N + diffused layer 14 Are arranged to face each other with the comb portions 12b and 14b interposed therebetween, with the first P-diffusion layer 15 interposed therebetween, except for the boundary 16 with the respective first P-diffusion layer 15. The peripheral part is formed in contact with the element isolation layer 9.

The second photosensitive element 21 of the present embodiment is formed in the second diode forming region 6b set in the thin second silicon semiconductor layer 4b in the same manner as the first photosensitive element 11, and FIGS. 1 and 2. As shown in the figure, the other side 9d of the inner side of the element isolation layer 9 which faces the one side 9c from the peak 22a in contact with the one side 9c of the inner side of the element isolation layer 9 is disposed. A second P + diffusion layer 22 and a device isolation layer 9 as a P-type high concentration diffusion layer in which a plurality of P-type impurities formed in a “Π” -shaped comb shape are diffused at a relatively high concentration in the plurality of comb portions 22b extending toward the surface. A relatively high concentration of N-type impurities formed in the shape of a comb of an "E" shape in a plurality of comb portions 24b extending from the peak portion 24a facing the other side 9d on the inner side thereof to face one side 9c. N + diffusion as an N-type high concentration diffusion layer diffused by The layers 24 are disposed to face each other by engaging the comb portions 22b and 24b with each other, and are interposed in contact with the boundary 26 between the second P + diffusion layer 22 and the second N + diffusion layer 24. A second P-diffusion layer 25 is provided as a low concentration diffusion layer in which P-type impurities are diffused at a relatively low concentration.

As shown in FIG. 6 (P13), the first and second photosensitive elements 11 and 21 of the present embodiment include the nMOS element 31 and the pMOS element 41 formed in the first silicon semiconductor layer 4a. Formed together.

The nMOS element 31 of the present embodiment is formed in the transistor formation region 8a set in the thick first silicon semiconductor layer 4a.

In Fig. 6 (P13), 32 is a gate oxide film, and a relatively thin film insulating film made of an insulating material such as silicon oxide.

33 is a gate electrode, and is an electrode made of polysilicon or the like in which impurities (N type in this embodiment) of the same type as the source layer 35 (described later) are diffused at a relatively high concentration, and the gate length of the transistor formation region 8a is formed. It is formed to face the first silicon semiconductor layer 4a of the transistor formation region 8a with the gate oxide film 32 therebetween in the center of the direction, and on the side thereof with an insulating material such as silicon nitride (Si ₃ N ₄ ). A side wall 34 is formed.

In the first silicon semiconductor layer 4a on both sides of the gate electrode 33 of the transistor formation region 8a, a source layer 35 and a drain layer 36 in which N-type impurities are diffused in a relatively high concentration are formed, respectively. On the gate electrode 33 side of each of the extension portions 37 of the source layer 35 and the drain layer 36, impurities of the same type as the source layer 35 have a lower concentration (medium concentration) than the source layer 35. It is formed by diffusing.

In the first silicon semiconductor layer 4a between the source layer 35 under the gate oxide film 32 and the respective extending portions 37 of the drain layer 36, impurities of the type opposite to the source layer 35 are formed. A channel region 38 in which a channel of the nMOS element 31 in which phosphorus P-type impurities are diffused at a relatively low concentration is formed.

The pMOS element 41 of this embodiment is formed in the transistor formation region 8b set in the thick first silicon semiconductor layer 4a in the same manner with the impurity of the nMOS element 31 reversed, and the source layer 45 ) And the side on the side opposite to each other with the gate oxide film 42 interposed between the drain layer 46 and the channel region 48 between each of the extension portions 47 of the source layer 45 and the drain layer 46. It has the gate electrode 43 in which the wall 34 was formed.

The first and second P + diffusion layers 12 and 22 of the first and second photosensitive elements 11 and 21 of the present embodiment, and the source layer 45 and the drain layer 46 of the pMOS element 41, It is formed by diffusing the same impurities of the P type at the same concentration.

In addition, the 1st and 2nd N + diffused layers 14 and 24 of the 1st and 2nd photosensitive elements 11 and 21, and the source layer 35 and the drain layer 36 of the nMOS element 31 are respectively, It is formed by diffusing the same impurities of N type to the same concentration.

Further, the first and second P-diffusion layers 15 and 25 of the first and second photosensitive elements 11 and 21 and the channel region 38 of the nMOS element 31 each contain the same impurity of P type. It is formed by diffusion to the same concentration.

In addition, said gate length direction means the direction from the source layer 35 or 45 to the drain layer 36 or 46 in parallel with the upper surface of the 1st silicon semiconductor layer 4a, or the reverse direction.

3 to 5, 51 is a resist mask as a mask member, and is a mask pattern formed by exposing and developing a positive or negative type resist applied on the silicon semiconductor layer 4 by photolithography. It functions as a mask in the etching and ion implantation of this embodiment.

Hereinafter, the manufacturing method of the photo IC of a present Example is demonstrated according to the process shown by P in FIGS.

The silicon semiconductor layer 4 of the semiconductor wafer of this embodiment is formed on the semiconductor wafer of the SOI structure or the buried oxide film 3 formed by leaving a thin silicon layer on the buried oxide film 3 by the SIMO (Separation by Implanted Oxygen) method. A sacrificial oxide film is formed by a thermal oxidation method on a thin silicon layer of a semiconductor wafer of an SOI structure formed by attaching a thin silicon layer, which is removed by wet etching to form a thickness of 35 nm equal to the thickness of the first silicon semiconductor layer 4a. .

On the silicon semiconductor layer 4 of the semiconductor wafer in which the silicon semiconductor layer 4 of predetermined thickness (35 nm in this embodiment) was formed on the P1 (FIG. 3) and the buried oxide film 3, it was thin by the thermal oxidation method. A pad oxide film having a film thickness is formed, a silicon nitride film made of silicon nitride is formed on the pad oxide film by CVD (Chemical Vapor Deposition) method, and the first diode forming regions 6a, 6b are formed on the silicon nitride film by photolithography. ) And a resist mask (not shown) covering the transistor formation regions 8a and 8b, i.e., exposing the element isolation regions 10, are formed as a mask to remove the silicon nitride film by anisotropic etching to expose the pad oxide film. .

By removing the resist mask and using the exposed silicon nitride film as a mask, the silicon semiconductor layer 4 of the device isolation region 10 is oxidized by the LOCOS (Local Oxidation Of Silicon) method to reach the buried oxide film 3. The device isolation layer 9 is formed, the silicon nitride film and the pad oxide film are removed by wet etching, and the device isolation layer 9 is formed in each device isolation region 10 of the silicon semiconductor layer 4.

Then, a silicon nitride film 53 made of silicon nitride is formed on the silicon semiconductor layer 4 by CVD, and the second diode forming region 6b is exposed on the silicon nitride film 53 by photolithography. The resist mask 51 is formed, and as a mask, the silicon nitride film 53 is removed by anisotropic etching to expose the silicon semiconductor layer 4 of the second diode formation region 6b.

The resist mask 51 formed in P2 (FIG. 3) and step P1 is removed, and a sacrificial oxide film 54 is formed in the silicon semiconductor layer 4 of the second diode formation region 6b by thermal oxidation.

P3 (FIG. 3), the sacrificial oxide film 54 is removed by wet etching, immersed in thermal phosphoric acid to remove the silicon nitride film 53, and the thickness of the silicon semiconductor layer 4 in the second diode formation region 6b. The second silicon semiconductor layer 4b having a thickness of 10 nm is formed.

Thereby, the silicon semiconductor layer 4 of regions other than the 2nd diode formation region 6b which was covered by the silicon nitride film 53 is formed as the 1st silicon semiconductor layer 4a.

P4 (FIG. 3), the first diode forming region 6a and the transistor forming region 8a of the first silicon semiconductor layer 4a by photolithography, and the second diode forming region of the second silicon semiconductor layer 4b. A resist mask 51 having exposed 6b is formed, and as a mask, P-type impurity ions are implanted into the exposed first and second silicon semiconductor layers 4a, 4b, and the first silicon semiconductor layer ( In the 4a), the first P-diffusion layer 15 of the first photosensitive element 11 in which the P-type impurity is diffused at a relatively low concentration, and the channel region 38 of the nMOS element 31 are formed. In the semiconductor layer 4b, a second P-diffusion layer 25 of the second photosensitive element 21 in which P-type impurities are diffused at a relatively low concentration is formed.

The resist mask 51 formed at P5 (FIG. 4) and step P4 is removed, and a resist mask 51 is formed by exposing the transistor formation region 8b of the first silicon semiconductor layer 4a by photolithography. N-type impurity ions are implanted into the first silicon semiconductor layer 4a exposed as a mask, and N-type impurities are diffused in a relatively low concentration into the first silicon semiconductor layer 4a of the transistor formation region 8b. The channel region 48 of the pMOS element 41 is formed.

P6 (FIG. 4), the upper surfaces of the first and second silicon semiconductor layers 4a and 4b are oxidized by thermal oxidation to form a silicon oxide film 55, and the polyoxide is deposited on the silicon oxide film 55 by CVD. Silicon is deposited to form a polysilicon layer 56 of relatively thick film.

P7 (FIG. 4), the resist mask which covers the formation area of the gate electrode 33 and 43 of the center part of the gate length direction of the transistor formation area 8a, 8b on the polysilicon layer 56 by photolithography (illustration ), The polysilicon layer 56 and the silicon oxide film 55 are etched by dry etching or the like as a mask, and the channel of the first silicon semiconductor layer 4a is interposed through the gate oxidizing films 32 and 42. Gate electrodes 33 and 43 opposing the regions 38 and 48 are formed, and the above resist mask is removed.

P8 (FIG. 4), formation region of the 1st and 2nd N + diffused layers 14 and 24 of the 1st and 2nd diode formation area | regions 6a and 6b by photolithography ("E" shape shown in FIG. 1) And the resist mask 51 which exposes the transistor formation region 8a, and exposes it as a mask, the polysilicon of the 1st and 2nd silicon semiconductor layers 4a and 4b and the gate electrode 33 which were exposed. N-type impurity ions are implanted into the first silicon semiconductor layer 4a on both sides of the gate electrode 33 to form an extension portion 37 of the nMOS element 31 in which the N-type impurity is diffused at a medium concentration. In the first and second silicon semiconductor layers 4a and 4b in the formation region of the gate electrode 33 and the first and second N + diffusion layers 14 and 24, medium concentration N-type impurities are diffused.

The resist mask 51 formed at P9 (FIG. 5) and step P8 is removed, and the first and second P + diffusion layers 12 and 22 of the first and second diode formation regions 6a and 6b are removed by photolithography. ) And a resist mask 51 exposing the transistor formation region 8b and the first and second silicon semiconductor layers exposed as a mask. PMOS devices in which P-type impurity ions are implanted into the polysilicon of the gate electrodes 43 and 4a and 4b, and the P-type impurities are diffused to the first silicon semiconductor layer 4a on both sides of the gate electrode 43 at a medium concentration. The extension part 47 of the 41 is formed, and the first and second silicon semiconductor layers 4a and 4b in the formation region of the gate electrode 43 and the first and second P + diffusion layers 12 and 22. D-type impurities are diffused to the medium.

The resist mask 51 formed in P10 (FIG. 5) and step P9 is removed, and silicon nitride is deposited on the entire surfaces of the gate electrodes 33 and 43 and the first and second silicon semiconductor layers 4a and 4b by CVD. Is deposited to form a silicon nitride film, the silicon nitride film is etched by anisotropic etching, and the top surfaces of the gate electrodes 33 and 43 and the top surfaces of the first and second silicon semiconductor layers 4a and 4b are exposed to form a gate electrode. Side walls 34 are formed on the side surfaces of the sides 33 and 43.

P11 (FIG. 5), the same resist mask 51 as in step P8 is formed by photolithography, and the first and second silicon semiconductor layers 4a and 4b and the gate electrode 33 exposed as a mask are exposed. The source layer 35 and the drain of the nMOS element 31 in which N-type impurity ions are injected into polysilicon and N-type impurities are diffused in a relatively high concentration in the first silicon semiconductor layer 4a on both sides of the sidewall 34. Forming first and second N + diffused layers 14, 24 of the first and second photosensitive elements 11, 21 on the layer 36 and the first and second silicon semiconductor layers 4a, 4b, respectively. In addition, relatively high concentrations of N-type impurities are diffused into the gate electrode 33.

The resist mask 51 formed in P12 (FIG. 5) and step P11 is removed, and the same resist mask 51 as in step P9 is formed by photolithography, and the first and second silicon exposed as a mask are exposed. P-type impurity ions are implanted into the polysilicon of the semiconductor layers 4a and 4b and the gate electrode 43, and the P-type impurities are diffused into the first silicon semiconductor layer 4a on both sides of the sidewall 34 in a relatively high concentration. The first and second photosensitive elements 11 and 21 to the source layer 45, the drain layer 46, and the first and second silicon semiconductor layers 4a and 4b of the pMOS device 41, respectively. And the second P + diffusion layers 12, 22, and a relatively high concentration of P-type impurities are diffused into the gate electrode 43. As shown in FIG.

The resist mask 51 formed in P13 (FIG. 6) and step P12 was removed, and heat treatment was performed to activate the respective diffusion layers, thereby providing the first and second photosensitive elements 11 and 21 of the present embodiment, and the nMOS element. 31, the pMOS element 41 is formed.

Thereafter, an insulating material such as silicon oxide is deposited relatively thick on the entire surface of the first and second silicon semiconductor layers 4a and 4b, such as on the element isolation layer 9, by the CVD method, and the top surface thereof is planarized. A resist mask having an opening in which an interlayer insulating film is formed, and the interlayer insulating film of the contact hole formation region on the second P + diffusion layer 22 and the second N + diffusion layer 24 is exposed on the interlayer insulating film by photolithography. (Not shown) to form a contact hole through the interlayer insulating film to reach the second P + diffusion layer 22 and the second N + diffusion layer 24 by anisotropic etching to selectively etch silicon oxide as a mask. After removing the resist mask, a conductive material is embedded in the contact hole by CVD or sputtering to form a contact plug, and the top surface thereof is planarized. The upper surface of the interlayer insulating film is exposed.

Next, in the same manner as above, a conductive material is embedded in the contact holes on the first P + diffusion layer 12 and the first N + diffusion layer 14, the source layers 35 and 45, and the drain layers 36 and 46. To form a contact plug, and to planarize the upper surface thereof to expose the upper surface of the interlayer insulating film.

In the same manner as above, a contact plug is formed by embedding a conductive material in the contact holes reaching the gate electrodes 33 and 43, and a planarization process is performed to form the photo IC 58 of the present embodiment.

The first and second photosensitive elements 11 and 21 formed in this way have a channel region (n) of the nMOS element 31 whose first and second P-diffusion layers 15 and 25 constitute a photo IC 58. Since the same P-type impurities as 38) are diffused at the same concentration, in step P4 of forming the channel region 38 of the nMOS element 31, it is possible to simultaneously form using the same resist mask 51, The manufacturing process of the photo IC 58 can be simplified.

In addition, the source layer 35 and the drain of the nMOS element 31 in which the first and second N + diffusion layers 14 and 24 of the first and second photosensitive elements 11 and 21 constitute the photo IC 58. Since the N-type impurities like the layer 36 are diffused at the same concentration, the same resist mask 51 is used in the step P11 of forming the source layer 35 and the drain layer 36 of the nMOS element 31. It becomes possible to form simultaneously, and can simplify the manufacturing process of the photo IC 58.

In addition, the source layer 45 and the drain of the pMOS element 41, in which the first and second P + diffusion layers 12 and 22 of the first and second photosensitive elements 11 and 21 constitute the photo IC 58, respectively. Since the P-type impurities such as the layer 46 are diffused at the same concentration, in the step P12 of forming the source layer 45 and the drain layer 46 of the pMOS element 41, the same resist mask 51 is used. It becomes possible to form simultaneously using it, and can simplify the manufacturing process of the photoIC58.

Uniformity of ultraviolet rays of all wavelengths in the ultraviolet region is applied to the photodiode 1 composed of the first and second photosensitive elements 11 and 21 having different thicknesses of the first and second P-diffusion layers 15 and 25, respectively. The calculation result of the light absorption rate I / Io with respect to the wavelength at the time of irradiation is shown in FIG.

The thickness of the 1st P-diffusion layer 15 of the 1st photosensitive element 11 used for calculation is 35 nm, and the thickness of the 2nd P-diffusion layer 25 of the 2nd photosensitive element 21 is 10 nm.

As shown in Fig. 10, the first photosensitive element 11 (thickness of the first P-diffusion layer 15: 35 nm) of the present embodiment, and the second photosensitive element 21 (second P-diffusion layer ( 25) thickness: 10 nm), the light absorption rate characteristics are different, and using this characteristic, UV-A wave, UV by calculating by the difference in their output or their absolute value or their proportional multiple, their combination, etc. -B wave and UV-C wave (hereinafter referred to as A wave, B wave and C para) can be separated to detect respective intensities.

That is, although the ultraviolet rays of all the same wavelengths are irradiated uniformly to the 1st and 2nd photosensitive elements 11 and 21, since the thickness of each silicon semiconductor layer 4 is different, each light absorption rate characteristic differs, As shown in Fig. 11 (a), the output of the second photosensitive element 21 is approximately 1.1 times (broken line shown in Fig. 11 (a)) and subtracted from the output of the first photosensitive element 11, the C wave. Cancels the difference, resulting in an output containing approximately 5% of A and B waves, respectively.

This difference is approximately 20 times to obtain the incident light intensity of the wavelength region where A and B waves are combined, and subtracted from the incident light intensity of the ultraviolet region obtained by about 5 times the first photosensitive element 11 to obtain the incident light intensity of C wave. Can be.

In addition, as shown in FIG. 11 (b), when the output of the second photosensitive element 21 is approximately 1.4 times (broken line shown in FIG. 11 (b)), and subtracted from the output of the first photosensitive element 11, The absolute value of the difference is that the A wave cancels out, resulting in an output containing about 5% of the B and C waves, respectively.

The incident light intensity of the wavelength region obtained by adding the B wave and the C wave by calculating the absolute value of this difference by about 20 times, and subtracting the incident light intensity of the C wave obtained above from the difference, becomes the incident light intensity of the B wave.

Then, the incident light intensity of the B wave and the C wave obtained above is subtracted from the incident light intensity of the ultraviolet region obtained by multiplying the first photosensitive element 11 by about five times, and the difference becomes the incident light intensity of the A wave.

In the same manner as in the above calculation, the result of obtaining the incident light intensities of the respective wavelength widths in the short wavelength width is shown in FIG.

As can be seen from Fig. 12, when the respective outputs from the first and second photosensitive elements 11 and 21 having two kinds of thicknesses of the photodiode 1 of the present embodiment are calculated, UV-A waves, UV- It can be seen that in the state where the B wave and the UV-C wave are separated, the respective intensities can be detected.

In this case, the output from the first and second photosensitive elements 11, 21 of the photodiode 1 converts the photo-generated current into a voltage using a resistor or the like and converts it into a digital value with an A / D converter or the like. What is necessary is just to detect the intensity | strength of each wavelength area | region by extracting and calculating these by the calculation circuit formed in the external circuit.

As described above, in the present embodiment, the first and second layers each having a P + diffusion layer and an N + diffusion layer disposed opposite to each other with a P− diffusion layer interposed therebetween in the first and second silicon semiconductor layers having different thicknesses formed on the insulating layer. By forming two photosensitive elements, ultraviolet rays in three wavelength ranges can be determined by calculation from two kinds of outputs outputted from the first and second photosensitive elements, and their intensities can be obtained. Moreover, the photodiode which can detect the intensity | strength can be obtained easily.

Example 2

FIG. 13 is an explanatory diagram showing a cross section of the photodiode of Example 2, and FIGS. 14 to 17 are explanatory diagrams showing a manufacturing method of the photo IC of Example 2. FIG.

13 is sectional drawing shown by the same cross section as FIG. 2 of Example 1, and the upper surface is the same as FIG. 1 of Example 1. FIG. In addition, the part same as the said Example 1 attaches | subjects the same code | symbol, and abbreviate | omits the description.

As shown in FIGS. 14 to 17, the thinner second silicon semiconductor layer 4b of the present embodiment has a second P-formation region 61 (shown in FIG. 1) of the second P-diffusion layer 25. It is formed only in the "(pi)" shape 2nd P + diffused layer 22 of the 2nd diode formation area | region 6b, and the area | region inserted in the 2nd N + diffused layer 24 of the "E" shape). .

For this reason, as shown in FIG. 13, the 2nd P + diffused layer 22 and the 2nd N + diffused layer 24 of a present Example are formed in the same thickness as the 1st silicon semiconductor layer 4a.

In this case, the second silicon semiconductor layer 4b is set to a thickness of 3 nm or more and less than 30 nm, and the first silicon semiconductor layer 4a is set to 30 nm or more and 36 nm or less.

The thickness of the silicon semiconductor layer 4 is set to 3 nm or more and 36 nm or less for the same reason as in the first embodiment.

When the thickness of the second silicon semiconductor layer 4b is set to less than 30 nm, the thickness of the second P + diffusion layer 22 and the second N + diffusion layer 24 is 30 nm or more. When the thicknesses of the P + diffusion layer 22 and the second N + diffusion layer 24 are each less than 30 nm, even in the case of the P + diffusion layer shown in FIG. 18, even in the case of the N + diffusion layer shown in FIG. 19, the sheet resistance is extremely high. It is because it rises to and the output from the 2nd photosensitive element 21 falls.

In addition, the horizontal axis in FIG. 18, FIG. 19 is the width | variety of the gate length direction of P + diffusion layer and N + diffusion layer, ie, each width of the cross-sectional direction shown in FIG.

Hereinafter, the manufacturing method of the photo IC of a present Example is demonstrated according to the process shown by PA in FIGS. 14-17.

The silicon semiconductor layer 4 of the semiconductor wafer of this embodiment is formed in the same manner as in the above-described first embodiment at 35 nm equal to the thickness of the first silicon semiconductor layer 4a.

In the same manner as in the process of PA1 (FIG. 14) and Example P1, an element isolation layer 9 is formed in each element isolation region 10 of the silicon semiconductor layer 4, and the silicon semiconductor layer 4 is formed on the element isolation region 10. Next, a silicon nitride film 53 made of silicon nitride is formed by the CVD method, and the second P-forming region 61 of the second diode formation region 6b is formed on the silicon nitride film 53 by photolithography. The exposed resist mask 51 is formed, and as a mask, the silicon nitride film 53 is removed by anisotropic etching to expose the silicon semiconductor layer 4 of the second P-formation region 61.

The resist mask 51 formed in PA2 (FIG. 14) and step P1 is removed, and a sacrificial oxide film 54 is formed in the silicon semiconductor layer 4 of the second P-forming region 61 by thermal oxidation. .

The sacrificial oxide film 54 is removed by wet etching with PA3 (FIG. 14), the silicon nitride film 53 is removed by immersion in thermal phosphoric acid, and the silicon semiconductor layer 4 of the second P-formation region 61 is formed. The second silicon semiconductor layer 4b having a thickness of 10 nm is formed.

As a result, the silicon semiconductor layer 4 in a region other than the second P-formed region 61 covered with the silicon nitride film 53 is formed as the first silicon semiconductor layer 4a.

A second diode comprising PA4 (FIG. 14), a first diode forming region 6a and a transistor forming region 8a of the first silicon semiconductor layer 4a by photolithography, and a second silicon semiconductor layer 4b. The resist mask 51 which exposed the formation area 6b was formed, and it was made the same as process P4 of Example 1 as a mask, and the 1st P-diffusion layer 15 of the 1st photosensitive element 11 and The second photosensitive element in which the channel region 38 of the nMOS element 31 is formed, and the P-type impurity is diffused in a relatively low concentration in the second diode formation region 6b including the second silicon semiconductor layer 4b. The second P-diffusion layer 25 of 21 is formed.

The resist mask 51 formed in PA5 (FIG. 15) and step P4 is removed, and the channel region 48 of the pMOS element 41 is formed in the same manner as in step P5 of the first embodiment.

In the same manner as PA6 (FIG. 15) and Step P6 in Example 1, a silicon oxide film 55 is formed, and a polysilicon layer 56 is formed thereon.

PA7 (FIG. 15) and the gate electrode 33 which oppose the channel regions 38 and 48 of the first silicon semiconductor layer 4a via the gate oxide films 32 and 42 in the same manner as in the step P7 of the first embodiment. , 43).

Formation area | region of the 1st and 2nd N + diffused layers 14 and 24 of 1st and 2nd diode formation area | region 6a, 6b by PA8 (FIG. 15) and photolithography ("E" shape shown in FIG. 1) N-type impurity ions are formed in the polysilicon of the first silicon semiconductor layer 4a and the gate electrode 33, which are exposed as a mask. Is injected into the first silicon semiconductor layer 4a on both sides of the gate electrode 33 to form an extension 37 of the nMOS element 31 in which the N-type impurities are diffused in a medium concentration, and the gate electrode 33 is formed. ) And medium N-type impurities in the first silicon semiconductor layer 4a in the formation regions of the first and second N + diffusion layers 14 and 24.

The resist mask 51 formed at PA9 (FIG. 16) and step PA8 is removed, and the first and second P + diffusion layers 12, 22 of the first and second diode formation regions 6a, 6b are removed by photolithography. ) And a resist mask 51 exposing the transistor forming region 8b and the first silicon semiconductor layer 4a exposing this as a mask. And the extension of the pMOS element 41 in which P-type impurity ions are implanted into the polysilicon of the gate electrode 43, and the P-type impurity is diffused to the first silicon semiconductor layer 4a on both sides of the gate electrode 43 at a medium concentration. The portion 47 is formed and medium concentration P-type impurities are diffused into the gate electrode 43 and the first silicon semiconductor layer 4a in the formation regions of the first and second P + diffusion layers 12 and 22. Let's do it.

In the same manner as in step PA10 (FIG. 16) and step P10 in Example 1, sidewalls 34 are formed on the side surfaces of the gate electrodes 33 and 43.

The same resist mask 51 as in the step PA8 is formed by PA11 (FIG. 16) and photolithography, and the N-type is formed on the polysilicon of the first silicon semiconductor layer 4a and the gate electrode 33 which are exposed as a mask. Source layer 35 and drain layer 36 of nMOS element 31 in which impurity ions are implanted and N-type impurities are diffused in relatively high concentrations in first silicon semiconductor layer 4a on both sides of sidewall 34; The first and second N + diffusion layers 14 and 24 of the first and second photosensitive elements 11 and 21 are formed in the first silicon semiconductor layer 4a, and the concentration is relatively high in the gate electrode 33. D-type impurities are diffused.

The resist mask 51 formed in PA12 (FIG. 16) and step PA11 is removed, and the same resist mask 51 as in step PA9 is formed by photolithography, and the first silicon semiconductor layer exposed as a mask ( The pMOS device 41 in which P-type impurity ions are implanted into the polysilicon of the 4a) and the gate electrode 43, and the P-type impurity is diffused in a relatively high concentration in the first silicon semiconductor layer 4a on both sides of the sidewall 34. The first and second P + diffusion layers 12, 22 of the first and second photosensitive elements 11, 21 on the source layer 45, the drain layer 46, and the first silicon semiconductor layer 4a. In addition, relatively high concentration of P-type impurities are diffused into the gate electrode 43.

The resist mask 51 formed in PA13 (FIG. 17) and step PA12 was removed, and heat treatment was performed to activate the respective diffusion layers, thereby providing the first and second photosensitive elements 11 and 21 of the present embodiment, and the nMOS element. 31, the pMOS element 41 is formed.

Thereafter, an interlayer insulating film is formed in the same manner as in Example 1, and the first and second P + diffusion layers 12 and 22 and the first and second N + diffusion layers 14 are formed on the interlayer insulating film by photolithography. 24, a resist mask (not shown) having an opening exposing the interlayer insulating film of the contact hole formation region on the source layers 35 and 45 and the drain layers 36 and 46 is formed, and is the same as in the first embodiment. To form contact plugs that reach each of the diffusion layers, and planarize the upper surface to expose the upper surface of the interlayer insulating film.

Next, in the same manner as described above, a contact plug is formed by filling a conductive material in the contact holes reaching the gate electrodes 33 and 43, and a planarization process is performed to form the photo IC 58 of the present embodiment.

The first and second photosensitive elements 11 and 21 thus formed have the same impurities as those of the first embodiment, each diffusion layer having the same type as each of the diffusion layers of the nMOS element 31 and the pMOS element 41. Since the diffusion is carried out at the same concentration, it is possible to simultaneously form the same resist mask 51 in each formation step, thereby simplifying the manufacturing process of the photo IC 58.

As described above, even if the second P- diffusion layer 25 of the second photosensitive element 21 of the present embodiment has a thickness of less than 30 nm, the second P + diffusion layer 22 and the second N + diffusion layer 25 Since it is formed in the 1st silicon semiconductor layer 4a which has a thickness of 30 nm or more, sheet resistance does not become excessive and the output from the 2nd photosensitive element 21 does not fall.

In addition, since the second P + diffusion layer 22 and the second N + diffusion layer 25 are formed in the first silicon semiconductor layer 4a forming the nMOS element 31 and the pMOS element 41, the depth of the contact hole is increased. The depth of the contact hole formed in the diffusion layer of another source layer or the like can be the same, and the process for forming the contact plug can be simplified, and the manufacturing process of the photo IC 58 can be simplified further.

In the present embodiment, the case where the thickness of the second P-diffusion layer 25 is less than 30 nm has been described as an example, but the case where the thickness of the second P-diffusion layer 25 is 30 nm or more is explained. When the second P + diffusion layer 22 and the second N + diffusion layer 25 are formed in the first silicon semiconductor layer 4a, the effect of the process simplification in forming the same contact plug as described above is obtained.

As described above, in the present embodiment, in addition to the same effect as in the first embodiment, when the thickness of the second silicon semiconductor layer forming the second P-diffusion layer is less than 30 nm, the second P + diffusion layer And by setting the second N + diffusion layer to a thickness of 30 nm or more, the sheet resistance of the high concentration diffusion layer of the second photosensitive element can be prevented from being excessive, and a decrease in the output from the second photosensitive element can be prevented.

Further, by forming the second P + diffusion layer and the second N + diffusion layer in the first silicon semiconductor layer, the upper surfaces of the second P + diffusion layer and the second N + diffusion layer are flush with the upper surfaces of the source and drain layers of the MOSFET. The manufacturing process of the photo IC can be simplified by simplifying the process at the time of forming the contact plug.

In each of the above embodiments, the low concentration diffusion layer of the photodiode of the photodiode has been described as being formed in two kinds of silicon semiconductor layers having different thicknesses, but may be formed in silicon semiconductor layers having three or more kinds of different thicknesses, respectively. do.

In the above embodiments, the low concentration diffusion layer was formed by diffusing the P-type impurities, but the same effect as described above can be obtained even when the N-type impurities are formed by diffusing at a relatively low concentration.

In each of the above embodiments, the P + diffusion layer has been described as having a "?" Shape and the N + diffusion layer has a "E" shape. However, the shapes may be reversed and the number of comb portions may be increased.

Incidentally, in the above embodiments, it has been described that a plurality of comb portions are formed in the P + diffusion layer and the N + diffusion layer and are arranged so as to be interlocked with each other. However, the peak portions may be disposed to face each other with only the low concentration diffusion layer interposed therebetween. .

In each of the above embodiments, the silicon semiconductor layer is described as being a silicon semiconductor layer formed on the buried oxide film as the insulating layer of the SOI substrate, but the silicon semiconductor of the SOS (Silicon On Sapphire) substrate formed on the sapphire substrate as the insulating layer. The layer may be a silicon semiconductor layer of a silicon on quartz (SOQ) substrate formed on a quartz substrate as an insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which shows the upper surface of the photodiode of Example 1. FIG.

Explanatory drawing which shows the cross section of the photodiode of Example 1. FIG.

FIG. 3 is an explanatory diagram showing a method of manufacturing the photo IC of Example 1. FIG.

4 is an explanatory diagram showing a method of manufacturing the photo IC of Example 1. FIG.

FIG. 5 is an explanatory diagram showing a method for manufacturing the photo IC of Example 1. FIG.

FIG. 6 is an explanatory diagram showing a method of manufacturing the photo IC of Example 1. FIG.

7 is a graph showing the wavelength dependence of the light absorption coefficient of silicon (100).

8 is a graph showing the light absorption rate according to the thickness of the silicon semiconductor layer.

9 is a graph showing a wavelength at which the light absorption rate becomes 10%.

10 is a graph showing the light absorption of each photosensitive element of the photodiode of Example 1. FIG.

FIG. 11 is an explanatory diagram showing a detection method of ultraviolet light in each wavelength region of the photodiode of Example 1. FIG.

12 is a graph showing the output characteristics of the photodiode of Example 1. FIG.

FIG. 13 is an explanatory diagram showing a cross section of a photodiode of Example 2. FIG.

FIG. 14 is an explanatory diagram showing a method for manufacturing the photo IC of Example 2. FIG.

FIG. 15 is an explanatory diagram showing a method for manufacturing the photo IC of Example 2. FIG.

FIG. 16 is an explanatory diagram showing a method for manufacturing the photo IC of Example 2. FIG.

FIG. 17 is an explanatory diagram showing a method for manufacturing the photo IC of Example 2. FIG.

FIG. 18 is a graph showing sheet resistance of P + diffusion layers of Example 2. FIG.

FIG. 19 is a graph showing the sheet resistance of the N + diffusion layer of Example 2. FIG.

20 is a graph showing the sensitivity of the photosensitive element when the thickness of the silicon semiconductor layer is 40.04 nm.

Fig. 21 is a graph showing the sub-peak wavelength according to the thickness of the silicon semiconductor layer.

(Explanation of symbols for the main parts of the drawing)

1: Photodiode

3: buried oxide film

4: silicon semiconductor layer

4a: first silicon semiconductor layer

4b: second silicon semiconductor layer

6a: 1st diode formation area

6b: second diode formation region

8a, 8b: transistor formation region

9: element isolation layer

9a, 9c: One side

9b, 9d ： other side

10: device isolation region

11: first photosensitive element

12: first P + diffusion layer

12a, 14a, 22a, 24a: Peak part

12b, 14b, 22b, 24b: comb part

14 first N + diffusion layer

15: first P-diffusion layer

16, 26: Boundary

21: second photosensitive element

22: second P + diffusion layer

24: Second N + diffusion layer

25: second P-diffusion layer

31: nMOS element

32, 42 ： gate oxide film

33, 43: gate electrode

34: Side wall

35, 45 ： Source layer

36, 46 ： Drain floor

37, 47: Extension part

38, 48 ： Channel area

41 ： pMOS element

51: resist mask

53: silicon nitride film

54: sacrificial oxide film

55 silicon silicon film

56: Polysilicon layer

58: Photo IC

61: second P-forming region

Claims (9)

A plurality of silicon semiconductor layers having different thicknesses formed on the insulating layer, The silicon semiconductor layer of each thickness has a low concentration diffusion layer formed by diffusing impurities of either type of P type and N type at low concentration, A P-type high concentration diffusion layer formed by diffusing P-type impurities at high concentration with each of the low concentration diffusion layers interposed therebetween, and an N-type high concentration diffusion layer formed by diffusing N-type impurities at high concentration. diode. The method of claim 1, The P-type high concentration diffusion layer and the N-type high concentration diffusion layer which are disposed to face each other with the low concentration diffusion layer interposed therebetween are formed in a silicon semiconductor layer of the same thickness. The method according to claim 1 or 2, And the silicon semiconductor layers having different thicknesses each have a thickness in a range of 3 nm or more and 36 nm or less. The method of claim 1, When the low concentration diffusion layer is formed in a silicon semiconductor layer of less than 30 nm, the P-type high concentration diffusion layer and the N-type high concentration diffusion layer, which face each other with the low concentration diffusion layer interposed therebetween, have a thickness of 30 nm or more and 36 nm or less. Photodiode characterized in that. A first silicon semiconductor layer formed on the insulating layer, A second silicon semiconductor layer having a thickness thinner than the first silicon semiconductor layer formed on the insulating layer; The first low concentration diffusion layer in which the impurity of any one of the P type and the N type formed on the first silicon semiconductor layer is diffused at low concentration, and the first low concentration diffusion layer is interposed between the first low concentration diffusion layer at a high concentration. A first photosensitive element in which a first P-type high concentration diffusion layer diffused and a first N-type high concentration diffusion layer in which N-type impurities are diffused at high concentration are opposed to each other; The second low concentration diffusion layer in which the impurities of the same type as either the P type or the N type are diffused at low concentration, and the second P type high concentration diffusion layer in which the P type impurities are diffused at a high concentration between the second low concentration diffusion layer. And a second photosensitive element in which a second N-type high concentration diffusion layer in which N-type impurities are diffused at high concentration is disposed to face each other. And the second low concentration diffusion layer is formed in the second silicon semiconductor layer. The method of claim 5, wherein The second P-type high concentration diffusion layer and the second N-type high concentration diffusion layer are formed in the second silicon semiconductor layer. The method of claim 5, wherein The second P-type high concentration diffusion layer and the second N-type high concentration diffusion layer are formed in the first silicon semiconductor layer. The method according to any one of claims 5 to 7, And the first and second silicon semiconductor layers each have a thickness in a range of 3 nm or more and 36 nm or less. The method according to any one of claims 5 to 7, And the first silicon semiconductor layer has a thickness in the range of 30 nm or more and 36 nm or less, and the second silicon semiconductor layer has a thickness in the range of 3 nm or more and less than 30 nm.

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