KR20080041894A - Liquid crystal display - Google Patents

Abstract

An LCD device is provided to ensure a charging time by adjusting a duty ratio of a gate signal, thereby improving display quality. An LCD(Liquid Crystal Display) device includes a timing controller(500), a clock generator(600), a gate driver(400), and a liquid crystal panel(300). The timing controller outputs a first clock generation control signal and a second clock generation control signal with a variable duty ratio. The clock generator receives the first and second clock generation control signals and outputs first and second clock signals having opposite phases and varying the duty ratio. The gate driver receives the first and second clock signals, and outputs a gate signal varying the duty ratio. The liquid crystal panel includes plural pixels which display images by receiving the gate signal.

Description

Liquid crystal display

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2A is an equivalent circuit diagram of one pixel of FIG. 1.

FIG. 2B is a diagram for describing the structure of the pixels of FIG. 1.

3 is a block diagram illustrating the timing controller of FIG. 1.

4 is a block diagram illustrating a clock generator of FIG. 1.

FIG. 5 is a circuit diagram illustrating the flip-flop of FIG. 4.

6 is a signal diagram illustrating a timing controller and a clock generator of FIG. 1.

FIG. 7 is a block diagram illustrating the gate driver of FIG. 1.

FIG. 8 is a circuit diagram illustrating the j-th stage of FIG. 7.

9 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 10 is a block diagram illustrating the timing controller of FIG. 9.

FIG. 11 is a signal diagram illustrating a timing controller and a clock generator of FIG. 9.

(Explanation of symbols for the main parts of the drawing)

10, 11: liquid crystal display device 100: first substrate

200: second substrate 300: liquid crystal panel

400, 400a, 400b: gate driver 410: buffer part

420: charging unit 430: pull-up unit

440: pull-down unit 450: discharge unit

460: holding unit 470: carry signal generation unit

500, 501: timing controller

510 and 511: first clock generation control signal generator

520 and 521: second clock generation control signal generator

530, 531: duty ratio control signal generator

600, 600a, 600b: clock generator 610: flip-flop

620: first clock voltage application unit 630: second clock voltage application unit

640: charge sharing unit 700: data driver

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving display quality.

As the resolution of the liquid crystal display increases, the number of data lines and the number of data driving ICs increase, leading to an increase in manufacturing cost and difficulty in miniaturizing the liquid crystal display. In order to solve this problem, the long sides of the pixels are arranged in the horizontal direction, and the color, red, green, and blue color filters are arranged in the horizontal stripe shape, thereby significantly reducing the number of data driving ICs, thereby lowering the manufacturing cost.

However, in the liquid crystal display having such a structure, pixels connected to some gate lines appear dark. This occurs because the data voltage is not sufficiently charged in the pixel electrode. Therefore, some gate lines must be provided with a gate-on voltage for a sufficient time.

An object of the present invention is to provide a liquid crystal display device capable of improving display quality.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a liquid crystal display device includes a timing controller configured to output a first clock generation control signal, a second clock generation control signal having a variable duty ratio, and the first clock generation control. A clock generator which receives a signal and the second clock generation control signal and outputs a first clock signal and a second clock signal having a different duty ratio and having opposite phases, and the first clock signal and the second clock signal. And a liquid crystal panel including a gate driver configured to receive a gate signal having a variable duty ratio, and a plurality of pixels that receive the gate signal and are turned on / off to display an image.

Other specific details of the present invention are included in the detailed description and drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and those skilled in the art to which the present invention pertains. It is provided to inform the full scope of the invention. Like reference numerals refer to like elements throughout.

Hereinafter, the duty ratio refers to a ratio of time that is a high level for one period.

A liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 8. 1 is a block diagram illustrating a liquid crystal display according to example embodiments of the inventive concept, FIG. 2A is an equivalent circuit diagram of one pixel of FIG. 1, and FIG. 2B is a diagram for explaining the structure of the pixels of FIG. 1. 3 is a block diagram illustrating the timing controller of FIG. 1, FIG. 4 is a block diagram illustrating the clock generator of FIG. 1, FIG. 5 is a circuit diagram illustrating the flip-flop of FIG. 4, and FIG. 6 is a signal diagram illustrating the timing controller and the clock generator of FIG. 1, FIG. 7 is a block diagram illustrating the gate driver of FIG. 1, and FIG. 8 is a circuit diagram illustrating the j-th stage of FIG. 7.

Referring to FIG. 1, the liquid crystal display 10 according to the exemplary embodiment of the present invention may include a liquid crystal panel 300, a timing controller 500, a clock generator 600, a gate driver 400, and a data driver 700. ).

The liquid crystal panel 300 is divided into a display unit DA on which an image is displayed and a non-display unit PA on which an image is not displayed.

The display unit DA includes a first substrate (not shown) on which a plurality of gate lines G1 to Gn, a plurality of data lines D1 to Dm, a switching element (not shown), and a pixel electrode (not shown) are formed, and a color; Including a second substrate (not shown) having a filter (not shown) and a common electrode (not shown), and a liquid crystal layer (not shown) interposed between the first substrate (not shown) and the second substrate (not shown) Display the video. The gate lines G1 to Gn extend substantially in the row direction and are substantially parallel to each other, and the data lines D1 to Dm extend substantially in the column direction and are substantially parallel to each other. The non-display area PA refers to a portion where the first substrate (see 100 of FIG. 2) is formed wider than the second substrate (see 200 of FIG. 2) so that an image is not displayed.

Referring to FIG. 2A, a pixel PX of FIG. 1 is described. A color of a portion of the common electrode CE of the second substrate 200 to face the pixel electrode PE of the first substrate 100 is described. Filter CF may be formed. For example, the pixel PX connected to the i-th (i = 1 to n) gate line Gi and the j-th (j = 1 to m) data line Dj is a switching element connected to the signal lines Gi and Dj. (Q) and a liquid crystal capacitor (Clc) and a storage capacitor (Cst) connected thereto. The sustain capacitor Cst may be omitted as necessary. The switching element Q is a TFT made of a-Si (amorphous silicon). As shown in FIG. 2B, each pixel is formed such that the horizontal length is longer than the vertical length, and the red, green, and blue color filters R, G, and B are arranged in a horizontal stripe shape. That is, the red, green, and blue color filters R, G, and B are sequentially arranged along the data lines D1 -Dm.

For example, the data driver 700 receives the image signal DAT and the data control signal CONT from the timing controller 500, and outputs the image data voltage corresponding to the image signal DAT to each data line D1 to Dm. To provide. The data control signal CONT is a signal for controlling the operation of the data driver 700, and includes a horizontal start signal for starting the operation of the data driver 700, a load signal for indicating output of two data voltages, and the like. .

The timing controller 500 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsinc, a vertical sync signal Hsync, a main clock signal Mclk, and a data enable signal DE.

The timing controller 500 generates a data control signal CONT2 based on the input image signals R, G, and B and the input control signal, and outputs the data control signal CONT2 and the image data DAT to the data driver 700. Send to).

In addition, the timing controller 500 provides the clock generator 600 with the first clock generation control signal OE, the second clock generation control signal CPV, and the original scan start signal STV. Here, the first clock generation control signal OE is a gate enable signal for enabling the gate signal, the original scan start signal STV is a signal indicating the start of one frame, and the second clock generation control signal CPV is As a gate clock signal for determining the duty ratio of the gate signal, the duty ratio is a signal. For example, when the duty ratio of the second clock generation control signal CPV increases, the first clock signal CKV and the second clock generation generated by the first clock generation control signal OE and the second clock generation control signal CPV are increased. The duty ratio of the clock signal CKVB is increased. When the duty ratio of the first clock signal CKV and the second clock signal CKVB increases, the duty ratio of the gate signal increases. The detailed operation and internal circuit of the timing controller 500 will be described later with reference to FIG. 3.

Meanwhile, the clock generator 600 receives the first clock generation control signal OE, the second clock generation control signal CPV, and the scan start signal STV, and thus, the first clock signal CKV and the second clock. The signal CKVB, the scan start signal STVP, and the gate off voltage Voff are provided to the gate driver 400.

The first clock signal CKV and the second clock signal CKVB are signals having opposite phases to each other. The first clock signal CKV and the second clock signal CKVB are signals in which the duty ratio is varied according to the duty ratio of the second clock generation control signal CPV. The scan start signal STVP is a signal whose voltage level is increased in the original scan start signal STV. The detailed operation and internal circuit of the clock generator 600 will be described later with reference to FIGS. 4 to 6.

The gate driver 400 receives the first clock signal CKV and the second clock signal CKVB, the second scan start signal STVP, and the gate off voltage Voff to receive a plurality of gate lines G1 to Gn. To provide a gate signal.

Since the duty ratios of the first clock signal CKV and the second clock signal CKVB are variable, the duty ratio of the gate driver 400 is adjusted according to the duty ratio of the first clock signal CKV and the second clock signal CKVB. Outputs a gate signal. For example, when the duty ratio of the first clock signal CKV and the second clock signal CKVB increases, a gate signal of which the duty ratio is increased is output. The detailed operation and internal circuit of the gate driver 400 will be described later with reference to FIGS. 7 and 8.

The timing controller 500 of FIG. 1 will be described in detail with reference to FIGS. 3 and 6.

First, referring to FIG. 3, the timing controller 500 includes a first clock generation control signal generator 510, a raw second clock generation control signal generator 520, a duty ratio adjustment signal generator 530, and a logic sum. Operator (OR).

In detail, the first clock generation control signal generator 510 receives the main clock Mclk, outputs a first clock generation control signal OE having a predetermined frequency, and outputs the original second clock generation control signal. The generator 520 receives the main clock Mclk and outputs a second clock generation control signal OCPV having a predetermined frequency.

When the duty ratio control signal generator 530 outputs the duty ratio control signal DUCON, the OR operator OR performs an OR operation on the duty ratio control signal DUCON and the second clock generation control signal OCPV. Output the clock generation control signal CPV.

The duty ratio control signal DUCON is a high level signal in a section where a duty ratio is increased. As shown in FIG. 6, the duty ratio of the second clock generation control signal CPV is increased in a predetermined section due to the duty ratio adjustment signal DUCON. Due to the increased duty ratio, the duty ratio of the gate signal Gout _(j) increases. Detailed description thereof will be described later.

That is, the duty ratio control signal generator 530 outputs a signal having a high level in a section corresponding to the gate signal Gout _(j) to increase the duty ratio. The duty ratio of the gate signal Gout _{(j) also} varies according to the time that is the high level of the duty ratio control signal DUCON.

A clock generator of FIG. 1 will be described with reference to FIGS. 4 to 6.

The clock generator 601 includes a logical OR operator, a flip-flop 610, a first clock voltage applier 620, a second clock voltage applier 630, and a charge sharing unit 640. However, the internal circuit of the clock generator 601 is not limited thereto.

The OR operator receives the first clock generation control signal OE and the second clock generation control signal CPV and performs an OR operation to generate a third clock generation control signal CPVX, and then deflip-flop 610. To provide.

As shown in FIG. 5, the deflip-flop 610 receives the third clock generation control signal CPVX through the clock terminal CLK, and the input terminal D is connected to the output bar terminal / Q. Therefore, the second clock enable signal ECS toggled at the rising edge of the third clock generation control signal CPVX is output from the output terminal Q, and the second clock is output from the output bar terminal / Q. The first clock enable signal OCS is out of phase with the enable signal ECS (see FIG. 6).

The first clock enable signal OCS is provided to the first clock voltage applying unit 620, and the second clock enable signal ECS is provided to the second clock voltage applying unit 630.

The first clock voltage applying unit 620 is enabled to the first clock enable signal OCS, and is high level Von when the first clock enable signal OCS is at a high level (see FIG. 6). When the first clock enable signal OCS is at the low level, the first clock signal CKV having the low level Voff is output (see the second section of FIG. 6). In addition, the second clock voltage applying unit 630 is enabled to the second clock enable signal ECS, and when the second clock enable signal ECS is at a high level, it is high level Von (see FIG. 6). When the second clock enable signal ECS is at the low level, the second clock signal CKVB having the low level Voff is output (see the second section of FIG. 6).

Here, the charge sharing unit 640 receives the third clock generation control signal CPVX and shares charges when charging and discharging the first clock signal CKV and the second clock signal CKVB.

More specifically, as shown in FIG. 6, in the first period, the first clock signal CKV is at the high level Von and the second clock signal CKVB is at the low level Voff.

Here, when the third clock generation control signal CPVX becomes low, the first clock signal CKV starts discharging, and the second clock signal CKVB starts charging. That is, in the third section, the first clock signal CKV is discharged and gradually transitions to the low level Voff while sharing the charge, and the second clock signal CKVB is the charge provided from the first clock signal CKV. Is charged and gradually transitions to the high level (Von).

In the second period, the first clock signal CKV becomes the low level Voff and the second clock signal CKVB becomes the high level Von. Next, in the third section, the first clock signal CKV starts charging and the second clock signal CKVB starts discharging again by sharing charges. In this case, the charge sharing period, that is, the third period, is adjusted according to the duty ratio of the third clock generation control signal CPVX. When the duty ratio of the third clock generation control signal CPVX increases, the third section decreases and the second section increases.

Therefore, the first clock signal CKV having the high level Von in the first section is output as the j-1 th gate signal Gout _(j-1) , and the second having the high level Von in the second section. The clock signal CKVB is output as the j-th gate signal Gout _(j) . That is, the j th gate signal Gout _(j) is a time T1 that is the high level of the j-1 th gate signal Gout _(j-1) due to the high level interval of the duty ratio control signal DUCON. Has a time level T2 that is longer than. In the case of the pixel (see PX of FIG. 1) receiving the j-th gate signal Gout _(j) having the increased duty ratio, the display time may be improved by increasing the charging time.

Hereinafter, the data driver 400 outputting the gate signal according to the first clock signal CKV and the second clock signal CKVB provided from the clock generator 600 will be described with reference to FIGS. 7 and 8. . However, the internal circuit of the data driver 400 is not limited thereto.

The gate driver 400 includes a plurality of stages ST ₁ to ST _{n +1} , and each stage ST ₁ to ST _{n + 1} is dependently connected to each other, and the gate signals Gout ₁ to Gout _{(n + 1)} is output, and the gate-off voltage Voff, the first clock signal CKV, the second clock signal CKVB, and the initialization signal INT are input. All stages except the last stage ST _{n +1} are connected one-to-one with a gate line (not shown) of the liquid crystal panel (not shown). Here, the first clock signal CKV and the second clock signal CKVB are signals whose duty ratios are variable as described above.

Each stage ST ₁ to ST _{n +1} includes a first clock terminal CK1, a second clock terminal CK2, a set terminal S, a reset terminal R, a power supply voltage terminal GV, and a frame reset terminal. FR, the gate output terminal OUT1, and the carry output terminal OUT2.

The carry signal Cout _(j-1) of the front stage ST _j-1 is provided to the set terminal S of each stage ST ₁ to ST _{n +1} , for example, the j th stage ST _j . The gate signal Gout _{(j + 1} ) of the rear stage ST _{j +1} is input to the reset terminal R, and the first clock signal is input to the first clock terminal CK1 and the second clock terminal CK2. The CKV and the second clock signal CKVB are input, the gate-off voltage Voff is input to the power supply voltage terminal GV, and the initialization signal INT is input to the frame reset terminal FR. The gate output terminal OUT1 outputs the gate signal Gout ₁ , and the carry output terminal OUT2 outputs the carry signal Cout _(j) . The carry signal Cout _{(n + 1) of the} last stage ST _{n +1} is provided to each stage ST ₁ to ST _{n + 1} as an initialization signal.

However, the scan start signal STVP is input to the first stage ST ₁ instead of the front carry signal, and the scan start signal STVP is input to the last stage ST _{n +1} instead of the rear gate signal.

Here, the j-th stage STj of FIG. 9 will be described in detail with reference to FIG. 8.

Referring to FIG. 8, the j-th stage STj includes the buffer unit 410, the charging unit 420, the pull-up unit 430, the carry signal generator 470, the pull-down unit 440, the discharge unit 450, and the like. The holding unit 460 is included.

The buffer unit 410 has a common drain and gate of the transistor T4 and connects a carry signal Cout _(j-1) of the front stage ST _{n -1} input through the set terminal S to a source. The charging unit 420, the carry signal generator 470, the discharge unit 450, and the holding unit 460 are provided.

One end of the charging unit 420 is connected to the source and the discharge unit 450 of the transistor T4, and the other end is formed of a capacitor C1 connected to the gate output terminal OUT1. The charging unit 420 is charged with the carry signal Cout _(j-1 ) of the front stage ST _n-1 .

The pull-up unit 430 may include a transistor having a drain connected to the first clock terminal CK1, a gate connected to one end of the capacitor C1, and a source connected to the other end of the capacitor C1 and the gate output terminal OUT1. T1). When the capacitor C1 of the charging unit 420 is charged, the transistor T1 is turned on, and the first clock signal CKV input through the first clock terminal CK1 is gated through the gate output terminal OUT1. Provided as (Gout _(j) ). That is, when the duty ratio of the first clock signal CKV and the second clock signal CKVB is increased, the duty ratio of the gate signal Gout _(j) is also increased (see FIG. 6).

The carry signal generator 470 includes a transistor T15 and a gate having a drain connected to the first clock terminal CK1, a source connected to the gate output terminal OUT1, and a gate connected to the buffer unit 410. And a capacitor C2 connected to the source. The capacitor C2 is charged in the same manner as the charging unit 420, and when the capacitor C2 is charged, the transistor C2 transfers the first clock signal CKV to the carry signal Cout _(j) through the carry output terminal OUT2. Output

The pull-down unit 440 has a drain connected to the source of the transistor T1 and the other end of the capacitor C1, a source connected to the power supply voltage terminal GV, and a gate connected to the reset terminal R. It includes. The pull-down unit 440 is input through the reset terminal R and then turned on to the gate signal Gout _{(j + 1)} of the stage ST _{j +1} to convert the gate signal Gout _(j ) into a gate-off voltage ( Voff).

The discharge unit 450 has a gate connected to the reset terminal R, a drain connected to one end of the capacitor C1, and a source connected to the power supply voltage terminal GV, so that the gate of the next stage ST _{j +1} is discharged. A transistor T9 for discharging the charging unit 720 in response to the signal Gout _{(j + 1)} , a gate connected to the frame reset terminal FR, a drain connected to one end of the capacitor C1, and a source Is connected to the power supply voltage terminal GV and includes a transistor T6 for discharging the charging unit 420 in response to the initialization signal INT. That is, the discharge unit 450 gates off the charges charged in the capacitor C1 through the source in response to the gate signal Gout _{(j + 1} ) or the initialization signal INT of the next stage ST _{j +1} . Discharge to voltage Voff.

The holding unit 460 maintains the transistor T3 when the gate signal Gout _(j) is at a high level to perform a hold operation, and the gate signal Gout _(j) moves from a high level to a low level. After the conversion, the transistors T3 and T5 are turned on to perform a hold operation.

In more detail, the transistor T3 has a drain connected to the gate output terminal OUT1 and a source connected to the gate off voltage Voff. The transistors T7 and T8 are turned on when the gate signal Gout _(j) output through the gate output terminal OUT1 is at a high level to pull down the gate of the transistor T3 to the gate-off voltage Voff to turn off. Therefore, the high level of the gate signal Gout _(j) is held.

The transistor T11 has a drain connected to the set terminal S, a gate connected to the second clock terminal CK2, and a source connected to one end of the capacitor C1. The transistor T10 has a drain connected to the source of the transistor T11 and one end of the capacitor C1, a gate connected to the first clock terminal CK1, and a source connected to the gate output terminal OUT1. The transistor T5 has a drain connected to the gate output terminal OUT1, a gate connected to the second clock terminal CK2 in common with the gate of the transistor T11, and a source connected to the power supply voltage terminal GV. .

When the second clock signal CKVB is at the high level, the gate signal Gout _(j) is at a low level and the transistor T5 is turned on to hold the gate output terminal OUT1 at the gate-off voltage Voff. Perform.

The gate driver 400 receives a first clock signal CKV and a second clock signal CKVB having a variable duty ratio, and outputs a gate signal Gout _(j) having a variable duty ratio accordingly. Increasing the duty ratio of the first clock signal CKV and the second clock signal CKVB increases the charging time of each pixel (see PX in FIG. 1), thereby improving display quality. Although the duty ratio of the gate signal is increased by increasing the duty ratio of the second clock generation control signal CPV, the duty ratio of the second clock generation control signal CPV is decreased as necessary. The duty ratio of the signal can be reduced.

Hereinafter, a liquid crystal display according to another exemplary embodiment of the present invention will be described with reference to FIGS. 9 through 11. 9 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention, FIG. 10 is a block diagram illustrating the timing controller of FIG. 9, and FIG. 11 is a timing controller and a clock generator of FIG. 9. It is a signal diagram for explanation. The same reference numerals are used for components that have the same function as the components illustrated in FIGS. 1 to 5, and detailed descriptions of the corresponding components will be omitted for convenience of description.

9, the liquid crystal display 11 according to another exemplary embodiment of the present invention may include a liquid crystal panel 300, a timing controller 501, clock generators 600a and 600b, gate drivers 400a and 400b, and The data driver 700 is included.

Unlike the previous embodiment, it includes two gate drivers 400a and 400b installed in the display unit PA. Each gate driver 400a or 400b is provided at one side and the other side of the display unit DA, and alternately provides gate signals to the plurality of gate lines G1 to Gn. In order to drive the gate drivers 400a and 400b, the timing controller 501 may drive the first clock generation control signal OE, the second clock generation control signals CPV1 and CPV2, and the original scan start signals STV1 and STV2. The clock generators 600a and 600b provide scan start signals STVP1 and STVP2, first clock signals CKV1 and CKV2, and second clock signals CKVB1 and CKVB2 to the gate drivers 400a and 400b. It provides a gate off voltage (Voff).

Here, the timing controller 501 will be described in detail with reference to FIGS. 10 and 11. The timing controller 501 includes a first clock generation control signal generator 511 and a source second clock generation control signal generator ( 521, a duty ratio control signal generator 531, and an OR operator.

The first clock generation control signal generator 511 and the original second clock generation control signal generator 521 respectively control the first clock generation control signals OE1 and OE2 having a predetermined phase difference and the original second clock generation control. Output signals OCPV1 and OCPV2. The duty ratio control signal generator 531 outputs two duty ratio control signals DUCON1 and DUCON2. The OR operator outputs the second clock generation control signals CPV1 and CPV2.

As illustrated in FIG. 11, one duty ratio control signal DUCON1 has a predetermined section at a high level and another duty ratio control signal DUCON2 has a low level. Due to the duty ratio control signals DUCON1 and DUCON2, only one second clock generation control signal CPV1 has a section in which the duty ratio is increased, and the other second clock generation control signal CPV2 is a raw second. The waveform is the same as the clock generation control signal OCPV2.

The second clock generation control signals CPV1 and CPV2 are provided to the clock generation units 600a and 600b, respectively. Each of the clock generation units 600a and 600b generates the third clock generation control signals CPVX1 and CPVX2 as described above.

The j-1 th to j + 2 th gate signals Gout _(j-1) to Gout _{(j + 2} ) are output according to the third clock generation control signals CPVX1 and CPVX2. As described above, during the high level intervals of the respective gate signals Gout _(j-1) to Gout _{(j + 2)} , predetermined intervals may overlap. That is, during the overlapping period, the pixel (see PX of FIG. 9) is precharged.

In addition, the duty ratio of the j-th gate signal Gout _(j-1) is increased by the duty ratio control signal DUCON1 having a high level section. That is, the time T3 which is the high level of the _j- th gate signal Gout _(j-1) is the high level of the other gate signals Gout _(j-1) and Gout _{(j + 1)} Gout _{(j + 2)} . It becomes longer than the phosphorus time T1, T2, and T4.

Therefore, in the case of the pixel (refer to PX in FIG. 9) receiving the _j- th gate signal Gout _(j-1) , the charging time is long, and the display quality is improved.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the liquid crystal display according to the embodiment of the present invention as described above, it is possible to secure the charging time by adjusting the duty ratio of the gate signal, thereby improving the display quality.

Claims (8)

A timing controller configured to output a first clock generation control signal and a second clock generation control signal having a variable duty ratio; A clock generation unit receiving the first clock generation control signal and the second clock generation control signal and outputting a first clock signal and a second clock signal having a different duty ratio and having opposite phases; A gate driver configured to receive the first clock signal and the second clock signal and output a gate signal having a variable duty ratio; And And a liquid crystal panel including a plurality of pixels that receive the gate signal and are turned on / off to display an image. The method of claim 1, The duty ratio of the gate signal increases when the duty ratio of the second clock generation control signal increases, and the duty ratio of the gate signal decreases when the duty ratio of the second clock generation control signal decreases. The method of claim 1, The timing controller generates the original second clock generation control signal and the duty ratio adjustment signal, and the second clock generation control in which the duty ratio is changed through a logical operation of the original second clock generation control signal and the duty ratio adjustment signal. A liquid crystal display device that outputs a signal. The method of claim 3, wherein And the timing controller outputs the second clock generation control signal having a high level increased through a logical sum operation of the original second clock generation control signal and the duty ratio adjustment signal. The method of claim 4, wherein The timing controller may include a duty ratio control signal generator configured to provide the duty ratio control signal, and a logical sum operator configured to receive the original second clock generation control signal and the duty ratio control signal and perform the logical sum operation. Device. The method of claim 1, The third clock generation control signal is a signal obtained by performing an OR operation on the first clock generation control signal and the second clock generation control signal. In a section in which the third clock generation control signal is at a first level, the first and second clock signals are in the first or second level, and in the section in which the third clock generation control signal is in a second level. And first and second clock signals transition from the first level to the second level or from the second level to the first level. The method of claim 6, wherein the clock generator, A logical sum operator configured to receive the first clock generation control signal and the second clock generation control signal and output the third clock generation control signal; A flip-flop for outputting a first clock enable signal whose phase is inverted at each rising edge of the third clock generation control signal and a second clock enable signal that is in phase opposite to the first clock enable signal; A first clock receiving the first clock enable signal and outputting the first level of the first clock signal during the first period, and outputting the second level of the first clock signal during the second period A voltage application unit, A second clock receiving the second clock enable signal and outputting the second level of the second clock signal during the first period, and outputting the first level of the second clock signal during the second period A voltage application unit, And a charge sharing unit configured to receive the third clock generation control signal and control a transition of levels of the first and second clock signals during the third period. The method of claim 1, wherein each pixel, A gate line, a data line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor, the first side being parallel to the gate line and having a length shorter than the first side; A liquid crystal display comprising a pixel electrode having one side and a neighboring second side.

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